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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-25 12:08:07 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-25 12:08:07 +0300 |
| commit | ba73f1ead5db93abe955598f8f7dd9f14a28d8f6 (patch) | |
| tree | 5433ef766569990af4ed0f0bddfc0c5894809a44 | |
| parent | de4e3db2705813e3630ee95ce2d4a6740a757cd4 (diff) | |
| parent | 49991cca67d584a59cb10d48825cce3d11f7d843 (diff) | |
| download | linux-ba73f1ead5db93abe955598f8f7dd9f14a28d8f6.tar.xz | |
Merge tag 'renesas-r9a08g045-dt-binding-defs-tag2' into renesas-clk-for-v6.13
Renesas RZ/G3S DT Binding Definitions
RTC power domain definition for the Renesas RZ/G3S (R9A08G045) SoC,
shared by driver and DT source files.
| -rw-r--r-- | include/dt-bindings/clock/r9a08g045-cpg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h index 8281e9caf3a9..311521fe4b59 100644 --- a/include/dt-bindings/clock/r9a08g045-cpg.h +++ b/include/dt-bindings/clock/r9a08g045-cpg.h @@ -308,5 +308,6 @@ #define R9A08G045_PD_DDR 64 #define R9A08G045_PD_TZCDDR 65 #define R9A08G045_PD_OTFDE_DDR 66 +#define R9A08G045_PD_RTC 67 #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ |