diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2024-12-28 00:25:11 +0300 |
|---|---|---|
| committer | Neil Armstrong <neil.armstrong@linaro.org> | 2025-02-28 11:16:23 +0300 |
| commit | dbf921861985c8d1db339bc8ad0652b9064f2f84 (patch) | |
| tree | b317461ebb3e443ce4f7d6f378896a7ea71722bb | |
| parent | 802cff460aab9db54eeb1c243e6987dd79f05e61 (diff) | |
| download | linux-dbf921861985c8d1db339bc8ad0652b9064f2f84.tar.xz | |
ARM: dts: amlogic: meson8b: switch to the new PWM controller binding
Use the new PWM controller binding which now relies on passing all
clock inputs available on the SoC (instead of passing the "wanted"
clock input for a given board).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241227212514.1376682-3-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/amlogic/meson8b-ec100.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/amlogic/meson8b-mxq.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/amlogic/meson8b.dtsi | 18 |
4 files changed, 15 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts index 18ea6592b7d7..236999548094 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts @@ -443,8 +443,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts index fb28cb330f17..0bca0b33eea2 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts @@ -162,8 +162,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &uart_AO { diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts index 2aa012f38a3b..1cd2093202ca 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts @@ -347,8 +347,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi index 9e02a97f86a0..0876611ce26a 100644 --- a/arch/arm/boot/dts/amlogic/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -403,8 +403,12 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x86c0 0x10>; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; @@ -674,11 +678,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { |