diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2024-12-28 00:25:10 +0300 |
|---|---|---|
| committer | Neil Armstrong <neil.armstrong@linaro.org> | 2025-02-28 11:16:23 +0300 |
| commit | 802cff460aab9db54eeb1c243e6987dd79f05e61 (patch) | |
| tree | cd18d67cd53748ab339d29770f635a74fbd9605d | |
| parent | 2014c95afecee3e76ca4a56956a936e23283f05b (diff) | |
| download | linux-802cff460aab9db54eeb1c243e6987dd79f05e61.tar.xz | |
ARM: dts: amlogic: meson8: switch to the new PWM controller binding
Use the new PWM controller binding which now relies on passing all
clock inputs available on the SoC (instead of passing the "wanted"
clock input for a given board).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241227212514.1376682-2-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/amlogic/meson8.dtsi | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi index 9ff142d9fe3f..847f7b1f1e96 100644 --- a/arch/arm/boot/dts/amlogic/meson8.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -449,7 +449,11 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; reg = <0x86c0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -699,11 +703,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { |