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12 daysPCI: vmd: Remove MSI-X check on child devicesNam Cao1-3/+0
d7d8ab87e3e7 ("PCI: vmd: Switch to msi_create_parent_irq_domain()") added a WARN_ON sanity check that child devices support MSI-X, because VMD document says [1]: Intel VMD only supports MSIx Interrupts from child devices and therefore the BIOS must enable PCIe Hot Plug and MSIx interrups [sic]. However, the VMD device can't even tell the difference between a child device using MSI and one using MSI-X. Per 185a383ada2e ("x86/PCI: Add driver for Intel Volume Management Device (VMD)"), VMD does not support INTx interrupts, but does support child devices using either MSI or MSI-X. Remove the sanity check to avoid the WARN_ON and allow child devices to use MSI, reported by Ammar. Fixes: d7d8ab87e3e7 ("PCI: vmd: Switch to msi_create_parent_irq_domain()") Link: https://cdrdv2-public.intel.com/776857/VMD_White_Paper.pdf [1] Reported-by: Ammar Faizi <ammarfaizi2@gnuweeb.org> Closes: https://lore.kernel.org/linux-pci/aJXYhfc%2F6DfcqfqF@linux.gnuweeb.org/ Signed-off-by: Nam Cao <namcao@linutronix.de> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Ammar Faizi <ammarfaizi2@gnuweeb.org> Link: https://patch.msgid.link/20250811053935.4049211-1-namcao@linutronix.de
12 daysPCI: xilinx: Fix NULL pointer dereference in xilinx_pcie_intr_handler()Nam Cao1-1/+1
f29861aa301c5 ("PCI: xilinx: Switch to msi_create_parent_irq_domain()") changed xilinx_pcie::msi_domain from child devices' interrupt domain to Xilinx AXI bridge's interrupt domain. However, xilinx_pcie_intr_handler() wasn't changed and still reads Xilinx AXI bridge's interrupt domain from xilinx_pcie::msi_domain->parent. This pointer is NULL now. Update xilinx_pcie_intr_handler() to read the correct interrupt domain pointer. Fixes: f29861aa301c5 ("PCI: xilinx: Switch to msi_create_parent_irq_domain()") Signed-off-by: Nam Cao <namcao@linutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250811054144.4049448-1-namcao@linutronix.de
2025-08-07PCI: vmd: Fix wrong kfree() in vmd_msi_free()Nam Cao1-1/+3
vmd_msi_alloc() allocates struct vmd_irq and stashes it into irq_data->chip_data associated with the VMD's interrupt domain. vmd_msi_free() extracts the pointer by calling irq_get_chip_data() and frees it. irq_get_chip_data() returns the chip_data associated with the top interrupt domain. This worked in the past because VMD's interrupt domain was the top domain. But d7d8ab87e3e7 ("PCI: vmd: Switch to msi_create_parent_irq_domain()") changed the interrupt domain hierarchy so VMD's interrupt domain is not the top domain anymore. irq_get_chip_data() now returns the chip_data at the MSI devices' interrupt domains. It is therefore broken for vmd_msi_free() to kfree() this chip_data. Fix by extracting the chip_data associated with the VMD's interrupt domain. Fixes: d7d8ab87e3e7 ("PCI: vmd: Switch to msi_create_parent_irq_domain()") Reported-by: Kenneth Crudup <kenny@panix.com> Closes: https://lore.kernel.org/linux-pci/dfa40e48-8840-4e61-9fda-25cdb3ad81c1@panix.com/ Reported-by: Ammar Faizi <ammarfaizi2@gnuweeb.org> Closes: https://lore.kernel.org/linux-pci/ed53280ed15d1140700b96cca2734bf327ee92539e5eb68e80f5bbbf0f01@linux.gnuweeb.org/ Tested-by: Ammar Faizi <ammarfaizi2@gnuweeb.org> Tested-by: Kenneth Crudup <kenny@panix.com> Signed-off-by: Nam Cao <namcao@linutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250807081051.2253962-1-namcao@linutronix.de
2025-08-01Merge tag 'pci-v6.17-changes' of ↵Linus Torvalds40-983/+1337
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Allow built-in drivers, not just modular drivers, to use async initial probing (Lukas Wunner) - Support Immediate Readiness even on devices with no PM Capability (Sean Christopherson) - Consolidate definition of PCIE_RESET_CONFIG_WAIT_MS (100ms), the required delay between a reset and sending config requests to a device (Niklas Cassel) - Add pci_is_display() to check for "Display" base class and use it in ALSA hda, vfio, vga_switcheroo, vt-d (Mario Limonciello) - Allow 'isolated PCI functions' (multi-function devices without a function 0) for LoongArch, similar to s390 and jailhouse (Huacai Chen) Power control: - Add ability to enable optional slot clock for cases where the PCIe host controller and the slot are supplied by different clocks (Marek Vasut) PCIe native device hotplug: - Fix runtime PM ref imbalance on Hot-Plug Capable ports caused by misinterpreting a config read failure after a device has been removed (Lukas Wunner) - Avoid creating a useless PCIe port service device for pciehp if the slot is handled by the ACPI hotplug driver (Lukas Wunner) - Ignore ACPI hotplug slots when calculating depth of pciehp hotplug ports (Lukas Wunner) Virtualization: - Save VF resizable BAR state and restore it after reset (Michał Winiarski) - Allow IOV resources (VF BARs) to be resized (Michał Winiarski) - Add pci_iov_vf_bar_set_size() so drivers can control VF BAR size (Michał Winiarski) Endpoint framework: - Add RC-to-EP doorbell support using platform MSI controller, including a test case (Frank Li) - Allow BAR assignment via configfs so platforms have flexibility in determining BAR usage (Jerome Brunet) Native PCIe controller drivers: - Convert amazon,al-alpine-v[23]-pcie, apm,xgene-pcie, axis,artpec6-pcie, marvell,armada-3700-pcie, st,spear1340-pcie to DT schema format (Rob Herring) - Use dev_fwnode() instead of of_fwnode_handle() to remove OF dependency in altera (fixes an unused variable), designware-host, mediatek, mediatek-gen3, mobiveil, plda, xilinx, xilinx-dma, xilinx-nwl (Jiri Slaby, Arnd Bergmann) - Convert aardvark, altera, brcmstb, designware-host, iproc, mediatek, mediatek-gen3, mobiveil, plda, rcar-host, vmd, xilinx, xilinx-dma, xilinx-nwl from using pci_msi_create_irq_domain() to using msi_create_parent_irq_domain() instead; this makes the interrupt controller per-PCI device, allows dynamic allocation of vectors after initialization, and allows support of IMS (Nam Cao) APM X-Gene PCIe controller driver: - Rewrite MSI handling to MSI CPU affinity, drop useless CPU hotplug bits, use device-managed memory allocations, and clean things up (Marc Zyngier) - Probe xgene-msi as a standard platform driver rather than a subsys_initcall (Marc Zyngier) Broadcom STB PCIe controller driver: - Add optional DT 'num-lanes' property and if present, use it to override the Maximum Link Width advertised in Link Capabilities (Jim Quinlan) Cadence PCIe controller driver: - Use PCIe Message routing types from the PCI core rather than defining private ones (Hans Zhang) Freescale i.MX6 PCIe controller driver: - Add IMX8MQ_EP third 64-bit BAR in epc_features (Richard Zhu) - Add IMX8MM_EP and IMX8MP_EP fixed 256-byte BAR 4 in epc_features (Richard Zhu) - Configure LUT for MSI/IOMMU in Endpoint mode so Root Complex can trigger doorbel on Endpoint (Frank Li) - Remove apps_reset (LTSSM_EN) from imx_pcie_{assert,deassert}_core_reset(), which fixes a hotplug regression on i.MX8MM (Richard Zhu) - Delay Endpoint link start until configfs 'start' written (Richard Zhu) Intel VMD host bridge driver: - Add Intel Panther Lake (PTL)-H/P/U Vendor ID (George D Sworo) Qualcomm PCIe controller driver: - Add DT binding and driver support for SA8255p, which supports ECAM for Configuration Space access (Mayank Rana) - Update DT binding and driver to describe PHYs and per-Root Port resets in a Root Port stanza and deprecate describing them in the host bridge; this makes it possible to support multiple Root Ports in the future (Krishna Chaitanya Chundru) - Add Qualcomm QCS615 to SM8150 DT binding (Ziyue Zhang) - Add Qualcomm QCS8300 to SA8775p DT binding (Ziyue Zhang) - Drop TBU and ref clocks from Qualcomm SM8150 and SC8180x DT bindings (Konrad Dybcio) - Document 'link_down' reset in Qualcomm SA8775P DT binding (Ziyue Zhang) - Add required PCIE_RESET_CONFIG_WAIT_MS delay after Link up IRQ (Niklas Cassel) Rockchip PCIe controller driver: - Drop unused PCIe Message routing and code definitions (Hans Zhang) - Remove several unused header includes (Hans Zhang) - Use standard PCIe config register definitions instead of rockchip-specific redefinitions (Geraldo Nascimento) - Set Target Link Speed to 5.0 GT/s before retraining so we have a chance to train at a higher speed (Geraldo Nascimento) Rockchip DesignWare PCIe controller driver: - Prevent race between link training and register update via DBI by inhibiting link training after hot reset and link down (Wilfred Mallawa) - Add required PCIE_RESET_CONFIG_WAIT_MS delay after Link up IRQ (Niklas Cassel) Sophgo PCIe controller driver: - Add DT binding and driver for Sophgo SG2044 PCIe controller driver in Root Complex mode (Inochi Amaoto) Synopsys DesignWare PCIe controller driver: - Add required PCIE_RESET_CONFIG_WAIT_MS after waiting for Link up on Ports that support > 5.0 GT/s. Slower Ports still rely on the not-quite-correct PCIE_LINK_WAIT_SLEEP_MS 90ms default delay while waiting for the Link (Niklas Cassel)" * tag 'pci-v6.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (116 commits) dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset dt-bindings: PCI: Remove 83xx-512x-pci.txt dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema dt-bindings: PCI: Convert apm,xgene-pcie to DT schema dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema dt-bindings: PCI: Convert st,spear1340-pcie to DT schema PCI: Move is_pciehp check out of pciehp_is_native() PCI: pciehp: Use is_pciehp instead of is_hotplug_bridge PCI/portdrv: Use is_pciehp instead of is_hotplug_bridge PCI/ACPI: Fix runtime PM ref imbalance on Hot-Plug Capable ports selftests: pci_endpoint: Add doorbell test case misc: pci_endpoint_test: Add doorbell test case PCI: endpoint: pci-epf-test: Add doorbell test support PCI: endpoint: Add pci_epf_align_inbound_addr() helper for inbound address alignment PCI: endpoint: pci-ep-msi: Add checks for MSI parent and mutability PCI: endpoint: Add RC-to-EP doorbell support using platform MSI controller PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode PCI: vmd: Switch to msi_create_parent_irq_domain() PCI: vmd: Convert to lock guards ...
2025-08-01Merge branch 'pci/misc'Bjorn Helgaas1-1/+1
- Remove resolved hotplug TODO item (Guilherme Giacomo Simoes) - Fix typos (Bjorn Helgaas) * pci/misc: PCI: Fix typos PCI: hotplug: Remove TODO about unused .get_power(), .hardware_test()
2025-08-01Merge branch 'pci/controller/xgene'Bjorn Helgaas2-281/+180
- Teach handle_simple_irq() to resend an in-progress interrupt (Marc Zyngier) - Defer probing if the MSI widget driver hasn't probed yet (Marc Zyngier) - Drop useless conditional compilation, since pci-xgene.c is only compiled when CONFIG_PCI_XGENE is selected (Marc Zyngier) - Drop useless XGENE_PCIE_IP_VER_UNKN IP version (Marc Zyngier) - Simplify and make per-CPU interrupt setup robust (Marc Zyngier) - Drop superfluous struct xgene_msi fields (Marc Zyngier) - Use device-managed memory allocations (Marc Zyngier) - Drop intermediate xgene_msi_group tracking structure (Marc Zyngier) - Rewrite pci-xgene-msi.c to fix MSI CPU affinity and clean things up (Marc Zyngier) - Resend an MSI racing with itself on a different CPU (Marc Zyngier) - Probe xgene-msi as a standard platform driver rather than a subsys_initcall (Marc Zyngier) - Simplify MSI handler setup/teardown by dropping useless CPU hotplug bits (Marc Zyngier) - Remove unused cpuhp_state CPUHP_PCI_XGENE_DEAD (Marc Zyngier) * pci/controller/xgene: cpu/hotplug: Remove unused cpuhp_state CPUHP_PCI_XGENE_DEAD PCI: xgene-msi: Restructure handler setup/teardown PCI: xgene-msi: Probe as a standard platform driver PCI: xgene-msi: Resend an MSI racing with itself on a different CPU PCI: xgene-msi: Sanitise MSI allocation and affinity setting PCI: xgene-msi: Get rid of intermediate tracking structure PCI: xgene-msi: Use device-managed memory allocations PCI: xgene-msi: Drop superfluous fields from xgene_msi structure PCI: xgene-msi: Make per-CPU interrupt setup robust PCI: xgene: Drop XGENE_PCIE_IP_VER_UNKN PCI: xgene: Drop useless conditional compilation PCI: xgene: Defer probing if the MSI widget driver hasn't probed yet genirq: Teach handle_simple_irq() to resend an in-progress interrupt
2025-08-01Merge branch 'pci/controller/vmd'Bjorn Helgaas1-0/+2
- Add Intel Panther Lake (PTL)-H/P/U Vendor ID (George D Sworo) * pci/controller/vmd: PCI: vmd: Add VMD Device ID Support for Panther Lake (PTL)-H/P/U
2025-08-01Merge branch 'pci/controller/sophgo'Bjorn Helgaas3-0/+268
- Add DT binding and driver for Sophgo SG2044 PCIe controller driver in Root Complex mode (Inochi Amaoto) * pci/controller/sophgo: PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode dt-bindings: pci: Add Sophgo SG2044 PCIe host
2025-08-01Merge branch 'pci/controller/rockchip-host'Bjorn Helgaas1-11/+2
- Fix log message that said "malformed TLP" when it should have said "Unexpected Completion" (Hans Zhang) - Fix log message that said "no fatal error" when it should have said "non fatal error" (Hans Zhang) - Remove several unused header includes (Hans Zhang) * pci/controller/rockchip-host: PCI: rockchip-host: Remove unused header includes PCI: rockchip-host: Correct non-fatal error log message PCI: rockchip-host: Fix "Unexpected Completion" log message
2025-08-01Merge branch 'pci/controller/rockchip'Bjorn Helgaas3-49/+30
- Drop unused PCIe Message routing and code definitions (Hans Zhang) - Use standard PCIe config register definitions instead of rockchip-specific redefinitions (Geraldo Nascimento) - Set Target Link Speed to 5.0 GT/s before retraining so we have a chance to train at a higher speed (Geraldo Nascimento) * pci/controller/rockchip: PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining PCI: rockchip: Use standard PCIe definitions PCI: rockchip: Remove redundant PCIe message routing definitions
2025-08-01Merge branch 'pci/controller/qcom'Bjorn Helgaas6-59/+327
- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM implementation (Mayank Rana) - Rename gen_pci_init() to pci_host_common_ecam_create() and export for use by controller drivers (Mayank Rana) - Add DT binding and driver support for SA8255p, which supports ECAM for Configuration Space access (Mayank Rana) - Update DT binding and driver to describe PHYs and per-Root Port resets in a Root Port stanza and deprecate describing them in the host bridge; this makes it possible to support multiple Root Ports in the future (Krishna Chaitanya Chundru) * pci/controller/qcom: PCI: qcom: Add support for parsing the new Root Port binding dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers PCI: dwc: Export DWC MSI controller related APIs
2025-08-01Merge branch 'pci/controller/mvebu'Bjorn Helgaas1-4/+2
- Use devm_add_action_or_reset() when adding port->clk devm cleanup action so we don't have to explicitly call clk_put() (Salah Triki) * pci/controller/mvebu: PCI: mvebu: Use devm_add_action_or_reset() instead of devm_add_action()
2025-08-01Merge branch 'pci/controller/imx6'Bjorn Helgaas1-14/+26
- Add IMX8MQ_EP third 64-bit BAR in epc_features (Richard Zhu) - Add IMX8MM_EP and IMX8MP_EP fixed 256-byte BAR 4 in epc_features (Richard Zhu) - Factor imx_pcie_add_lut_by_rid() out of imx_pcie_enable_device() for use by LUT configuration (Frank Li) - Configure LUT for MSI/IOMMU in Endpoint mode so Root Complex can trigger doorbel on Endpoint (Frank Li) - Remove apps_reset (LTSSM_EN) from imx_pcie_{assert,deassert}_core_reset(), which fixes a hotplug regression on i.MX8MM (Richard Zhu) - Delay Endpoint link start until configfs 'start' written (Richard Zhu) * pci/controller/imx6: PCI: imx6: Delay link start until configfs 'start' written PCI: imx6: Remove apps_reset toggling from imx_pcie_{assert/deassert}_core_reset PCI: imx6: Add LUT configuration for MSI/IOMMU in Endpoint mode PCI: imx6: Add helper function imx_pcie_add_lut_by_rid() PCI: imx6: Add IMX8MM_EP and IMX8MP_EP fixed 256-byte BAR 4 in epc_features PCI: imx6: Add IMX8MQ_EP third 64-bit BAR in epc_features
2025-08-01Merge branch 'pci/controller/dw-rockchip'Bjorn Helgaas1-3/+12
- Prevent race between link training and register update via DBI by inhibiting link training after hot reset and link down (Wilfred Mallawa) * pci/controller/dw-rockchip: PCI: dw-rockchip: Delay link training after hot reset in EP mode
2025-08-01Merge branch 'pci/controller/dwc'Bjorn Helgaas1-8/+8
- Simplify debugfs 'return' statements (Hans Zhang) - Make dw_pcie_ptm_ops static (Manivannan Sadhasivam) * pci/controller/dwc: PCI: dwc: Make dw_pcie_ptm_ops static PCI: dwc: Simplify the return value of PTM debugfs functions returning bool
2025-08-01Merge branch 'pci/controller/cadence'Bjorn Helgaas2-21/+1
- Use PCIe Message routing types from the PCI core rather than defining private ones (Hans Zhang) * pci/controller/cadence: PCI: cadence: Replace private message routing enums with PCI core definitions
2025-08-01Merge branch 'pci/controller/brcmstb'Bjorn Helgaas1-6/+27
- Add optional DT 'num-lanes' property and if present, use it to override the Maximum Link Width advertised in Link Capabilities (Jim Quinlan) * pci/controller/brcmstb: PCI: brcmstb: Replace open coded value with PCIE_T_RRS_READY_MS MAINTAINERS: Drop Nicolas from maintaining pcie-brcmstb PCI: brcmstb: Set MLW based on "num-lanes" DT property if present dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
2025-08-01Merge branch 'pci/controller/linkup-fix'Bjorn Helgaas6-9/+15
- Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS (the required delay before sending config requests after a reset) (Niklas Cassel) - PCIE_T_RRS_READY_MS and PCIE_RESET_CONFIG_WAIT_MS were two names for the same delay; replace PCIE_T_RRS_READY_MS with PCIE_RESET_CONFIG_WAIT_MS and remove PCIE_T_RRS_READY_MS (Niklas Cassel) - Add required PCIE_RESET_CONFIG_WAIT_MS delay after Link up IRQ to dw-rockchip, qcom (Niklas Cassel) - Add required PCIE_RESET_CONFIG_WAIT_MS after waiting for Link up on Ports that support > 5.0 GT/s in dwc core (Niklas Cassel) - Move LINK_WAIT_SLEEP_MS and LINK_WAIT_MAX_RETRIES to pci.h and prefix with 'PCIE_' for potential sharing across drivers (Niklas Cassel) * pci/controller/linkup-fix: PCI: Move link up wait time and max retries macros to pci.h PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS
2025-07-25PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex modeInochi Amaoto3-0/+268
Add driver support for DesignWare based PCIe controller in SG2044 SoC. The driver currently supports the Root Complex mode. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> [mani: renamed the driver to 'pcie-sophgo.c' and Kconfig fix] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: whitespace] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250504004420.202685-3-inochiama@gmail.com
2025-07-25PCI: vmd: Switch to msi_create_parent_irq_domain()Nam Cao2-80/+91
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, wrap long lines, squash fix from https://lore.kernel.org/r/20250716201216.TsY3Kn45@linutronix.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/de3f1d737831b251e9cd2cbf9e4c732a5bbba13a.1750858083.git.namcao@linutronix.de
2025-07-25PCI: vmd: Convert to lock guardsNam Cao1-44/+29
Convert lock/unlock pairs to lock guard and tidy up the code. Signed-off-by: Nam Cao <namcao@linutronix.de> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/836cca37449c70922a2bea1fb13f37940a7a7132.1750858083.git.namcao@linutronix.de
2025-07-25PCI: plda: Switch to msi_create_parent_irq_domain()Nam Cao3-24/+23
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/1279fe6500a1d8135d8f5feb2f055df008746c88.1750858083.git.namcao@linutronix.de
2025-07-25PCI: xilinx: Switch to msi_create_parent_irq_domain()Nam Cao2-25/+32
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/b1353c797ce53714c22823de3bd2ae3d09fcd84f.1750858083.git.namcao@linutronix.de
2025-07-25PCI: xilinx-nwl: Switch to msi_create_parent_irq_domain()Nam Cao2-23/+24
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/5ac6e216bf2eaa438c8854baf2ff3e5cf0b2284f.1750858083.git.namcao@linutronix.de
2025-07-25PCI: xilinx-xdma: Switch to msi_create_parent_irq_domain()Nam Cao2-28/+22
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/b4620dc1808f217a69d0ae50700ffa12ffd657eb.1750858083.git.namcao@linutronix.de
2025-07-25PCI: rcar-host: Switch to msi_create_parent_irq_domain()Nam Cao2-45/+26
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/ab4005db0a829549be1f348f6c27be50a2118b5e.1750858083.git.namcao@linutronix.de
2025-07-25PCI: mediatek: Switch to msi_create_parent_irq_domain()Nam Cao2-26/+23
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/76f6e6ce6021607cd0fdfd79fef7d2eb69d9f361.1750858083.git.namcao@linutronix.de
2025-07-25PCI: mediatek-gen3: Switch to msi_create_parent_irq_domain()Nam Cao2-42/+26
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message & fixed merge conflict] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/bfbd2e375269071b69e1aa85e629ee4b7c99518f.1750858083.git.namcao@linutronix.de
2025-07-25PCI: iproc: Switch to msi_create_parent_irq_domain()Nam Cao2-25/+22
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message & squashed the kdoc cleanup patch] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/53946d74caf1fd134a1820eac82c3cf64d48779f.1750858083.git.namcao@linutronix.de
2025-07-25PCI: brcmstb: Switch to msi_create_parent_irq_domain()Nam Cao2-23/+23
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/fa72703e06c2ee2c7554082c7152913eb0dd294f.1750858083.git.namcao@linutronix.de
2025-07-25PCI: altera-msi: Switch to msi_create_parent_irq_domain()Nam Cao2-24/+22
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/0a88da04bb82bd588828a7889e9d58c515ea5dbb.1750858083.git.namcao@linutronix.de
2025-07-25PCI: aardvark: Switch to msi_create_parent_irq_domain()Nam Cao2-36/+24
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/68b2f9387bbe4f08bcd428bfab83ad1219fb8d80.1750858083.git.namcao@linutronix.de
2025-07-25PCI: mobiveil: Switch to msi_create_parent_irq_domain()Nam Cao3-22/+23
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/af46c15c47a7716f7e0c50d0f7391509c95b49c2.1750858083.git.namcao@linutronix.de
2025-07-25PCI: dwc: Switch to msi_create_parent_irq_domain()Nam Cao3-46/+25
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <namcao@linutronix.de> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/04d4a96046490e50139826c16423954e033cdf89.1750858083.git.namcao@linutronix.de
2025-07-25PCI: controller: Use dev_fwnode() instead of of_fwnode_handle()Jiri Slaby (SUSE)9-14/+11
All irq_domain functions now accept fwnode instead of of_node. But many PCI controllers still extract dev to of_node and then of_node to fwnode. Instead, clean this up and simply use the dev_fwnode() helper to extract fwnode directly from dev. Internally, it still does dev => of_node => fwnode steps, but it's now hidden from the users. In the case of altera, this also removes an unused 'node' variable that is only used when CONFIG_OF is enabled: drivers/pci/controller/pcie-altera.c: In function 'altera_pcie_init_irq_domain': drivers/pci/controller/pcie-altera.c:855:29: error: unused variable 'node' [-Werror=unused-variable] 855 | struct device_node *node = dev->of_node; Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> # altera [bhelgaas: squash together, rebase to precede msi-parent] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250521163329.2137973-1-arnd@kernel.org Link: https://patch.msgid.link/20250611104348.192092-16-jirislaby@kernel.org Link: https://patch.msgid.link/20250723065907.1841758-1-jirislaby@kernel.org
2025-07-24Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski2-2/+20
Cross-merge networking fixes after downstream PR (net-6.16-rc8). Conflicts: drivers/net/ethernet/microsoft/mana/gdma_main.c 9669ddda18fb ("net: mana: Fix warnings for missing export.h header inclusion") 755391121038 ("net: mana: Allocate MSI-X vectors dynamically") https://lore.kernel.org/20250711130752.23023d98@canb.auug.org.au Adjacent changes: drivers/net/ethernet/ti/icssg/icssg_prueth.h 6e86fb73de0f ("net: ti: icssg-prueth: Fix buffer allocation for ICSSG") ffe8a4909176 ("net: ti: icssg-prueth: Read firmware-names from device tree") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-24PCI: imx6: Delay link start until configfs 'start' writtenRichard Zhu1-3/+0
According to Documentation/PCI/endpoint/pci-endpoint-cfs.rst, the Endpoint controller (EPC) should only start the link when userspace writes '1' to the '/sys/kernel/config/pci_ep/controllers/<EPC>/start' attribute, which ultimately results in calling imx_pcie_start_link() via pci_epc_start_store(). To align with the documented behavior, do not start the link automatically when adding the EP controller. Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> [mani: reworded commit subject and description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250709033722.2924372-3-hongxing.zhu@nxp.com
2025-07-24PCI: imx6: Remove apps_reset toggling from imx_pcie_{assert/deassert}_core_resetRichard Zhu1-2/+3
apps_reset corresponds to LTSSM_EN in i.MX7, i.MX8MQ, i.MX8MM and i.MX8MP platforms. Since assertion/de-assertion of apps_reset is done in imx_pcie_ltssm_enable() and imx_pcie_ltssm_disable(), remove it from imx_pcie_assert_core_reset() and imx_pcie_deassert_core_reset(). This also fixes a failure in enumerating the PI7C9X2G608GP (hotplug) chip reliably on i.MX8MM, as reported by Tim. It should be noted that only i.MX7D, i.MX8MQ, i.MX8MM, and i.MX8MP platforms have the apps_reset logic, so this change doesn't have any effect on other platforms. Fixes: ef61c7d8d032 ("PCI: imx6: Deassert apps_reset in imx_pcie_deassert_core_reset()") Reported-by: Tim Harvey <tharvey@gateworks.com> Closes: https://lore.kernel.org/all/CAJ+vNU3ohR2YKTwC4xoYrc1z-neDoH2TTZcMHDy+poj9=jSy+w@mail.gmail.com/ Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> [mani: reworded commit subject and description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mp-venice-gw74xx (i.MX8MP + hotplug capable switch) Reviewed-by: Frank Li <Frank.Li@nxp.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250709033722.2924372-2-hongxing.zhu@nxp.com
2025-07-23PCI: Fix typosBjorn Helgaas1-1/+1
Fix typos. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20250722213743.2822761-1-helgaas@kernel.org
2025-07-23PCI: mvebu: Use devm_add_action_or_reset() instead of devm_add_action()Salah Triki1-4/+2
Replace devm_add_action() with devm_add_action_or_reset() to avoid explicitly dropping the 'port->clk' reference in error path. Signed-off-by: Salah Triki <salah.triki@gmail.com> [mani: reworded commit subject and description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/aHsgYALHfQbrgq0t@pc
2025-07-22PCI: xgene-msi: Restructure handler setup/teardownMarc Zyngier1-70/+37
Another utterly pointless aspect of the xgene-msi driver is that it is built around CPU hotplug. Which is quite amusing since this is one of the few arm64 platforms that, by construction, cannot do CPU hotplug in a supported way (no EL3, no PSCI, no luck). Drop the CPU hotplug nonsense and just setup the IRQs and handlers in a less overdesigned way, grouping things more logically in the process. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-13-maz@kernel.org
2025-07-22PCI: xgene-msi: Probe as a standard platform driverMarc Zyngier1-6/+1
Now that we have made the dependency between the PCI driver and the MSI driver explicit, there is no need to use subsys_initcall() as a probing hook, and we can rely on builtin_platform_driver() instead. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-12-maz@kernel.org
2025-07-22PCI: xgene-msi: Resend an MSI racing with itself on a different CPUMarc Zyngier1-0/+1
Since changing the affinity of an MSI really is about changing the target address and that it isn't possible to mask an individual MSI, it is completely possible for an interrupt to race with itself, usually resulting in a lost interrupt. Paper over the design blunder by informing the core code of this sad state of affairs. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-11-maz@kernel.org
2025-07-22PCI: xgene-msi: Sanitise MSI allocation and affinity settingMarc Zyngier1-129/+93
Plugging a device that doesn't use managed affinity on an XGene-1 machine results in messages such as: genirq: irq_chip PCI-MSIX-0000:01:00.0 did not update eff. affinity mask of irq 39 As it turns out, the driver was never updated to populate the effective affinity on irq_set_affinity() call, and the core code is prickly about that. But upon further investigation, it appears that the driver keeps repainting the hwirq field of the irq_data structure as a way to track the affinity of the MSI, something that is very much frowned upon as it breaks the fundamentals of an IRQ domain (an array indexed by hwirq). Fixing this results more or less in a rewrite of the driver: - Define how a hwirq and a CPU affinity map onto the MSI termination registers - Allocate a single entry in the bitmap per MSI instead of *8* - Correctly track CPU affinity - Fix the documentation so that it actually means something (to me) - Use standard bitmap iterators - and plenty of other cleanups With this, the driver behaves correctly on my vintage Mustang board. Signed-off-by: Marc Zyngier <maz@kernel.org> [lpieralisi: replaced open coded GENMASK(6, 4) with MSInRx_HWIRQ_MASK] Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-10-maz@kernel.org
2025-07-22PCI: xgene-msi: Get rid of intermediate tracking structureMarc Zyngier1-42/+18
The xgene-msi driver uses an odd construct in the form of an intermediate tracking structure, evidently designed to deal with multiple instances of the MSI widget. However, the existing HW only has one set, and it is obvious that there won't be new HW coming down that particular line. Simplify the driver by using a bit of pointer arithmetic instead, directly tracking the interrupt and avoiding extra memory allocation. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-9-maz@kernel.org
2025-07-22PCI: xgene-msi: Use device-managed memory allocationsMarc Zyngier1-18/+19
Since the MSI driver is probed as a platform device, there is no reason to not use device-managed allocations. That's including the top-level bookkeeping structure, which is better dynamically allocated than being static. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-8-maz@kernel.org
2025-07-22PCI: xgene-msi: Drop superfluous fields from xgene_msi structureMarc Zyngier1-13/+10
The xgene_msi structure remembers both the of_node of the device and the number of CPUs. All of which are perfectly useless. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-7-maz@kernel.org
2025-07-22PCI: xgene-msi: Make per-CPU interrupt setup robustMarc Zyngier1-23/+6
The way the per-CPU interrupts are dealt with in the XGene MSI driver isn't great: - the affinity is set after the interrupt is enabled - nothing prevents userspace from moving the interrupt around - the affinity setting code pointlessly allocates memory - the driver checks for conditions that cannot possibly happen Address all of this in one go, resulting in slightly simpler setup code. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-6-maz@kernel.org
2025-07-22PCI: xgene: Drop XGENE_PCIE_IP_VER_UNKNMarc Zyngier1-5/+1
XGENE_PCIE_IP_VER_UNKN is only refered to when probing for the original XGene PCIe implementation, and get immediately overridden if the device has the "apm,xgene-pcie" compatible string. Given that the only way to get there is by finding this very string in the DT, it is obvious that we will always overwrite the version with XGENE_PCIE_IP_VER_1. Drop the whole thing. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-5-maz@kernel.org
2025-07-22PCI: xgene: Drop useless conditional compilationMarc Zyngier1-4/+0
pci-xgene.c only gets compiled if CONFIG_PCI_XGENE is selected. It is therefore pointless to check for CONFIG_PCI_XGENE inside the driver. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-4-maz@kernel.org
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-24 20:05:39 +0300