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path: root/drivers/gpu/drm/msm/adreno
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2025-08-07drm/msm: Fix a7xx TPL1 cluster snapshotRob Clark2-2/+11
Later gens have both a PIPE_BR and PIPE_NONE section. The snapshot tool seems to expect this for x1-85 as well. I guess this was just a bug in downstream kgsl, which went unnoticed? Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/666662/
2025-08-07drm/msm: Fix debugbus snapshotRob Clark1-1/+2
We weren't setting the # of captured debugbus blocks. Reported-by: Connor Abbott <cwabbott0@gmail.com> Suggested-by: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/666660/
2025-08-07drm/msm: Fix a7xx debugbus readRob Clark1-8/+24
The bitfield positions changed in a7xx. v2: Don't open-code the bitfield building v3: Also fix cx_debugbus Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/666659/
2025-08-07drm/msm: Constify snapshot tablesRob Clark4-14/+14
A bit of divergence from the downstream driver from which these headers were imported. But no need for these tables not to be const. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/666656/
2025-08-07drm/msm: Fix order of selector programming in cluster snapshotRob Clark1-4/+4
Program the selector _after_ selecting the aperture. This aligns with the downstream driver, and fixes a case where we were failing to capture ctx0 regs (and presumably what we thought were ctx1 regs were actually ctx0). Suggested-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/666655/
2025-08-07drm/msm: Fix section names and sizesRob Clark2-31/+31
The section names randomly appended _DATA or _ADDR in many cases, and/or didn't match the reg names. Fix them so crashdec can properly resolve the section names back to reg names. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/666654/
2025-08-07drm/msm: Add missing "location"s to devcoredumpRob Clark1-0/+2
This is needed to properly interpret some of the sections. v2: Fix missing \n Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/666651/
2025-07-05drm/msm: enable separate binding of GPU and display devicesDmitry Baryshkov1-1/+2
There are cases when we want to have separate DRM devices for GPU and display pipelines. One example is development, when it is beneficial to be able to bind the GPU driver separately, without the display pipeline (and without the hacks adding "amd,imageon" to the compatible string). Another example is some of Qualcomm platforms, which have two MDSS units, but only one GPU. With current approach it is next to impossible to support this usecase properly, while separate binding allows users to have three DRM devices: two for MDSS units and a single headless GPU. Add kernel param msm.separate_gpu_kms, which if set to true forces creation of separate display and GPU DRM devices. Mesa supports this setup by using the kmsro wrapper. The param is disabled by default, in order to be able to test userspace for the compatibility issues. Simple clients are able to handle this setup automatically. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/662590/ [Rob: renamed the modparam to separate_gpu_kms, and add missing DRIVER_GEM_GPUVA] Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm: rework binding of Imageon GPUsDmitry Baryshkov1-28/+8
Currently the msm driver creates an extra interim platform device for Imageon GPUs. This is not ideal, as the device doesn't have corresponding OF node. If the headless mode is used for newer GPUs, then the msm_use_mmu() function can not detect corresponding IOMMU devices. Also the DRM device (although it's headless) is created with modesetting flags being set. To solve all these issues, rework the way the Imageon devices are bound. Remove the interim device, don't register a component and instead use a cut-down version of the normal functions to probe or remove the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/662584/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/adreno: Switch to the common UBWC config structKonrad Dybcio4-86/+59
Now that Adreno specifics are out of the way, use the common config (but leave the HBB hardcoding in place until that is wired up on the other side). Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660985/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05soc: qcom: ubwc: Add #defines for UBWC swizzle bitsKonrad Dybcio1-1/+1
Make the values a bit more meaningful. This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660981/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/a6xx: Simplify min_acc_len calculationKonrad Dybcio1-9/+9
It's only necessary for some lower end parts. Also rename it to min_acc_len_64b to denote that if set, the minimum access length is 64 bits, 32b otherwise. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660977/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/a6xx: Resolve the meaning of rgb565_predicatorKonrad Dybcio1-5/+2
It's supposed to be on when the UBWC encoder version is >= 4.0. Drop the per-GPU assignments. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660975/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calcKonrad Dybcio1-1/+1
ubwc_swizzle is a bitmask. Check for a bit to make it more obvious. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660973/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/a6xx: Resolve the meaning of UBWC_MODEKonrad Dybcio1-1/+1
This bit is set iff the UBWC version is 1.0. That notably does not include QCM2290's "no UBWC". This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660971/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/a6xx: Simplify uavflagprd_inv detectionKonrad Dybcio1-9/+6
Instead of setting it on a gpu-per-gpu basis, converge it to the intended "is A650 family or A7xx". Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660969/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/a6xx: Resolve the meaning of AMSBCKonrad Dybcio1-9/+3
The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it as a separate field. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660967/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm/a6xx: Get a handle to the common UBWC configKonrad Dybcio2-2/+17
Start the great despaghettification by getting a pointer to the common UBWC configuration, which houses e.g. UBWC versions that we need to make decisions. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660965/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-05drm/msm: Update register xmlRob Clark6-6/+10
Sync register xml from mesa commit eb3e0b7164a3 ("freedreno/a6xx: Split descriptors out into their own file"). Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/662470/
2025-07-05drm/msm: Add VM logging for VM_BIND updatesRob Clark1-0/+11
When userspace opts in to VM_BIND, the submit no longer holds references keeping the VMA alive. This makes it difficult to distinguish between UMD/KMD/app bugs. So add a debug option for logging the most recent VM updates and capturing these in GPU devcoredumps. The submitqueue id is also captured, a value of zero means the operation did not go via a submitqueue (ie. comes from msm_gem_vm_close() tearing down the remaining mappings when the device file is closed. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661518/
2025-07-05drm/msm: Support IO_PGTABLE_QUIRK_NO_WARN_ONRob Clark1-1/+1
With user managed VMs and multiple queues, it is in theory possible to trigger map/unmap errors. These will (in a later patch) mark the VM as unusable. But we want to tell the io-pgtable helpers not to spam the log. In addition, in the unmap path, we don't want to bail early from the unmap, to ensure we don't leave some dangling pages mapped. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661520/
2025-07-05drm/msm: Add opt-in for VM_BINDRob Clark2-2/+17
Add a SET_PARAM for userspace to request to manage to the VM itself, instead of getting a kernel managed VM. In order to transition to a userspace managed VM, this param must be set before any mappings are created. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661494/
2025-07-05drm/msm: Lazily create context VMRob Clark2-7/+10
In the next commit, a way for userspace to opt-in to userspace managed VM is added. For this to work, we need to defer creation of the VM until it is needed. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661490/
2025-07-05drm/msm: Add PRR supportRob Clark1-0/+10
Add PRR (Partial Resident Region) is a bypass address which make GPU writes go to /dev/null and reads return zero. This is used to implement vulkan sparse residency. To support PRR/NULL mappings, we allocate a page to reserve a physical address which we know will not be used as part of a GEM object, and configure the SMMU to use this address for PRR/NULL mappings. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661486/
2025-07-05drm/msm: Add mmu support for non-zero offsetRob Clark1-1/+4
Only needs to be supported for iopgtables mmu, the other cases are either only used for kernel managed mappings (where offset is always zero) or devices which do not support sparse bindings. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661501/
2025-07-05drm/msm: Use drm_gpuvm types moreRob Clark8-23/+30
Most of the driver code doesn't need to reach in to msm specific fields, so just use the drm_gpuvm/drm_gpuva types directly. This should hopefully improve commonality with other drivers and make the code easier to understand. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661483/
2025-07-05drm/msm: drm_gpuvm conversionRob Clark4-11/+10
Now that we've realigned deletion and allocation, switch over to using drm_gpuvm/drm_gpuva. This allows us to support multiple VMAs per BO per VM, to allow mapping different parts of a single BO at different virtual addresses, which is a key requirement for sparse/VM_BIND. This prepares us for using drm_gpuvm to translate a batch of MAP/ MAP_NULL/UNMAP operations from userspace into a sequence of map/remap/ unmap steps for updating the page tables. Since, unlike our prior vm/vma setup, with drm_gpuvm the vm_bo holds a reference to the GEM object. To prevent reference loops causing us to leak all GEM objects, we implicitly tear down the mapping when the GEM handle is close or when the obj is unpinned. Which means the submit needs to also hold a reference to the vm_bo, to prevent the VMA from being torn down while the submit is in-flight. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661479/
2025-07-04drm/msm: Remove vram carveout supportRob Clark8-48/+5
It is standing in the way of drm_gpuvm / VM_BIND support. Not to mention frequently broken and rarely tested. And I think only needed for a 10yr old not quite upstream SoC (msm8974). Maybe we can add support back in later, but I'm doubtful. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661467/
2025-07-04drm/msm: Rename msm_gem_address_space -> msm_gem_vmRob Clark14-109/+108
Re-aligning naming to better match drm_gpuvm terminology will make things less confusing at the end of the drm_gpuvm conversion. This is just rename churn, no functional change. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661466/
2025-07-04drm/msm: Rename msm_file_private -> msm_contextRob Clark3-6/+6
This is a more descriptive name. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661459/
2025-07-04drm/msm/adreno: Add Adreno X1-45 supportAkhil P Oommen1-0/+39
Add support for Adreno X1-45 GPU present Snapdragon X1P42100 series of compute chipsets. This GPU is a smaller version of X1-85 GPU with lower core count and smaller internal memories. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # x1-26-100 Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660217/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-07-04drm/msm/adreno: Add speedbin support for X1-85Akhil P Oommen1-0/+7
Add the speedbin table to the X1-85's entry in the catalogue to enable SKU detection. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/661837/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-06-29Merge remote-tracking branch 'drm/drm-next' into msm-nextRob Clark2-2/+4
Back-merge drm-next to (indirectly) get arm-smmu updates for making stall-on-fault more reliable. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-06-14drm/msm: Fix inverted WARN_ON() logicRob Clark1-1/+1
We want to WARN_ON() if info is NULL. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Fixes: 0838fc3e6718 ("drm/msm/adreno: Check for recognized GPU before bind") Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reported-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/658631/
2025-06-10drm/msm/adreno: Check for recognized GPU before bindRob Clark1-5/+24
If we have a newer dtb than kernel, we could end up in a situation where the GPU device is present in the dtb, but not in the drivers device table. We don't want this to prevent the display from probing. So check that we recognize the GPU before adding the GPU component. v2: use %pOF Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/657701/
2025-06-09drm/msm/adreno: Pass device_node to find_chipid()Rob Clark1-5/+5
We are going to want to re-use this before the component is bound, when we don't yet have the device pointer (but we do have the of node). v2: use %pOF Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/657705/
2025-06-09drm/msm/a7xx: Call CP_RESET_CONTEXT_STATEConnor Abbott1-0/+14
Calling this packet is necessary when we switch contexts because there are various pieces of state used by userspace to synchronize between BR and BV that are persistent across submits and we need to make sure that they are in a "safe" state when switching contexts. Otherwise a userspace submission in one context could cause another context to function incorrectly and hang, effectively a denial of service (although without leaking data). This was missed during initial a7xx bringup. Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/654924/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-06-09drm/msm: Temporarily disable stall-on-fault after a page faultConnor Abbott4-1/+47
When things go wrong, the GPU is capable of quickly generating millions of faulting translation requests per second. When that happens, in the stall-on-fault model each access will stall until it wins the race to signal the fault and then the RESUME register is written. This slows processing page faults to a crawl as the GPU can generate faults much faster than the CPU can acknowledge them. It also means that all available resources in the SMMU are saturated waiting for the stalled transactions, so that other transactions such as transactions generated by the GMU, which shares translation resources with the GPU, cannot proceed. This causes a GMU watchdog timeout, which leads to a failed reset because GX cannot collapse when there is a transaction pending and a permanently hung GPU. On older platforms with qcom,smmu-v2, it seems that when one transaction is stalled subsequent faulting transactions are terminated, which avoids this problem, but the MMU-500 follows the spec here. To work around these problems, disable stall-on-fault as soon as we get a page fault until a cooldown period after pagefaults stop. This allows the GMU some guaranteed time to continue working. We only use stall-on-fault to halt the GPU while we collect a devcoredump and we always terminate the transaction afterward, so it's fine to miss some subsequent page faults. We also keep it disabled so long as the current devcoredump hasn't been deleted, because in that case we likely won't capture another one if there's a fault. After this commit HFI messages still occasionally time out, because the crashdump handler doesn't run fast enough to let the GMU resume, but the driver seems to recover from it. This will probably go away after the HFI timeout is increased. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/654891/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-06-09drm/msm: Delete resume_translation()Connor Abbott1-5/+0
Unused since the previous commit. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/654890/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-06-09drm/msm: Don't use a worker to capture fault devcoredumpConnor Abbott1-14/+8
Now that we use a threaded IRQ, it should be safe to do this in the fault handler. We can also remove fault_info from struct msm_gpu and just pass it directly. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/654889/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-06-08treewide, timers: Rename from_timer() to timer_container_of()Ingo Molnar2-2/+4
Move this API to the canonical timer_*() namespace. [ tglx: Redone against pre rc1 ] Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/aB2X0jCKQO56WdMt@gmail.com
2025-05-10drm/msm/adreno: Remove MODULE_FIRMWARE()'sRob Clark5-33/+0
The driver handles the case where gpu fw is not in the initrd. OTOH it doesn't always handle the case where _some_ fw is in the initrd, but others are not. In particular the zap fw tends to be signed with an OEM specific key, so the paths/names differ across devices with the same SoC/GPU, so we cannot sanely list them with MODULE_FIRMWARE(). So MODULE_FIRMWARE() just ends up causing problems without actually solving anything. Remove them! Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/652195/
2025-05-10drm/msm/a6xx: Disable rgb565_predicator on Adreno 7c3Konrad Dybcio1-1/+0
This feature is supposed to be enabled with UBWC v4 or later. Implementations of this SKU feature an effective UBWC version of 3, so disable it, in line with the BSP kernel. Reported-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Fixes: 192f4ee3e408 ("drm/msm/a6xx: Add support for Adreno 7c Gen 3 gpu") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/651759/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-05-04drm/msm/adreno: Add module param to disable ACDAkhil P Oommen2-0/+11
Add a module param to disable ACD which will help to quickly rule it out for any GPU issues. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Tested-by: Maya Matuszczyk <maccraft123mc@gmail.com> Tested-by: Anthony Ruhier <aruhier@mailbox.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/649349/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-05-04drm/msm: a6x: Rework qmp_get() error handlingAkhil P Oommen1-2/+3
Fix the following for qmp_get() errors: 1. Correctly handle probe defer for A6x GPUs 2. Ignore other errors because those are okay when GPU ACD is not required. They are checked again during gpu acd probe. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Maya Matuszczyk <maccraft123mc@gmail.com> Tested-by: Anthony Ruhier <aruhier@mailbox.org> Patchwork: https://patchwork.freedesktop.org/patch/649346/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-05-04drm/msm/a6xx: Increase HFI response timeoutAkhil P Oommen1-1/+1
When ACD feature is enabled, it triggers some internal calibrations which result in a pretty long delay during the first HFI perf vote. So, increase the HFI response timeout to match the downstream driver. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Tested-by: Maya Matuszczyk <maccraft123mc@gmail.com> Tested-by: Anthony Ruhier <aruhier@mailbox.org> Patchwork: https://patchwork.freedesktop.org/patch/649344/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-05-04drm/msm/adreno: Add support for ACDAkhil P Oommen4-10/+132
ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce the power consumption. In some chipsets, it is also a requirement to support higher GPU frequencies. This patch adds support for GPU ACD by sending necessary data to GMU and AOSS. The feature support for the chipset is detected based on devicetree data. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Tested-by: Maya Matuszczyk <maccraft123mc@gmail.com> Tested-by: Anthony Ruhier <aruhier@mailbox.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/649342/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-05-04drm/msm/adreno: Drop fictional address_space_sizeRob Clark4-22/+36
Really the only purpose of this was to limit the address space size to 4GB to avoid 32b rollover problems in 64b pointer math in older sqe fw. So replace the address_space_size with a quirk limiting the address space to 4GB. In all other cases, use the SMMU input address size (IAS) to determine the address space size. v2: Properly account for vm_start Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/649467/
2025-05-04drm/msm: Be more robust when HFI response times outConnor Abbott1-9/+26
If the GMU takes too long to respond to an HFI message, we may return early. If the GMU does eventually respond, and then we send a second message, we will see the response for the first, throw another error, and keep going. But we don't currently wait for the interrupt from the GMU again, so if the second response isn't there immediately we may prematurely return. This can cause a continuous cycle of missed HFI messages, and for reasons I don't quite understand the GMU does not shut down properly when this happens. Fix this by waiting for the GMU interrupt when we see an empty queue. If the GMU never responds then the queue really is empty and we quit. We can't wait for the interrupt when we see a wrong response seqnum because the GMU might have already queued both responses by the time we clear the interrupt the first time so we do need to check the queue before waiting on the interrupt again. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/650013/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-04-29Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-nextRob Clark6-7/+7
Merge drm-misc-next to get commit Fixes: fec450ca15af ("drm/display: hdmi: provide central data authority for ACR params"). Signed-off-by: Rob Clark <robdclark@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 17:26:23 +0300