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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2017-08-16drm/i915/cnl: Setup PAT Index.Rodrigo Vivi1-0/+1
2017-08-15drm/i915/hsw+: Add support for multiple power well regsImre Deak1-7/+25
2017-08-10drm/i915: add register macro definition style guideJani Nikula1-0/+91
2017-08-10drm/i915: enum i915_power_well_id is not proper kernel-docJani Nikula1-1/+1
2017-08-10drm/i915: Add render decompression supportVille Syrjälä1-0/+23
2017-08-09drm/i915/psr: Preserve SRD_CTL bit 29 on PSR initJim Bride1-0/+1
2017-08-03drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interfaceLionel Landwerlin1-3/+67
2017-08-03drm/i915: reorder NOA register definition to follow addressesLionel Landwerlin1-106/+106
2017-07-27drm/i915: cleanup the CHICKEN_MISC_2 (re)definitionsPaulo Zanoni1-5/+3
2017-07-27drm/i915: prepare pipe for YCBCR420 outputShashank Sharma1-0/+3
2017-07-27drm/i915/hsw+: Add has_fuses power well attributeImre Deak1-4/+10
2017-07-27drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macrosImre Deak1-5/+3
2017-07-27drm/i915/hsw, bdw: Add an ID for the global display power wellImre Deak1-0/+6
2017-07-27drm/i915/gen2: Add an ID for the display pipes power wellImre Deak1-0/+6
2017-07-27drm/i915: Unify power well ID enumsImre Deak1-14/+28
2017-07-27drm/i915/chv: Add unique power well ID for the pipe A power wellImre Deak1-0/+2
2017-07-07drm/i915/cnl: Get DDI clock based on PLLs.Rodrigo Vivi1-0/+2
2017-07-07drm/i915/cnl: Inherit RPS stuff from previous platforms.Rodrigo Vivi1-2/+2
2017-06-30drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing ProgrammingNavare, Manasi D1-1/+1
2017-06-20drm/i915/cnl: Fix RMW on ddi vswing sequence.Rodrigo Vivi1-0/+9
2017-06-14drm/i915/perf: Add OA unit support for Gen 8+Robert Bragg1-0/+22
2017-06-12drm/i915/cnl: Implement voltage swing sequence.Rodrigo Vivi1-0/+1
2017-06-12drm/i915/cnl: Add registers related to voltage swing sequences.Rodrigo Vivi1-0/+140
2017-06-12drm/i915: Add MMIO helper for 6 ports with different offsets.Rodrigo Vivi1-0/+3
2017-06-12drm/i915/cnl: Initialize PLLsRodrigo Vivi1-0/+48
2017-06-12drm/i915/cnl: DDI - PLL mappingRodrigo Vivi1-0/+9
2017-06-12drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä1-0/+23
2017-06-12drm/i915/cnl: Implement .get_display_clock_speed() for CNLVille Syrjälä1-0/+5
2017-06-07drm/i915: Remove unnecessary PORT3 definition.Rodrigo Vivi1-4/+2
2017-06-07drm/i915/cnl: Add power wells for CNLVille Syrjälä1-0/+5
2017-06-06drm/i915: Implement fbc_status "Compressing" info for all platformsVille Syrjälä1-5/+5
2017-06-02drm/i915/cnp: add CNP gmbus supportRodrigo Vivi1-1/+2
2017-06-02drm/i915/cnp: Get/set proper Raw clock frequency on CNP.Rodrigo Vivi1-0/+5
2017-05-30drm/i915: Remove decoupled MMIO codeKai Chen1-7/+0
2017-05-18drm/i915: Fix new -Wint-in-bool-context gcc compiler warningHans de Goede1-1/+1
2017-05-10drm/i915: Support variable cursor height on ivb+Ville Syrjälä1-1/+4
2017-05-10drm/i915: Parametrize cursor/primary pipe select bitsVille Syrjälä1-5/+2
2017-05-05drm/i915: Fix rawclk readout for g4xVille Syrjälä1-3/+7
2017-04-28drm/i915: Sanitize engine context sizesJoonas Lahtinen1-10/+0
2017-04-11drm/i915: Classify the engines in class + instanceDaniele Ceraolo Spurio1-0/+8
2017-03-28drm/i915: enable scramblingShashank Sharma1-0/+7
2017-03-16drm/i915: Use ktime to calculate rc0 residencyMika Kuoppala1-2/+0
2017-03-13drm/i915: Rename REDIRECT_TO_GUC bitChris Wilson1-1/+1
2017-03-09drm/i915: Initialize pm_intr_keep during intel_irq_init for GuCSagar Arun Kamble1-1/+2
2017-03-08Merge tag 'drm-intel-next-2017-03-06' of git://anongit.freedesktop.org/git/dr...Dave Airlie1-12/+90
2017-03-04drm/i915: Don't use enums for hardware engine idMichal Wajdeczko1-0/+6
2017-03-01drm/i915: Tighten mmio arrays for MIPI_PORTChris Wilson1-1/+1
2017-02-28drm/i915/glk: Program txesc clock divider for GLKDeepak M1-0/+5
2017-02-28drm/i915/glk: Add DSI PLL divider range for glkDeepak M1-0/+4
2017-02-28drm/i915/glk: Program new MIPI DSI PHY registers for GLKDeepak M1-0/+8
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