diff options
| author | Imre Deak <imre.deak@intel.com> | 2017-07-06 17:40:34 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-27 10:38:52 +0300 |
| commit | 1af474fef2697a1ab7e497627bddf026a3e767ac (patch) | |
| tree | b7b687993158f903508f361b4417e1e6da4b5569 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | ec46d48360432cbc9280e52692ec2f15bd85bdca (diff) | |
| download | linux-1af474fef2697a1ab7e497627bddf026a3e767ac.tar.xz | |
drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
Although on HSW/BDW there is only a single display global power well,
it's programmed the same way as other GEN9+ power wells. This also
means we can get at the HSW/BDW request and status flags the same way
it's done on GEN9+ by assigning the corresponding HSW/BDW power well ID.
This ID was assigned in a recent patch, so we can now switch to using
the same macros everywhere on HSW+.
Updating the HSW power well control register with RMW is not strictly
necessary, but this will allow us to use the same code for GEN9+.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-13-git-send-email-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 23dc1b5328d0..d7241a25a929 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1140,9 +1140,6 @@ enum i915_power_well_id { I915_DISP_PW_ALWAYS_ON = 20, }; -#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) -#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) - #define PUNIT_REG_PWRGT_CTRL 0x60 #define PUNIT_REG_PWRGT_STATUS 0x61 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) @@ -8016,8 +8013,9 @@ enum { #define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ #define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ #define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ -#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) -#define HSW_PWR_WELL_STATE_ENABLED (1<<30) +#define _HSW_PW_SHIFT(pw) ((pw) * 2) +#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) +#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |