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path: root/drivers/gpu/drm/i915/display/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2022-10-31drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak1-40/+28
2022-09-27drm/i915: Force DPLL calculation for TC ports after readoutVille Syrjälä1-3/+15
2022-09-07drm/i915: Relocate intel_crtc_dotclock()Ville Syrjälä1-22/+0
2022-08-31drm/i915/quirks: abstract checking for display quirksJani Nikula1-1/+2
2022-08-29drm/i915: move hotplug to display.hotplugJani Nikula1-3/+3
2022-08-29drm/i915: move dpll under display.dpllJani Nikula1-12/+12
2022-08-15drm/i915/tc: Fix PHY ownership programming in HDMI legacy modeImre Deak1-2/+8
2022-08-04Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-1/+1
2022-07-18drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling orderImre Deak1-1/+5
2022-07-12Merge tag 'drm-intel-next-2022-07-06' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-1/+1
2022-07-06drm/i915: Nuke PCH_MCCVille Syrjälä1-1/+1
2022-06-24Merge tag 'drm-intel-next-2022-06-22' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-31/+21
2022-06-14drm/i915: Extract intel_crtc_dotclock()Ville Syrjälä1-6/+12
2022-06-03drm/i915/regs: split out intel audio register definitionsJani Nikula1-0/+1
2022-06-01drm/i915/display: stop using BUG()Jani Nikula1-5/+6
2022-05-27drm/i915: Extract intel_edp_fixup_vbt_bpp()Ville Syrjälä1-20/+2
2022-05-11Merge tag 'drm-intel-next-2022-05-06' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-3/+3
2022-04-25drm/display: Move SCDC helpers into display-helper libraryThomas Zimmermann1-1/+1
2022-04-20drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platformImre Deak1-3/+3
2022-04-20drm/i915: Rename the power domain names to end with pipes/portsImre Deak1-1/+1
2022-04-11drm/i915/dg2: Do not explode on phy calibration errorLucas De Marchi1-2/+1
2022-03-30drm/i915/audio: move has_audio checks to within codec enable/disableJani Nikula1-10/+4
2022-03-16drm/i915: Do DRRS disable/enable during pre/post_plane_update()Ville Syrjälä1-4/+0
2022-03-15drm/i915: Move DRRS enable/disable higher upVille Syrjälä1-3/+0
2022-03-15drm/i915: Stash DRRS state under intel_crtcVille Syrjälä1-1/+3
2022-03-15drm/i915: Eliminate the intel_dp dependency from DRRSVille Syrjälä1-5/+3
2022-03-02drm/i915: Use str_enable_disable()Lucas De Marchi1-1/+3
2022-02-25drm/i915/dg2: Skip output init on PHY calibration failureMatt Roper1-0/+8
2022-02-21drm/i915/adlp: Add TypeC PHY TBT->DP-alt/legacy mode switch workaroundImre Deak1-1/+18
2022-02-15drm/i915: Change bigjoiner state tracking to use the pipe bitmaskVille Syrjälä1-5/+7
2022-02-15drm/i915: Introduce intel_crtc_is_bigjoiner_{slave,master}()Ville Syrjälä1-1/+1
2022-02-01drm/i915: Move M/N setup to a more logical place on ddi platformsVille Syrjälä1-9/+1
2022-02-01drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()Ville Syrjälä1-2/+4
2022-02-01drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä1-6/+6
2022-02-01drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä1-3/+4
2022-02-01drm/i915: Nuke intel_dp_get_m_n()Ville Syrjälä1-2/+7
2022-02-01drm/i915: Nuke intel_dp_set_m_n()Ville Syrjälä1-1/+3
2022-01-28drm/i915: s/gmch_{m,n}/data_{m,n}/Ville Syrjälä1-2/+2
2022-01-26drm/i915: Move dsc/joiner enable into hsw_crtc_enable()Ville Syrjälä1-6/+0
2022-01-24drm/i915: Nuke dg2_ddi_pre_enable_dp()Ville Syrjälä1-113/+4
2022-01-13drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequenceJosé Roberto de Souza1-0/+22
2022-01-12drm/i915: Move TC PHY registers to their own headerMatt Roper1-0/+1
2022-01-12drm/i915: Move combo PHY registers to their own headerMatt Roper1-0/+1
2021-12-09drm/i915: Add privacy-screen support (v3)Hans de Goede1-0/+16
2021-11-10drm/i915: Call intel_update_active_dpll() for both bigjoiner pipesVille Syrjälä1-1/+7
2021-11-03drm/i915: Use intel_de_rmw() for icl combo phy programmingVille Syrjälä1-26/+18
2021-11-03drm/i915: Use intel_de_rmw() for icl mg phy programmingVille Syrjälä1-73/+42
2021-11-03drm/i915: Use intel_de_rmw() for tgl dkl phy programmingVille Syrjälä1-21/+17
2021-11-03drm/i915: Query the vswing levels per-lane for tgl dkl phyVille Syrjälä1-14/+19
2021-11-03drm/i915: Query the vswing levels per-lane for icl mg phyVille Syrjälä1-1/+12
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