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path: root/drivers/clk/imx/clk-imx8qxp.c
AgeCommit message (Expand)AuthorFilesLines
2024-06-21clk: imx: imx8qxp: Parent should be initialized earlier than the clockPeng Fan1-3/+3
2024-06-21clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clkPeng Fan1-2/+2
2024-06-21clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocksOliver F. Brown1-4/+20
2024-06-21clk: imx: imx8qxp: Add LVDS bypass clocksPeng Fan1-9/+8
2023-12-20clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocksAlexander Stein1-4/+20
2023-10-04clk: imx: imx8qxp: correct the enet clocks for i.MX8DXLShenwei Wang1-2/+9
2023-10-04clk: imx: imx8qxp: Fix elcdif_pll clockRobert Chiras1-1/+1
2023-07-19clk: Explicitly include correct DT includesRob Herring1-1/+0
2022-01-29clk: imx: Add imx8dxl clk driverJacky Bai1-0/+1
2021-12-03clk: imx: use module_platform_driverMiles Chen1-1/+1
2021-06-14clk: imx: scu: add more scu clocksDong Aisheng1-2/+150
2021-06-14clk: imx: scu: add enet rgmii gpr clocksDong Aisheng1-4/+18
2021-06-14clk: imx8qm: add clock valid resource checkingDong Aisheng1-0/+1
2021-06-14clk: imx8qxp: add clock valid checking mechnismDong Aisheng1-3/+6
2021-06-14clk: imx: scu: remove legacy scu clock binding supportDong Aisheng1-124/+77
2021-01-05clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystemsLiu Ying1-0/+10
2021-01-05clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()Liu Ying1-2/+10
2021-01-05clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocksLiu Ying1-0/+2
2021-01-05clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocksLiu Ying1-0/+2
2020-10-26clk: imx: scu: add two cells binding supportDong Aisheng1-60/+76
2020-08-22clk: imx8qxp: Support building i.MX8QXP clock driver as moduleAnson Huang1-0/+4
2019-02-21clk: imx: scu: add fallback compatible string supportAisheng Dong1-0/+1
2018-12-28clk: imx8qxp: make the name of clock ID genericAisheng Dong1-77/+77
2018-12-15clk: imx: add imx8qxp clk driverAisheng Dong1-0/+153