diff options
Diffstat (limited to 'Documentation/devicetree/bindings')
857 files changed, 28513 insertions, 8388 deletions
diff --git a/Documentation/devicetree/bindings/.gitignore b/Documentation/devicetree/bindings/.gitignore index a77719968a7e..51ddb26d93f0 100644 --- a/Documentation/devicetree/bindings/.gitignore +++ b/Documentation/devicetree/bindings/.gitignore @@ -2,3 +2,8 @@ *.example.dts /processed-schema*.yaml /processed-schema*.json + +# +# We don't want to ignore the following even if they are dot-files +# +!.yamllint diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index bf2d8a8ced77..8b395893bd85 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -28,7 +28,7 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \ -name 'processed-schema*' \) -find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)" +find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" CHK_DT_DOCS := $(shell $(find_cmd)) quiet_cmd_yamllint = LINT $(src) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 3eee03aa935c..8c7575455422 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,6 +31,7 @@ properties: - description: Mercury+ AA1 boards items: - enum: + - enclustra,mercury-pe1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index e16b5fa55847..b634d5b04e15 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -154,6 +154,7 @@ properties: items: - enum: - khadas,vim3 + - radxa,zero2 - const: amlogic,a311d - const: amlogic,g12b @@ -165,6 +166,7 @@ properties: - azw,gtking-pro - hardkernel,odroid-go-ultra - hardkernel,odroid-n2 + - hardkernel,odroid-n2l - hardkernel,odroid-n2-plus - khadas,vim3 - ugoos,am6 @@ -176,6 +178,7 @@ properties: - enum: - amediatech,x96-air - amediatech,x96-air-gbit + - bananapi,bpi-m2-pro - bananapi,bpi-m5 - cyx,a95xf3-air - cyx,a95xf3-air-gbit diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 73f272664e83..e0eff4c05879 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -78,6 +78,7 @@ properties: - facebook,cloudripper-bmc - facebook,elbert-bmc - facebook,fuji-bmc + - facebook,greatlakes-bmc - ibm,everest-bmc - ibm,rainier-bmc - ibm,tacoma-bmc @@ -85,6 +86,7 @@ properties: - jabil,rbp-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc + - ufispace,ncplite-bmc - const: aspeed,ast2600 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 2224b18801a1..dfb8fd089197 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -91,9 +91,11 @@ properties: - const: atmel,sama5d2 - const: atmel,sama5 - - description: SAM9X60-EK board + - description: Microchip SAM9X60 Evaluation Boards items: - - const: microchip,sam9x60ek + - enum: + - microchip,sam9x60ek + - microchip,sam9x60-curiosity - const: microchip,sam9x60 - const: atmel,at91sam9 diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 01b5a9c689a2..c145f6a035ee 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -141,6 +141,7 @@ properties: - arm,cortex-a78ae - arm,cortex-a510 - arm,cortex-a710 + - arm,cortex-a715 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -151,6 +152,7 @@ properties: - arm,cortex-r7 - arm,cortex-x1 - arm,cortex-x2 + - arm,cortex-x3 - arm,neoverse-e1 - arm,neoverse-n1 - arm,neoverse-n2 @@ -257,7 +259,7 @@ properties: capacity-dmips-mhz: description: - u32 value representing CPU capacity (see ./cpu-capacity.txt) in + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 05b5276a0e14..442ce8f4d675 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -88,12 +88,56 @@ properties: items: - enum: - armadeus,imx28-apf28 # APF28 SoM - - armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board + - bluegiga,apx4devkit # Bluegiga APx4 SoM on dev board + - crystalfontz,cfa10036 # Crystalfontz CFA-10036 SoM + - eukrea,mbmx28lc - fsl,imx28-evk - i2se,duckbill - i2se,duckbill-2 + - karo,tx28 # Ka-Ro electronics TX28 module + - lwn,imx28-xea + - msr,m28cu3 # M28 SoM with custom base board + - schulercontrol,imx28-sps1 - technologic,imx28-ts4600 - const: fsl,imx28 + + - description: i.MX28 Aries M28 SoM Board + items: + - const: aries,m28 + - const: denx,m28 + - const: fsl,imx28 + + - description: i.MX28 Aries M28EVK Board + items: + - const: aries,m28evk + - const: denx,m28evk + - const: fsl,imx28 + + - description: i.MX28 Armadeus Systems APF28Dev Board + items: + - const: armadeus,imx28-apf28dev + - const: armadeus,imx28-apf28 + - const: fsl,imx28 + + - description: i.MX28 Crystalfontz CFA-10036 based Boards + items: + - enum: + - crystalfontz,cfa10037 + - crystalfontz,cfa10049 + - crystalfontz,cfa10057 + - crystalfontz,cfa10058 + - const: crystalfontz,cfa10036 + - const: fsl,imx28 + + - description: i.MX28 Crystalfontz CFA-10037 based Boards + items: + - enum: + - crystalfontz,cfa10055 + - crystalfontz,cfa10056 + - const: crystalfontz,cfa10037 + - const: crystalfontz,cfa10036 + - const: fsl,imx28 + - description: i.MX28 Duckbill 2 based Boards items: - enum: @@ -103,6 +147,19 @@ properties: - const: i2se,duckbill-2 - const: fsl,imx28 + - description: i.MX28 Eukrea Electromatique MBMX283LC Board + items: + - const: eukrea,mbmx283lc + - const: eukrea,mbmx28lc + - const: fsl,imx28 + + - description: i.MX28 Eukrea Electromatique MBMX287LC Board + items: + - const: eukrea,mbmx287lc + - const: eukrea,mbmx283lc + - const: eukrea,mbmx28lc + - const: fsl,imx28 + - description: i.MX31 based Boards items: - enum: @@ -173,6 +230,7 @@ properties: - kiebackpeter,imx53-ddc # K+P imx53 DDC - kiebackpeter,imx53-hsc # K+P imx53 HSC - menlo,m53menlo # i.MX53 Menlo board + - starterkit,sk-imx53 - voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668 - const: fsl,imx53 @@ -644,6 +702,16 @@ properties: - const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM - const: fsl,imx6ull + - description: i.MX6ULL DHCOM SoM based Boards + items: + - enum: + - dh,imx6ull-dhcom-drc02 + - dh,imx6ull-dhcom-pdk2 + - dh,imx6ull-dhcom-picoitx + - const: dh,imx6ull-dhcom-som # The DHCOR is soldered on the DHCOM + - const: dh,imx6ull-dhcor-som + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: @@ -815,7 +883,6 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board - - cloos,imx8mm-phg # i.MX8MM Cloos PHG Board - dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board @@ -830,7 +897,6 @@ properties: - innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM - - menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules @@ -861,8 +927,10 @@ properties: - description: Toradex Boards with Verdin iMX8M Mini Modules items: - enum: + - menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia - toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board + - toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -872,6 +940,7 @@ properties: - enum: - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia - toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -895,6 +964,7 @@ properties: one compatible is needed. items: - enum: + - cloos,imx8mm-phg # i.MX8MM Cloos PHG Board - tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx - const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM - const: fsl,imx8mm @@ -931,10 +1001,11 @@ properties: - description: i.MX8MP based Boards items: - enum: - - dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM - - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board + - beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board + - polyhex,imx8mp-debix # Polyhex Debix boards + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules @@ -947,6 +1018,12 @@ properties: - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM - const: fsl,imx8mp + - description: i.MX8MP DHCOM based Boards + items: + - const: dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board + - const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM + - const: fsl,imx8mp + - description: Engicam i.Core MX8M Plus SoM based boards items: - enum: @@ -965,6 +1042,7 @@ properties: - enum: - toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia - toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board + - toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -974,6 +1052,7 @@ properties: - enum: - toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia - toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -999,12 +1078,17 @@ properties: - fsl,imx8mq-evk # i.MX8MQ EVK Board - google,imx8mq-phanbell # Google Coral Edge TPU - kontron,pitx-imx8m # Kontron pITX-imx8m Board - - mntre,reform2 # MNT Reform2 Laptop - purism,librem5-devkit # Purism Librem5 devkit - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk - const: fsl,imx8mq + - description: i.MX8MQ NITROGEN SoM based Boards + items: + - const: mntre,reform2 # MNT Reform2 Laptop + - const: boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM + - const: fsl,imx8mq + - description: Purism Librem5 phones items: - enum: diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 2275e5d93721..ae12b1cab9fb 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -246,6 +246,10 @@ properties: - const: mediatek,mt8183 - items: - enum: + - mediatek,mt8365-evk + - const: mediatek,mt8365 + - items: + - enum: - mediatek,mt8516-pumpkin - const: mediatek,mt8516 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index 0502db73686b..eccd4b706a78 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7629-ethsys", "syscon" + - "mediatek,mt7981-ethsys", "syscon" - "mediatek,mt7986-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml index 1d7c837d9378..e997635e4fe4 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt6797-infracfg - mediatek,mt7622-infracfg - mediatek,mt7629-infracfg + - mediatek,mt7981-infracfg - mediatek,mt7986-infracfg - mediatek,mt8135-infracfg - mediatek,mt8167-infracfg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 0711f1834fbd..d1410345ef18 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -31,7 +31,11 @@ properties: - mediatek,mt8173-mmsys - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys + - mediatek,mt8188-vdosys0 - mediatek,mt8192-mmsys + - mediatek,mt8195-vdosys1 + - mediatek,mt8195-vppsys0 + - mediatek,mt8195-vppsys1 - mediatek,mt8365-mmsys - const: syscon diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml index 17fcbb45d121..d62d60181147 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml @@ -28,11 +28,9 @@ properties: - mediatek,mt8195-imp_iic_wrap_s - mediatek,mt8195-imp_iic_wrap_w - mediatek,mt8195-mfgcfg - - mediatek,mt8195-vppsys0 - mediatek,mt8195-wpesys - mediatek,mt8195-wpesys_vpp0 - mediatek,mt8195-wpesys_vpp1 - - mediatek,mt8195-vppsys1 - mediatek,mt8195-imgsys - mediatek,mt8195-imgsys1_dip_top - mediatek,mt8195-imgsys1_dip_nr @@ -93,13 +91,6 @@ examples: }; - | - vppsys0: clock-controller@14000000 { - compatible = "mediatek,mt8195-vppsys0"; - reg = <0x14000000 0x1000>; - #clock-cells = <1>; - }; - - - | wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8195-wpesys"; reg = <0x14e00000 0x1000>; @@ -121,13 +112,6 @@ examples: }; - | - vppsys1: clock-controller@14f00000 { - compatible = "mediatek,mt8195-vppsys1"; - reg = <0x14f00000 0x1000>; - #clock-cells = <1>; - }; - - - | imgsys: clock-controller@15000000 { compatible = "mediatek,mt8195-imgsys"; reg = <0x15000000 0x1000>; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index 29ca7a10b315..d2c24c277514 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -8,6 +8,8 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" - "mediatek,mt7629-sgmiisys", "syscon" + - "mediatek,mt7981-sgmiisys_0", "syscon" + - "mediatek,mt7981-sgmiisys_1", "syscon" - "mediatek,mt7986-sgmiisys_0", "syscon" - "mediatek,mt7986-sgmiisys_1", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml new file mode 100644 index 000000000000..2ec9b5b24d73 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Aggregator - TPDA + +description: | + TPDAs are responsible for packetization and timestamping of data sets + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or + more attached TPDM and pushing the resultant (packetized) data out a + master ATB interface. Performing an arbitrated ATB interleaving (funneling) + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). + + There is no strict binding between TPDM and TPDA. TPDA can have multiple + TPDMs connect to it. But There must be only one TPDA in the path from the + TPDM source to TMC sink. TPDM can directly connect to TPDA's inport or + connect to funnel which will connect to TPDA's inport. + + We can use the commands are similar to the below to validate TPDMs. + Enable coresight sink first. + + echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink + echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source + echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test + echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test + + The test data will be collected in the coresight sink which is enabled. + If rwp register of the sink is keeping updating when do integration_test + (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM + to sink. + +maintainers: + - Mao Jinlong <quic_jinlmao@quicinc.com> + - Tao Zhang <quic_taozha@quicinc.com> + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tpda + required: + - compatible + +properties: + $nodename: + pattern: "^tpda(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpda + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + type: object + description: | + Input connections from TPDM to TPDA + $ref: /schemas/graph.yaml#/properties/ports + + out-ports: + type: object + description: | + Output connections from the TPDA to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: + Output connection from the TPDA to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + # minimum tpda definition. + - | + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x6004000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml new file mode 100644 index 000000000000..5c08342664ea --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Monitor - TPDM + +description: | + The TPDM or Monitor serves as data collection component for various dataset + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef), + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete + Single Bit (DSB). It performs data collection in the data producing clock + domain and transfers it to the data collection time domain, generally ATB + clock domain. + + The primary use case of the TPDM is to collect data from different data + sources and send it to a TPDA for packetization, timestamping, and funneling. + +maintainers: + - Mao Jinlong <quic_jinlmao@quicinc.com> + - Tao Zhang <quic_taozha@quicinc.com> + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tpdm + required: + - compatible + +properties: + $nodename: + pattern: "^tpdm(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpdm + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + out-ports: + description: | + Output connections from the TPDM to coresight funnel/TPDA. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: Output connection from the TPDM to coresight + funnel/TPDA. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + # minimum TPDM definition. TPDM connect to coresight TPDA. + - | + tpdm@684c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0684c000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_tpdm_prng>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 27063a045bd0..1bb24d46e4ee 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -35,6 +35,8 @@ description: | mdm9615 msm8226 msm8916 + msm8939 + msm8953 msm8956 msm8974 msm8976 @@ -47,11 +49,13 @@ description: | qru1000 sa8155p sa8540p + sa8775p sc7180 sc7280 sc8180x sc8280xp sda660 + sdm450 sdm630 sdm632 sdm636 @@ -62,6 +66,7 @@ description: | sdx65 sm4250 sm6115 + sm6115p sm6125 sm6350 sm6375 @@ -70,6 +75,7 @@ description: | sm8250 sm8350 sm8450 + sm8550 The 'board' element must be one of the following strings: @@ -84,6 +90,7 @@ description: | liquid mtp qrd + ride sbc x100 @@ -162,6 +169,12 @@ properties: - items: - enum: + - sony,kanuti-tulip + - square,apq8039-t2 + - const: qcom,msm8939 + + - items: + - enum: - sony,kugo-row - sony,suzu-row - const: qcom,msm8956 @@ -194,8 +207,10 @@ properties: - items: - enum: + - acer,a1-724 - alcatel,idol347 - asus,z00l + - gplus,fl8005a - huawei,g7 - longcheer,l8910 - samsung,a3u-eur @@ -203,8 +218,13 @@ properties: - samsung,e5 - samsung,e7 - samsung,grandmax + - samsung,gt510 + - samsung,gt58 - samsung,j5 + - samsung,j5x - samsung,serranove + - thwc,uf896 + - thwc,ufi001c - wingtech,wt88047 - const: qcom,msm8916 @@ -215,6 +235,15 @@ properties: - items: - enum: + - motorola,potter + - xiaomi,daisy + - xiaomi,mido + - xiaomi,tissot + - xiaomi,vince + - const: qcom,msm8953 + + - items: + - enum: - lg,bullhead - microsoft,talkman - xiaomi,libra @@ -627,6 +656,12 @@ properties: - const: google,hoglin - const: qcom,sc7280 + - description: Qualcomm Technologies, Inc. sc7280 CRD Pro platform (newest rev) + items: + - const: google,zoglin-sku1536 + - const: google,hoglin-sku1536 + - const: qcom,sc7280 + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform items: - const: qcom,sc7280-idp @@ -679,6 +714,18 @@ properties: - const: google,zombie-sku512 - const: qcom,sc7280 + - description: Google Zombie with NVMe (newest rev) + items: + - const: google,zombie-sku2 + - const: google,zombie-sku3 + - const: google,zombie-sku515 + - const: qcom,sc7280 + + - description: Google Zombie with LTE and NVMe (newest rev) + items: + - const: google,zombie-sku514 + - const: qcom,sc7280 + - items: - enum: - lenovo,flex-5g @@ -695,6 +742,11 @@ properties: - items: - enum: + - motorola,ali + - const: qcom,sdm450 + + - items: + - enum: - sony,discovery-row - sony,kirin-row - sony,pioneer-row @@ -709,6 +761,7 @@ properties: - items: - enum: - fairphone,fp3 + - motorola,ocean - const: qcom,sdm632 - items: @@ -764,6 +817,11 @@ properties: - items: - enum: + - qcom,sa8775p-ride + - const: qcom,sa8775p + + - items: + - enum: - google,cheza - google,cheza-rev1 - google,cheza-rev2 @@ -792,6 +850,12 @@ properties: - items: - enum: + - lenovo,j606f + - const: qcom,sm6115p + - const: qcom,sm6115 + + - items: + - enum: - sony,pdx201 - const: qcom,sm6125 @@ -826,6 +890,7 @@ properties: - qcom,sm8250-mtp - sony,pdx203-generic - sony,pdx206-generic + - xiaomi,elish - const: qcom,sm8250 - items: @@ -845,6 +910,11 @@ properties: - sony,pdx224 - const: qcom,sm8450 + - items: + - enum: + - qcom,sm8550-mtp + - const: qcom,sm8550 + # Board compatibles go above qcom,msm-id: @@ -922,15 +992,22 @@ allOf: - qcom,apq8026 - qcom,apq8094 - qcom,apq8096 + - qcom,msm8939 + - qcom,msm8953 + - qcom,msm8956 - qcom,msm8992 - qcom,msm8994 - qcom,msm8996 - qcom,msm8998 + - qcom,sdm450 - qcom,sdm630 - qcom,sdm632 + - qcom,sdm636 - qcom,sdm845 - qcom,sdx55 - qcom,sdx65 + - qcom,sm4250 + - qcom,sm6115 - qcom,sm6125 - qcom,sm6350 - qcom,sm7225 @@ -954,6 +1031,8 @@ allOf: - oneplus,dumpling - oneplus,enchilada - oneplus,fajita + - oneplus,oneplus3 + - oneplus,oneplus3t then: properties: qcom,board-id: diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 88ff4422a8c1..35f74eda30ae 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -90,11 +90,33 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a + - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards + items: + - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board + - const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM + - const: rockchip,rv1126 + + - description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards + items: + - const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board + - const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM + - const: rockchip,rk3588 + - description: Elgin RV1108 R1 items: - const: elgin,rv1108-r1 - const: rockchip,rv1108 + - description: EmbedFire LubanCat 1 + items: + - const: embedfire,lubancat-1 + - const: rockchip,rk3566 + + - description: EmbedFire LubanCat 2 + items: + - const: embedfire,lubancat-2 + - const: rockchip,rk3568 + - description: Engicam PX30.Core C.TOUCH 2.0 items: - const: engicam,px30-core-ctouch2 @@ -599,6 +621,20 @@ properties: - const: pine64,soquartz - const: rockchip,rk3566 + - description: Radxa Compute Module 3(CM3) + items: + - enum: + - radxa,cm3-io + - const: radxa,cm3 + - const: rockchip,rk3566 + + - description: Radxa CM3 Industrial + items: + - enum: + - radxa,e25 + - const: radxa,cm3i + - const: rockchip,rk3568 + - description: Radxa Rock items: - const: radxa,rock @@ -652,6 +688,16 @@ properties: - const: radxa,rock3a - const: rockchip,rk3568 + - description: Radxa ROCK 5 Model A + items: + - const: radxa,rock-5a + - const: rockchip,rk3588s + + - description: Radxa ROCK 5 Model B + items: + - const: radxa,rock-5b + - const: rockchip,rk3588 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 @@ -689,6 +735,11 @@ properties: - const: rockchip,rk3036-evb - const: rockchip,rk3036 + - description: Rockchip RK3128 Evaluation board + items: + - const: rockchip,rk3128-evb + - const: rockchip,rk3128 + - description: Rockchip RK3228 Evaluation board items: - const: rockchip,rk3228-evb @@ -736,6 +787,11 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 + - description: Rockchip RK3588 Evaluation board + items: + - const: rockchip,rk3588-evb1-v10 + - const: rockchip,rk3588 + - description: Rockchip RV1108 Evaluation board items: - const: rockchip,rv1108-evb @@ -761,6 +817,11 @@ properties: - const: tronsmart,orion-r68-meta - const: rockchip,rk3368 + - description: Xunlong Orange Pi R1 Plus + items: + - const: xunlong,orangepi-r1-plus + - const: rockchip,rk3328 + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml index 8c73bc7f4009..b79c81cd9f0e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -27,6 +27,7 @@ select: - rockchip,rk3399-pmu - rockchip,rk3568-pmu - rockchip,rk3588-pmu + - rockchip,rv1126-pmu required: - compatible @@ -43,6 +44,7 @@ properties: - rockchip,rk3399-pmu - rockchip,rk3568-pmu - rockchip,rk3588-pmu + - rockchip,rv1126-pmu - const: syscon - const: simple-mfd diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index faea33e4f731..deb2cf971871 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -171,6 +171,7 @@ properties: - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite - hardkernel,odroid-xu4 # Hardkernel Odroid XU4 - hardkernel,odroid-hc1 # Hardkernel Odroid HC1 + - samsung,k3g # Samsung Galaxy S5 (SM-G900H) - const: samsung,exynos5800 - const: samsung,exynos5 diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 203faab80142..a60a4065caa8 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -38,10 +38,17 @@ properties: - ti,am642-sk - const: ti,am642 + - description: K3 AM642 SoC PHYTEC phyBOARD-Electra + items: + - const: phytec,am642-phyboard-electra-rdk + - const: phytec,am64-phycore-som + - const: ti,am642 + - description: K3 AM654 SoC items: - enum: - siemens,iot2050-advanced + - siemens,iot2050-advanced-m2 - siemens,iot2050-advanced-pg2 - siemens,iot2050-basic - siemens,iot2050-basic-pg2 @@ -69,9 +76,17 @@ properties: - description: K3 J721s2 SoC items: - enum: + - ti,am68-sk - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J784s4 SoC + items: + - enum: + - ti,am69-sk + - ti,j784s4-evm + - const: ti,j784s4 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml b/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml index 52e18600ecff..378692010c56 100644 --- a/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml +++ b/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml @@ -35,6 +35,7 @@ required: allOf: - $ref: pata-common.yaml# + - $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/bus/aspeed,ast2600-ahbc.yaml b/Documentation/devicetree/bindings/bus/aspeed,ast2600-ahbc.yaml new file mode 100644 index 000000000000..2894256c976d --- /dev/null +++ b/Documentation/devicetree/bindings/bus/aspeed,ast2600-ahbc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED Advanced High-Performance Bus Controller (AHBC) + +maintainers: + - Neal Liu <neal_liu@aspeedtech.com> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> + +description: | + Advanced High-performance Bus Controller (AHBC) supports plenty of mechanisms + including a priority arbiter, an address decoder and a data multiplexer + to control the overall operations of Advanced High-performance Bus (AHB). + +properties: + compatible: + enum: + - aspeed,ast2600-ahbc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + ahbc@1e600000 { + compatible = "aspeed,ast2600-ahbc"; + reg = <0x1e600000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml index d3ed048c9521..4157e885c6e7 100644 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml @@ -40,10 +40,10 @@ properties: maxItems: 1 "#address-cells": - const: 1 + enum: [ 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] ranges: true diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index 61b246cf5e72..a2c6eea9871d 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -54,6 +54,7 @@ properties: - idt,5p49v5925 - idt,5p49v5933 - idt,5p49v5935 + - idt,5p49v60 - idt,5p49v6901 - idt,5p49v6965 - idt,5p49v6975 diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index e4c4cadec501..0dbc1433fede 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -108,7 +108,7 @@ examples: }; - | - clock-controller@30390000 { + clock-controller@30380000 { compatible = "fsl,imx8mq-ccm"; reg = <0x30380000 0x10000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml new file mode 100644 index 000000000000..63a59015987e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-2 SoC Clock Control Module + +maintainers: + - Yinbo Zhu <zhuyinbo@loongson.cn> + +description: | + Loongson-2 SoC clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + enum: + - loongson,ls2k-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: 100m ref + + clock-names: + items: + - const: ref_100m + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h + for the full list of Loongson-2 SoC clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ref_100m: clock-ref-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ref_100m"; + }; + + clk: clock-controller@1fe00480 { + compatible = "loongson,ls2k-clk"; + reg = <0x1fe00480 0x58>; + #clock-cells = <1>; + clocks = <&ref_100m>; + clock-names = "ref_100m"; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index 731bfe0408c2..dae25dba4ba6 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt6797-apmixedsys - mediatek,mt7622-apmixedsys + - mediatek,mt7981-apmixedsys - mediatek,mt7986-apmixedsys - mediatek,mt8135-apmixedsys - mediatek,mt8173-apmixedsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index 81531b5b0db7..0fdf56414833 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt6779-topckgen - mediatek,mt6795-topckgen - mediatek,mt7629-topckgen + - mediatek,mt7981-topckgen - mediatek,mt7986-topckgen - mediatek,mt8167-topckgen - mediatek,mt8183-topckgen diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml index 93ec1f598e6e..426335a2841c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml @@ -21,12 +21,16 @@ properties: clocks: items: + - description: AHB - description: Board XO source + - description: Board active XO source - description: Sleep clock source clock-names: items: + - const: iface - const: bi_tcxo + - const: bi_tcxo_ao - const: sleep_clk '#clock-cells': @@ -38,9 +42,18 @@ properties: '#power-domain-cells': const: 1 + power-domains: + items: + - description: MMCX power domain + reg: maxItems: 1 + required-opps: + maxItems: 1 + description: + OPP node describing required MMCX performance point. + required: - compatible - reg @@ -54,13 +67,16 @@ additionalProperties: false examples: - | + #include <dt-bindings/clock/qcom,gcc-sm8250.h> #include <dt-bindings/clock/qcom,rpmh.h> clock-controller@ad00000 { compatible = "qcom,sm8250-camcc"; reg = <0x0ad00000 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - clock-names = "bi_tcxo", "sleep_clk"; + clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml index 8ade176c24f4..d84608269080 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -25,6 +25,30 @@ properties: compatible: const: qcom,gcc-apq8084 + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: UFS RX symbol 0 clock + - description: UFS RX symbol 1 clock + - description: UFS TX symbol 0 clock + - description: UFS TX symbol 1 clock + - description: SATA ASIC0 clock + - description: SATA RX clock + - description: PCIe PIPE clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: ufs_rx_symbol_0_clk_src + - const: ufs_rx_symbol_1_clk_src + - const: ufs_tx_symbol_0_clk_src + - const: ufs_tx_symbol_1_clk_src + - const: sata_asic0_clk + - const: sata_rx_clk + - const: pcie_pipe + required: - compatible @@ -32,11 +56,31 @@ unevaluatedProperties: false examples: - | + /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */ clock-controller@fc400000 { compatible = "qcom,gcc-apq8084"; reg = <0xfc400000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + + clocks = <&xo_board>, + <&sleep_clk>, + <&ufsphy 0>, + <&ufsphy 1>, + <&ufsphy 2>, + <&ufsphy 3>, + <&sata 0>, + <&sata 1>, + <&pcie_phy>; + clock-names = "xo", + "sleep_clk", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src", + "ufs_tx_symbol_1_clk_src", + "sata_asic0_clk", + "sata_rx_clk", + "pcie_pipe"; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml index 2d5355cf9def..3c9729050d6f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml @@ -25,7 +25,6 @@ properties: - description: Board XO source - description: Sleep clock source - description: Audio reference clock (Optional clock) - - description: PLL test clock source (Optional clock) minItems: 2 clock-names: @@ -33,7 +32,6 @@ properties: - const: xo - const: sleep_clk - const: aud_ref_clk # Optional clock - - const: core_bi_pll_test_se # Optional clock minItems: 2 required: @@ -57,11 +55,9 @@ examples: reg = <0x00100000 0xb0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep>, - <0>, <0>; clock-names = "xo", "sleep_clk", - "aud_ref_clk", - "core_bi_pll_test_se"; + "aud_ref_clk"; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index dca5775f79a4..b2256f81b265 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -20,26 +20,31 @@ properties: compatible: const: qcom,gcc-qcs404 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: PCIe 0 PIPE clock (optional) + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: cxo + - const: sleep_clk + - const: pcie_0_pipe_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: hdmi_pll required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | @@ -48,5 +53,6 @@ examples: reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml index c9d8e436d73a..5681e535fede 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml @@ -55,6 +55,10 @@ properties: - description: First EMAC controller reference clock - description: Second EMAC controller reference clock + power-domains: + items: + - description: CX domain + protected-clocks: maxItems: 389 @@ -70,6 +74,8 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@100000 { compatible = "qcom,gcc-sc8280xp"; reg = <0x00100000 0x1f0000>; @@ -106,6 +112,7 @@ examples: <&pcie4_lane>, <&rxc0_ref_clk>, <&rxc1_ref_clk>; + power-domains = <&rpmhpd SC8280XP_CX>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml index 68d3099c96ae..428e954d7638 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml @@ -24,15 +24,11 @@ properties: items: - description: Board XO source - description: Sleep clock source - - description: PLL test clock source (Optional clock) - minItems: 2 clock-names: items: - const: bi_tcxo - const: sleep_clk - - const: core_bi_pll_test_se # Optional clock - minItems: 2 required: - compatible @@ -51,8 +47,9 @@ examples: compatible = "qcom,gcc-sdx55"; reg = <0x00100000 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, <&pll_test_clk>; - clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se"; + <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml index ba62baab916c..523e18d7f150 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -26,8 +26,6 @@ properties: - description: Sleep clock source - description: PCIE Pipe clock source - description: USB3 phy wrapper pipe clock source - - description: PLL test clock source (Optional clock) - minItems: 5 clock-names: items: @@ -36,8 +34,6 @@ properties: - const: sleep_clk - const: pcie_pipe_clk - const: usb3_phy_wrapper_gcc_usb30_pipe_clk - - const: core_bi_pll_test_se # Optional clock - minItems: 5 required: - compatible @@ -56,9 +52,9 @@ examples: compatible = "qcom,gcc-sdx65"; reg = <0x100000 0x1f7400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", - "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml index 703d9e075247..b4fdde71ef18 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml @@ -23,7 +23,6 @@ properties: items: - description: Board XO source - description: Sleep clock source - - description: PLL test clock source (Optional clock) - description: PCIE 0 Pipe clock source (Optional clock) - description: PCIE 1 Pipe clock source (Optional clock) - description: UFS card Rx symbol 0 clock source (Optional clock) @@ -40,7 +39,6 @@ properties: items: - const: bi_tcxo - const: sleep_clk - - const: core_bi_pll_test_se # Optional clock - const: pcie_0_pipe_clk # Optional clock - const: pcie_1_pipe_clk # Optional clock - const: ufs_card_rx_symbol_0_clk # Optional clock diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml deleted file mode 100644 index fb7ae3d18503..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml +++ /dev/null @@ -1,71 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Graphics Clock & Reset Controller on SM8350 - -maintainers: - - Robert Foss <robert.foss@linaro.org> - -description: | - Qualcomm graphics clock control module provides the clocks, resets and power - domains on Qualcomm SoCs. - - See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h - -properties: - compatible: - enum: - - qcom,sm8350-gpucc - - clocks: - items: - - description: Board XO source - - description: GPLL0 main branch source - - description: GPLL0 div branch source - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - - clocks - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,gcc-sm8350.h> - #include <dt-bindings/clock/qcom,rpmh.h> - - soc { - #address-cells = <2>; - #size-cells = <2>; - - clock-controller@3d90000 { - compatible = "qcom,sm8350-gpucc"; - reg = <0 0x03d90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - }; -... diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 7256c438a4cf..db53eb288995 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -21,6 +21,7 @@ description: | include/dt-bindings/clock/qcom,gpucc-sm6350.h include/dt-bindings/clock/qcom,gpucc-sm8150.h include/dt-bindings/clock/qcom,gpucc-sm8250.h + include/dt-bindings/clock/qcom,gpucc-sm8350.h properties: compatible: @@ -33,6 +34,7 @@ properties: - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc + - qcom,sm8350-gpucc clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml index e6d17426e903..acf0c923c24f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -32,11 +32,11 @@ properties: clocks: minItems: 8 - maxItems: 10 + maxItems: 13 clock-names: minItems: 8 - maxItems: 10 + maxItems: 13 '#clock-cells': const: 1 @@ -142,6 +142,46 @@ allOf: compatible: contains: enum: + - qcom,mmcc-apq8084 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board sleep source + - description: MMSS GPLL0 voted clock + - description: GPLL0 clock + - description: GPLL0 voted clock + - description: GPLL1 clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: eDP phy PLL link clock + - description: eDP phy PLL vco clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: mmss_gpll0_vote + - const: gpll0 + - const: gpll0_vote + - const: gpll1 + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + - const: edp_link_clk + - const: edp_vco_div + + - if: + properties: + compatible: + contains: + enum: - qcom,mmcc-msm8994 - qcom,mmcc-msm8998 - qcom,mmcc-sdm630 @@ -229,7 +269,6 @@ allOf: - description: HDMI phy PLL clock - description: DisplayPort phy PLL link clock - description: DisplayPort phy PLL vco clock - - description: Test clock clock-names: items: @@ -242,7 +281,6 @@ allOf: - const: hdmipll - const: dplink - const: dpvco - - const: core_bi_pll_test_se - if: properties: diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml index c4971234fef8..fcace96c72eb 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -27,10 +27,12 @@ properties: clocks: items: - description: XO source + - description: SYS APCS AUX clock clock-names: items: - const: xo + - const: sys_apcs_aux required: - compatible @@ -48,6 +50,6 @@ examples: reg = <0x6400000 0x90000>; #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; + clocks = <&xo_board>, <&apcs_glb>; + clock-names = "xo", "sys_apcs_aux"; }; diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml new file mode 100644 index 000000000000..3ffe69d8cdd5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,msm8996-cbf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8996 Core Bus Fabric (CBF) clock controller + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: > + The clock controller for the Qualcomm MSM8996 CBF clock, which drives the + interconnect between two CPU clusters. + +properties: + compatible: + const: qcom,msm8996-cbf + + reg: + maxItems: 1 + + clocks: + items: + - description: XO source + - description: SYS APCS AUX clock + + '#clock-cells': + const: 0 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@9a11000 { + compatible = "qcom,msm8996-cbf"; + reg = <0x09a11000 0x10000>; + clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>; + #clock-cells = <0>; + #interconnect-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml new file mode 100644 index 000000000000..767a9d03aa32 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 + +maintainers: + - Melody Olvera <quic_molvera@quicinc.com> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on QDU1000 and QRU1000 + + See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h + +properties: + compatible: + const: qcom,qdu1000-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 0 Phy Auxiliary clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,qdu1000-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>, + <&usb3_phy_wrapper_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index cf25ba0419e2..d5a250b7c2af 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,qdu1000-rpmh-clk + - qcom,sa8775p-rpmh-clk - qcom,sc7180-rpmh-clk - qcom,sc7280-rpmh-clk - qcom,sc8180x-rpmh-clk @@ -31,6 +32,7 @@ properties: - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml new file mode 100644 index 000000000000..0f641c235b13 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on sa8775p + +maintainers: + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and + power domains on sa8775p. + + See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h + +properties: + compatible: + const: qcom,sa8775p-gcc + + clocks: + items: + - description: XO reference clock + - description: Sleep clock + - description: UFS memory first RX symbol clock + - description: UFS memory second RX symbol clock + - description: UFS memory first TX symbol clock + - description: UFS card first RX symbol clock + - description: UFS card second RX symbol clock + - description: UFS card first TX symbol clock + - description: Primary USB3 PHY wrapper pipe clock + - description: Secondary USB3 PHY wrapper pipe clock + - description: PCIe 0 pipe clock + - description: PCIe 1 pipe clock + - description: PCIe PHY clock + - description: First EMAC controller reference clock + - description: Second EMAC controller reference clock + + protected-clocks: + maxItems: 240 + + power-domains: + maxItems: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + gcc: clock-controller@100000 { + compatible = "qcom,sa8775p-gcc"; + reg = <0x100000 0xc7018>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&ufs_card_rx_symbol_0_clk>, + <&ufs_card_rx_symbol_1_clk>, + <&ufs_card_tx_symbol_0_clk>, + <&usb_0_ssphy>, + <&usb_1_ssphy>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&pcie_phy_pipe_clk>, + <&rxc0_ref_clk>, + <&rxc1_ref_clk>; + power-domains = <&rpmhpd SA8775P_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml new file mode 100644 index 000000000000..fd6658cb793d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6350-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM6350 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM6350. + + See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h + +properties: + compatible: + const: qcom,sm6350-camcc + + clocks: + items: + - description: Board XO source + + reg: + maxItems: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sm6350-camcc"; + reg = <0x0ad00000 0x16000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index a52a83fe2831..87ae74166807 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -32,6 +32,7 @@ properties: A phandle and PM domain specifier for the MMCX power domain. required-opps: + maxItems: 1 description: A phandle to an OPP node describing required MMCX performance point. diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml new file mode 100644 index 000000000000..ab25f7cbaa2e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller for SM8550 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Neil Armstrong <neil.armstrong@linaro.org> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM8550. + + See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h + +properties: + compatible: + enum: + - qcom,sm8550-dispcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Display's AHB clock + - description: sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY0 + - description: VCO DIV clock from DP PHY0 + - description: Link clock from DP PHY1 + - description: VCO DIV clock from DP PHY1 + - description: Link clock from DP PHY2 + - description: VCO DIV clock from DP PHY2 + - description: Link clock from DP PHY3 + - description: VCO DIV clock from DP PHY3 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@af00000 { + compatible = "qcom,sm8550-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp0_phy 0>, + <&dp0_phy 1>, + <&dp1_phy 0>, + <&dp1_phy 1>, + <&dp2_phy 0>, + <&dp2_phy 1>, + <&dp3_phy 0>, + <&dp3_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 000000000000..1bf1a41fd89c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h + +properties: + compatible: + items: + - const: qcom,sm8550-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + + clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr", "syscon"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt deleted file mode 100644 index 7474aba36607..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt +++ /dev/null @@ -1,59 +0,0 @@ -Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv) - -clkdiv configures the clock frequency of a set of outputs on the PMIC. -These clocks are typically wired through alternate functions on -gpio pins. - -======================= -Properties -======================= - -- compatible - Usage: required - Value type: <string> - Definition: must be "qcom,spmi-clkdiv". - -- reg - Usage: required - Value type: <prop-encoded-array> - Definition: base address of CLKDIV peripherals. - -- qcom,num-clkdivs - Usage: required - Value type: <u32> - Definition: number of CLKDIV peripherals. - -- clocks: - Usage: required - Value type: <prop-encoded-array> - Definition: reference to the xo clock. - -- clock-names: - Usage: required - Value type: <stringlist> - Definition: must be "xo". - -- #clock-cells: - Usage: required - Value type: <u32> - Definition: shall contain 1. - -======= -Example -======= - -pm8998_clk_divs: clock-controller@5b00 { - compatible = "qcom,spmi-clkdiv"; - reg = <0x5b00>; - #clock-cells = <1>; - qcom,num-clkdivs = <3>; - clocks = <&xo_board>; - clock-names = "xo"; - - assigned-clocks = <&pm8998_clk_divs 1>, - <&pm8998_clk_divs 2>, - <&pm8998_clk_divs 3>; - assigned-clock-rates = <9600000>, - <9600000>, - <9600000>; -}; diff --git a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.yaml b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.yaml new file mode 100644 index 000000000000..16c95ad6c9d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMIC clock divider + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Stephen Boyd <sboyd@kernel.org> + +description: | + Qualcomm SPMI PMIC clock divider configures the clock frequency of a set of + outputs on the PMIC. These clocks are typically wired through alternate + functions on GPIO pins. + +properties: + compatible: + const: qcom,spmi-clkdiv + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: xo + + "#clock-cells": + const: 1 + + qcom,num-clkdivs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of CLKDIV peripherals. + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - qcom,num-clkdivs + +additionalProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + qcom,num-clkdivs = <3>; + + assigned-clocks = <&pm8998_clk_divs 1>, + <&pm8998_clk_divs 2>, + <&pm8998_clk_divs 3>; + assigned-clock-rates = <9600000>, + <9600000>, + <9600000>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index e221985e743f..2b07146161b4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -30,12 +30,12 @@ properties: - qcom,sm8250-videocc clocks: - items: - - description: Board XO source + minItems: 1 + maxItems: 3 clock-names: - items: - - const: bi_tcxo + minItems: 1 + maxItems: 3 '#clock-cells': const: 1 @@ -68,6 +68,57 @@ required: - '#reset-cells' - '#power-domain-cells' +allOf: + - if: + properties: + compatible: + enum: + - qcom,sc7180-videocc + - qcom,sdm845-videocc + - qcom,sm8150-videocc + then: + properties: + clocks: + items: + - description: Board XO source + clock-names: + items: + - const: bi_tcxo + + - if: + properties: + compatible: + enum: + - qcom,sc7280-videocc + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active XO source + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + + - if: + properties: + compatible: + enum: + - qcom,sm8250-videocc + then: + properties: + clocks: + items: + - description: AHB + - description: Board XO source + - description: Board active XO source + clock-names: + items: + - const: iface + - const: bi_tcxo + - const: bi_tcxo_ao + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt deleted file mode 100644 index 2632d3f13004..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2410 Clock Controller - -The S3C2410 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2410, -s3c2440 and s3c2442 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC. - - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC. - - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2410.h header and can be used in device -tree sources. - -External clocks: - -The xti clock used as input for the plls is generated outside the SoC. It is -expected that is are defined using standard clock bindings with a -clock-output-names value of "xti". - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2410-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt deleted file mode 100644 index 21a8c23e658f..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2412 Clock Controller - -The S3C2412 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2412 -and s3c2413 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be "samsung,s3c2412-clock" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2412.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2412-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2412-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt deleted file mode 100644 index 985c0f574e9a..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Samsung S3C2443 Clock Controller - -The S3C2443 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to all SoCs in -the s3c24x family starting with the s3c2443. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC. - - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC. - - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2443.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_uart" - external uart clock - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2416-clock"; - reg = <0x4c000000 0x40>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml index c3be1b600007..c79e752283aa 100644 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> description: diff --git a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml index 9a0cc7341630..4e82582fb2f3 100644 --- a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml +++ b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml @@ -61,40 +61,7 @@ required: examples: - | - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - clock { - compatible = "socionext,uniphier-ld11-clock"; - #clock-cells = <1>; - }; - - // other nodes ... - }; - - - | - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - clock { - compatible = "socionext,uniphier-ld11-mio-clock"; - #clock-cells = <1>; - }; - - // other nodes ... - }; - - - | - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - clock { - compatible = "socionext,uniphier-ld11-peri-clock"; - #clock-cells = <1>; - }; - - // other nodes ... + clock-controller { + compatible = "socionext,uniphier-ld11-clock"; + #clock-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt index cc5e190390b7..f28e1adad428 100644 --- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt @@ -1,12 +1,12 @@ ========================================== -ARM CPUs capacity bindings +CPU capacity bindings ========================================== ========================================== 1 - Introduction ========================================== -ARM systems may be configured to have cpus with different power/performance +Some systems may be configured to have cpus with different power/performance characteristics within the same chip. In this case, additional information has to be made available to the kernel for it to be aware of such differences and take decisions accordingly. diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 903b31129f01..e4aa8c67d532 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -26,8 +26,13 @@ properties: items: - enum: - qcom,qdu1000-cpufreq-epss + - qcom,sc7280-cpufreq-epss + - qcom,sc8280xp-cpufreq-epss - qcom,sm6375-cpufreq-epss - qcom,sm8250-cpufreq-epss + - qcom,sm8350-cpufreq-epss + - qcom,sm8450-cpufreq-epss + - qcom,sm8550-cpufreq-epss - const: qcom,cpufreq-epss reg: @@ -54,6 +59,17 @@ properties: - const: xo - const: alternate + interrupts: + minItems: 1 + maxItems: 3 + + interrupt-names: + minItems: 1 + items: + - const: dcvsh-irq-0 + - const: dcvsh-irq-1 + - const: dcvsh-irq-2 + '#freq-domain-cells': const: 1 diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml index 9c086eac6ca7..6f5e7904181f 100644 --- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml @@ -17,6 +17,9 @@ description: | on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level according to the required OPPs defined in the CPU OPP tables. + For old implementation efuses are parsed to select the correct opp table and + voltage and CPR is not supported/used. + select: properties: compatible: @@ -33,37 +36,65 @@ select: required: - compatible -properties: - cpus: - type: object - - patternProperties: - '^cpu@[0-9a-f]+$': - type: object - - properties: - power-domains: - maxItems: 1 - - power-domain-names: - items: - - const: cpr - - required: - - power-domains - - power-domain-names - patternProperties: '^opp-table(-[a-z0-9]+)?$': - if: + allOf: + - if: + properties: + compatible: + const: operating-points-v2-kryo-cpu + then: + $ref: /schemas/opp/opp-v2-kryo-cpu.yaml# + + - if: + properties: + compatible: + const: operating-points-v2-qcom-level + then: + $ref: /schemas/opp/opp-v2-qcom-level.yaml# + + unevaluatedProperties: false + +allOf: + - if: properties: compatible: - const: operating-points-v2-kryo-cpu + contains: + enum: + - qcom,qcs404 + then: + properties: + cpus: + type: object + + patternProperties: + '^cpu@[0-9a-f]+$': + type: object + + properties: + power-domains: + maxItems: 1 + + power-domain-names: + items: + - const: cpr + + required: + - power-domains + - power-domain-names + patternProperties: - '^opp-?[0-9]+$': - required: - - required-opps + '^opp-table(-[a-z0-9]+)?$': + if: + properties: + compatible: + const: operating-points-v2-kryo-cpu + then: + patternProperties: + '^opp-?[0-9]+$': + required: + - required-opps additionalProperties: true diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml index 026a9f9e1aeb..4287678aa79f 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml @@ -14,6 +14,7 @@ properties: enum: - allwinner,sun8i-h3-crypto - allwinner,sun8i-r40-crypto + - allwinner,sun20i-d1-crypto - allwinner,sun50i-a64-crypto - allwinner,sun50i-h5-crypto - allwinner,sun50i-h6-crypto @@ -29,6 +30,7 @@ properties: - description: Bus clock - description: Module clock - description: MBus clock + - description: TRNG clock (RC oscillator) minItems: 2 clock-names: @@ -36,6 +38,7 @@ properties: - const: bus - const: mod - const: ram + - const: trng minItems: 2 resets: @@ -44,19 +47,33 @@ properties: if: properties: compatible: - const: allwinner,sun50i-h6-crypto + enum: + - allwinner,sun20i-d1-crypto then: properties: clocks: - minItems: 3 + minItems: 4 clock-names: - minItems: 3 + minItems: 4 else: - properties: - clocks: - maxItems: 2 - clock-names: - maxItems: 2 + if: + properties: + compatible: + const: allwinner,sun50i-h6-crypto + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + minItems: 3 + maxItems: 3 + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 required: - compatible diff --git a/Documentation/devicetree/bindings/crypto/aspeed,ast2600-acry.yaml b/Documentation/devicetree/bindings/crypto/aspeed,ast2600-acry.yaml new file mode 100644 index 000000000000..b18f178aac06 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/aspeed,ast2600-acry.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED ACRY ECDSA/RSA Hardware Accelerator Engines + +maintainers: + - Neal Liu <neal_liu@aspeedtech.com> + +description: + The ACRY ECDSA/RSA engines is designed to accelerate the throughput + of ECDSA/RSA signature and verification. Basically, ACRY can be + divided into two independent engines - ECC Engine and RSA Engine. + +properties: + compatible: + enum: + - aspeed,ast2600-acry + + reg: + items: + - description: acry base address & size + - description: acry sram base address & size + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ast2600-clock.h> + acry: crypto@1e6fa000 { + compatible = "aspeed,ast2600-acry"; + reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>; + interrupts = <160>; + clocks = <&syscon ASPEED_CLK_GATE_RSACLK>; + }; diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml index 0ccaab16dc61..0b7383b3106b 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator maintainers: - - Tudor Ambarus <tudor.ambarus@microchip.com> + - Tudor Ambarus <tudor.ambarus@linaro.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml index 5163c51b4547..ee2ffb034325 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator maintainers: - - Tudor Ambarus <tudor.ambarus@microchip.com> + - Tudor Ambarus <tudor.ambarus@linaro.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml index fcc5adf03cad..3d6ed24b1b00 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Triple Data Encryption Standard (TDES) HW cryptographic accelerator maintainers: - - Tudor Ambarus <tudor.ambarus@microchip.com> + - Tudor Ambarus <tudor.ambarus@linaro.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index 4ccb335e8063..b767ec72a999 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -6,12 +6,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 HASH +description: The STM32 HASH block is built on the HASH block found in + the STn8820 SoC introduced in 2007, and subsequently used in the U8500 + SoC in 2010. + maintainers: - Lionel Debieve <lionel.debieve@foss.st.com> properties: compatible: enum: + - st,stn8820-hash + - stericsson,ux500-hash - st,stm32f456-hash - st,stm32f756-hash @@ -41,11 +47,26 @@ properties: maximum: 2 default: 0 + power-domains: + maxItems: 1 + required: - compatible - reg - clocks - - interrupts + +allOf: + - if: + properties: + compatible: + items: + const: stericsson,ux500-hash + then: + properties: + interrupts: false + else: + required: + - interrupts additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt deleted file mode 100644 index 525a4bfd8634..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt +++ /dev/null @@ -1,112 +0,0 @@ -Cadence DSI bridge -================== - -The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes. - -Required properties: -- compatible: should be set to "cdns,dsi". -- reg: physical base address and length of the controller's registers. -- interrupts: interrupt line connected to the DSI bridge. -- clocks: DSI bridge clocks. -- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk". -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy". -- #address-cells: must be set to 1. -- #size-cells: must be set to 0. - -Optional properties: -- resets: DSI reset lines. -- reset-names: can contain "dsi_p_rst". - -Required subnodes: -- ports: Ports as described in Documentation/devicetree/bindings/graph.txt. - 2 ports are available: - * port 0: this port is only needed if some of your DSI devices are - controlled through an external bus like I2C or SPI. Can have at - most 4 endpoints. The endpoint number is directly encoding the - DSI virtual channel used by this device. - * port 1: represents the DPI input. - Other ports will be added later to support the new kind of inputs. - -- one subnode per DSI device connected on the DSI bus. Each DSI device should - contain a reg property encoding its virtual channel. - -Example: - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - - panel: dsi-dev@0 { - compatible = "<vendor,panel>"; - reg = <0>; - }; - }; - -or - - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi0_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_panel_input>; - }; - }; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - }; - - i2c@xxx { - panel: panel@59 { - compatible = "<vendor,panel>"; - reg = <0x59>; - - port { - dsi_panel_input: endpoint { - remote-endpoint = <&dsi0_output>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml new file mode 100644 index 000000000000..23060324d16e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DSI bridge + +maintainers: + - Boris Brezillon <boris.brezillon@bootlin.com> + +description: | + CDNS DSI is a bridge device which converts DPI to DSI + +properties: + compatible: + enum: + - cdns,dsi + - ti,j721e-dsi + + reg: + minItems: 1 + items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. + + clocks: + items: + - description: PSM clock, used by the IP + - description: sys clock, used by the IP + + clock-names: + items: + - const: dsi_p_clk + - const: dsi_sys_clk + + phys: + maxItems: 1 + + phy-names: + const: dphy + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: dsi_p_rst + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port representing the DSI output. It can have + at most 4 endpoints. The endpoint number is directly encoding + the DSI virtual channel used by this device. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port representing the DPI input. + + required: + - port@1 + +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: ti,j721e-dsi + then: + properties: + reg: + minItems: 2 + maxItems: 2 + power-domains: + maxItems: 1 + else: + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy0>; + phy-names = "dphy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + + panel@0 { + compatible = "panasonic,vvx10f034n00"; + reg = <0>; + power-supply = <&vcc_lcd_reg>; + }; + }; + }; + + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fd0c0000 { + compatible = "cdns,dsi"; + reg = <0x0 0xfd0c0000 0x0 0x1000>; + clocks = <&pclk>, <&sysclk>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + interrupts = <1>; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_panel_input>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index b19be0804abe..6e0e3ba9b49e 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -16,7 +16,9 @@ description: | properties: compatible: - const: fsl,imx8mp-ldb + enum: + - fsl,imx8mp-ldb + - fsl,imx93-ldb clocks: maxItems: 1 @@ -57,6 +59,18 @@ required: - clocks - ports +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx93-ldb + then: + properties: + ports: + properties: + port@2: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml index b697c42399ea..c9a882ee6d98 100644 --- a/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml @@ -52,9 +52,49 @@ properties: maxItems: 1 description: extcon specifier for the Power Delivery - port: - $ref: /schemas/graph.yaml#/properties/port - description: A port node pointing to DPI host port node + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: A port node pointing to DPI host port node + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + link-frequencies: + minItems: 1 + maxItems: 1 + description: Allowed max link frequencies in Hz + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Video port for DP output + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + uniqueItems: true + items: + - enum: [ 0, 1 ] + - const: 1 + - const: 2 + - const: 3 + + required: + - port@0 + - port@1 required: - compatible @@ -63,6 +103,7 @@ required: - interrupts - reset-gpios - extcon + - ports additionalProperties: false @@ -85,9 +126,24 @@ examples: reset-gpios = <&pio 179 1>; extcon = <&usbc_extcon>; - port { - it6505_in: endpoint { - remote-endpoint = <&dpi_out>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + it6505_in: endpoint { + remote-endpoint = <&dpi_out>; + link-frequencies = /bits/ 64 <150000000>; + }; + }; + + port@1 { + reg = <1>; + it6505_out: endpoint { + remote-endpoint = <&dp_in>; + data-lanes = <0 1>; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml index d3454da1247a..a7eb2603691f 100644 --- a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: - const: ite,it66121 + enum: + - ite,it66121 + - ite,it6610 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml index afeeb967393d..d33026f85e19 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml @@ -11,13 +11,14 @@ maintainers: description: | This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas - R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up + R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up to four data lanes. properties: compatible: enum: - renesas,r8a779a0-dsi-csi2-tx # for V3U + - renesas,r8a779g0-dsi-csi2-tx # for V4H reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index 131d5b63ec4f..e08c24633926 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -22,6 +22,7 @@ properties: items: - enum: - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L - const: renesas,rzg2l-mipi-dsi reg: diff --git a/Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml b/Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml new file mode 100644 index 000000000000..6d1a36b76fcb --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Image SiI8620 HDMI/MHL bridge + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +properties: + compatible: + const: sil,sii8620 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + cvcc10-supply: + description: Digital Core Supply Voltage (1.0V) + + interrupts: + maxItems: 1 + + iovcc18-supply: + description: I/O Supply Voltage (1.8V) + + reset-gpios: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + unevaluatedProperties: false + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for HDMI (encoder) input + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + MHL to connector port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - cvcc10-supply + - interrupts + - iovcc18-supply + - reset-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@39 { + reg = <0x39>; + compatible = "sil,sii8620"; + cvcc10-supply = <&ldo36_reg>; + iovcc18-supply = <&ldo34_reg>; + interrupt-parent = <&gpf0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>; + clocks = <&pmu_system_controller 0>; + clock-names = "xtal"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; + }; + + port@1 { + reg = <1>; + mhl_to_musb_con: endpoint { + remote-endpoint = <&musb_con_to_mhl>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt b/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt deleted file mode 100644 index b05052f7d62f..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt +++ /dev/null @@ -1,33 +0,0 @@ -Silicon Image SiI8620 HDMI/MHL bridge bindings - -Required properties: - - compatible: "sil,sii8620" - - reg: i2c address of the bridge - - cvcc10-supply: Digital Core Supply Voltage (1.0V) - - iovcc18-supply: I/O Supply Voltage (1.8V) - - interrupts: interrupt specifier of INT pin - - reset-gpios: gpio specifier of RESET pin - - clocks, clock-names: specification and name of "xtal" clock - - video interfaces: Device node can contain video interface port - node for HDMI encoder according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - sii8620@39 { - reg = <0x39>; - compatible = "sil,sii8620"; - cvcc10-supply = <&ldo36_reg>; - iovcc18-supply = <&ldo34_reg>; - interrupt-parent = <&gpf0>; - interrupts = <2 0>; - reset-gpio = <&gpv7 0 0>; - clocks = <&pmu_system_controller 0>; - clock-names = "xtal"; - - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index d4d585485e7b..92741486c24d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -31,6 +31,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-aal + - mediatek,mt8188-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal - const: mediatek,mt8183-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 63fb02014a56..b04820c95b22 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -27,12 +27,13 @@ properties: - const: mediatek,mt8192-disp-ccorr - items: - enum: + - mediatek,mt8188-disp-ccorr - mediatek,mt8195-disp-ccorr - const: mediatek,mt8192-disp-ccorr - items: - enum: - mediatek,mt8186-disp-ccorr - - const: mediatek,mt8183-disp-ccorr + - const: mediatek,mt8192-disp-ccorr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index d2f89ee7996f..62306c88f485 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -37,6 +37,7 @@ properties: - enum: - mediatek,mt8183-disp-color - mediatek,mt8186-disp-color + - mediatek,mt8188-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color - const: mediatek,mt8173-disp-color diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 8ad8187c02d1..5c7445c174e5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-dither + - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither - const: mediatek,mt8183-disp-dither diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index a89ea0ea7542..a5c6a91fac71 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-gamma + - mediatek,mt8188-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma - const: mediatek,mt8183-disp-gamma diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index a2a27d0ca038..065e526f950e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -36,6 +36,7 @@ properties: - const: mediatek,mt2701-disp-ovl - items: - enum: + - mediatek,mt8188-disp-ovl - mediatek,mt8195-disp-ovl - const: mediatek,mt8183-disp-ovl - items: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml index 654080bfbdfb..27de64495401 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-postmask + - mediatek,mt8188-disp-postmask - const: mediatek,mt8192-disp-postmask reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index 0882ae86e6c4..3ade2ece3fed 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -33,6 +33,10 @@ properties: - const: mediatek,mt8195-disp-rdma - items: - enum: + - mediatek,mt8188-disp-rdma + - const: mediatek,mt8195-disp-rdma + - items: + - enum: - mediatek,mt7623-disp-rdma - mediatek,mt2712-disp-rdma - const: mediatek,mt2701-disp-rdma diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index f2515af8256f..0e8d8df686dc 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -21,6 +21,9 @@ properties: - qcom,sc7280-edp - qcom,sc8180x-dp - qcom,sc8180x-edp + - qcom,sc8280xp-dp + - qcom,sc8280xp-edp + - qcom,sdm845-dp - qcom,sm8350-dp reg: @@ -68,8 +71,7 @@ properties: items: - const: dp - operating-points-v2: - maxItems: 1 + operating-points-v2: true opp-table: true @@ -81,6 +83,7 @@ properties: data-lanes: $ref: /schemas/types.yaml#/definitions/uint32-array + deprecated: true minItems: 1 maxItems: 4 items: @@ -102,8 +105,28 @@ properties: description: Input endpoint of the controller port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base description: Output endpoint of the controller + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + minItems: 1 + maxItems: 4 + items: + enum: [ 0, 1, 2, 3 ] + + link-frequencies: + minItems: 1 + maxItems: 4 + items: + enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ] + + required: + - port@0 + - port@1 required: - compatible @@ -127,11 +150,10 @@ allOf: enum: - qcom,sc7280-edp - qcom,sc8180x-edp + - qcom,sc8280xp-edp then: properties: "#sound-dai-cells": false - reg: - maxItems: 4 else: properties: aux-bus: false @@ -193,6 +215,8 @@ examples: reg = <1>; endpoint { remote-endpoint = <&typec>; + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; }; }; diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml index 8ffbc30c6b7f..3f953aa5e694 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -13,7 +13,15 @@ maintainers: description: | Common properties for QCom DPU display controller. +# Do not select this by default, otherwise it is also selected for all +# display-controller@ nodes +select: + false + properties: + $nodename: + pattern: '^display-controller@[0-9a-f]+$' + interrupts: maxItems: 1 @@ -40,10 +48,6 @@ properties: - port@0 required: - - compatible - - reg - - reg-names - - clocks - interrupts - power-domains - operating-points-v2 diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index f2c143730a55..e75a3efe4dac 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -9,14 +9,33 @@ title: Qualcomm Display DSI controller maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> -allOf: - - $ref: "../dsi-controller.yaml#" - properties: compatible: - enum: - - qcom,mdss-dsi-ctrl - - qcom,dsi-ctrl-6g-qcm2290 + oneOf: + - items: + - enum: + - qcom,apq8064-dsi-ctrl + - qcom,msm8916-dsi-ctrl + - qcom,msm8953-dsi-ctrl + - qcom,msm8974-dsi-ctrl + - qcom,msm8996-dsi-ctrl + - qcom,msm8998-dsi-ctrl + - qcom,qcm2290-dsi-ctrl + - qcom,sc7180-dsi-ctrl + - qcom,sc7280-dsi-ctrl + - qcom,sdm660-dsi-ctrl + - qcom,sdm845-dsi-ctrl + - qcom,sm8150-dsi-ctrl + - qcom,sm8250-dsi-ctrl + - qcom,sm8350-dsi-ctrl + - qcom,sm8450-dsi-ctrl + - qcom,sm8550-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + - items: + - enum: + - dsi-ctrl-6g-qcm2290 + - const: qcom,mdss-dsi-ctrl + deprecated: true reg: maxItems: 1 @@ -28,22 +47,23 @@ properties: maxItems: 1 clocks: - items: - - description: Display byte clock - - description: Display byte interface clock - - description: Display pixel clock - - description: Display escape clock - - description: Display AHB clock - - description: Display AXI clock + description: | + Several clocks are used, depending on the variant. Typical ones are:: + - bus:: Display AHB clock. + - byte:: Display byte clock. + - byte_intf:: Display byte interface clock. + - core:: Display core clock. + - core_mss:: Core MultiMedia SubSystem clock. + - iface:: Display AXI clock. + - mdp_core:: MDP Core clock. + - mnoc:: MNOC clock + - pixel:: Display pixel clock. + minItems: 3 + maxItems: 9 clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus + minItems: 3 + maxItems: 9 phys: maxItems: 1 @@ -52,10 +72,6 @@ properties: deprecated: true const: dsi - "#address-cells": true - - "#size-cells": true - syscon-sfpb: description: A phandle to mmss_sfpb syscon node (only for DSIv2). $ref: "/schemas/types.yaml#/definitions/phandle" @@ -67,12 +83,16 @@ properties: 2 DSI links. assigned-clocks: - maxItems: 2 + minItems: 2 + maxItems: 4 description: | Parents of "byte" and "pixel" for the given platform. + For DSIv2 platforms this should contain "byte", "esc", "src" and + "pixel_src" clocks. assigned-clock-parents: - maxItems: 2 + minItems: 2 + maxItems: 4 description: | The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. @@ -103,7 +123,7 @@ properties: properties: data-lanes: maxItems: 4 - minItems: 4 + minItems: 1 items: enum: [ 0, 1, 2, 3 ] @@ -119,7 +139,7 @@ properties: properties: data-lanes: maxItems: 4 - minItems: 4 + minItems: 1 items: enum: [ 0, 1, 2, 3 ] @@ -127,6 +147,26 @@ properties: - port@0 - port@1 + avdd-supply: + description: + Phandle to vdd regulator device node + + vcca-supply: + description: + Phandle to vdd regulator device node + + vdd-supply: + description: + VDD regulator + + vddio-supply: + description: + VDD-IO regulator + + vdda-supply: + description: + VDDA regulator + required: - compatible - reg @@ -137,11 +177,194 @@ required: - phys - assigned-clocks - assigned-clock-parents - - power-domains - - operating-points-v2 - ports -additionalProperties: false +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,apq8064-dsi-ctrl + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: iface + - const: bus + - const: core_mmss + - const: src + - const: byte + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8916-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8953-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8974-dsi-ctrl + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + - const: core_mmss + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-dsi-ctrl + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: mdp_core + - const: byte + - const: iface + - const: bus + - const: core_mmss + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-dsi-ctrl + - qcom,sc7280-dsi-ctrl + - qcom,sm8150-dsi-ctrl + - qcom,sm8250-dsi-ctrl + - qcom,sm8350-dsi-ctrl + - qcom,sm8450-dsi-ctrl + - qcom,sm8550-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm660-dsi-ctrl + then: + properties: + clocks: + maxItems: 9 + clock-names: + items: + - const: mdp_core + - const: byte + - const: byte_intf + - const: mnoc + - const: iface + - const: bus + - const: core_mmss + - const: pixel + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-dsi-ctrl + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + +unevaluatedProperties: false examples: - | @@ -151,7 +374,7 @@ examples: #include <dt-bindings/power/qcom-rpmpd.h> dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae94000 0x400>; reg-names = "dsi_ctrl"; diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml index d9ad8b659f58..3ec466c3ab38 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -69,7 +69,6 @@ required: - compatible - reg - reg-names - - vdds-supply unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index 819de5ce0bc9..a43e11d3b00d 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -39,7 +39,6 @@ required: - compatible - reg - reg-names - - vcca-supply unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index 3d8540a06fe2..cf4a338c4661 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp - qcom,dsi-phy-28nm-8960 @@ -34,6 +35,10 @@ properties: vddio-supply: description: Phandle to vdd-io regulator device node. + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: Indicates if the LDO mode PHY regulator is wanted. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index c851770bbdf2..8e9031bbde73 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -18,6 +18,10 @@ properties: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,sc7280-dsi-phy-7nm + - qcom,sm6375-dsi-phy-7nm + - qcom,sm8350-dsi-phy-5nm + - qcom,sm8450-dsi-phy-5nm + - qcom,sm8550-dsi-phy-4nm reg: items: @@ -44,7 +48,6 @@ required: - compatible - reg - reg-names - - vdds-supply unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml index 76d40f7933dd..0f6f08890e7e 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml @@ -4,14 +4,13 @@ $id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Description of Qualcomm Display DSI PHY common dt properties +title: Qualcomm Display DSI PHY Common Properties maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> -description: | - This defines the DSI PHY dt properties which are common for all - dsi phy versions. +description: + Common properties for Qualcomm Display DSI PHY. properties: "#clock-cells": diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index c5f49842dc7b..d4191cca71fb 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -89,7 +89,7 @@ properties: help bring the GPU out of secure mode. properties: memory-region: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 firmware-name: description: | @@ -149,6 +149,8 @@ allOf: description: GPU 3D engine clock - const: rbbmtimer description: GPU RBBM Timer for Adreno 5xx series + - const: rbcpr + description: GPU RB Core Power Reduction clock minItems: 2 maxItems: 7 diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt deleted file mode 100644 index 65d03c58dee6..000000000000 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ /dev/null @@ -1,132 +0,0 @@ -Qualcomm adreno/snapdragon MDP5 display controller - -Description: - -This is the bindings documentation for the MDP5 display -controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. - -MDP5: -Required properties: -- compatible: - * "qcom,mdp5" - MDP5 -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdp_phys" -- interrupts: Interrupt line from MDP5 to MDSS interrupt controller. -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. -- * "bus" -- * "iface" -- * "core" -- * "vsync" -- ports: contains the list of output ports from MDP. These connect to interfaces - that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a - special case since it is a part of the MDP block itself). - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - The availability of output ports can vary across SoC revisions: - - For MSM8974 and APQ8084: - Port 0 -> MDP_INTF0 (eDP) - Port 1 -> MDP_INTF1 (DSI1) - Port 2 -> MDP_INTF2 (DSI2) - Port 3 -> MDP_INTF3 (HDMI) - - For MSM8916: - Port 0 -> MDP_INTF1 (DSI1) - - For MSM8994 and MSM8996: - Port 0 -> MDP_INTF1 (DSI1) - Port 1 -> MDP_INTF2 (DSI2) - Port 2 -> MDP_INTF3 (HDMI) - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - * "tbu" - * "tbu_rt" - -Example: - -/ { - ... - - mdss: mdss@1a00000 { - compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ac8000 0x3000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&gcc MDSS_GDSC>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync" - - interrupts = <0 72 0>; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@1a01000 { - compatible = "qcom,mdp5"; - reg = <0x1a01000 0x90000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0 0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: dsi@1a98000 { - ... - ports { - ... - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - ... - }; - ... - }; - - dsi_phy0: dsi-phy@1a98300 { - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index 27d7242657b2..ccd7d6417523 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -15,7 +15,15 @@ description: Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like DPU display controller, DSI and DP interfaces etc. +# Do not select this by default, otherwise it is also selected for qcom,mdss +# devices. +select: + false + properties: + $nodename: + pattern: "^display-subsystem@[0-9a-f]+$" + reg: maxItems: 1 @@ -70,7 +78,6 @@ properties: - description: MDSS_CORE reset required: - - compatible - reg - reg-names - power-domains diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml new file mode 100644 index 000000000000..ef461ad6ce4a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5) + +description: + MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 + and MSM8996. + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + - Rob Clark <robdclark@gmail.com> + +properties: + compatible: + oneOf: + - const: qcom,mdp5 + deprecated: true + - items: + - enum: + - qcom,apq8084-mdp5 + - qcom,msm8916-mdp5 + - qcom,msm8917-mdp5 + - qcom,msm8953-mdp5 + - qcom,msm8974-mdp5 + - qcom,msm8976-mdp5 + - qcom,msm8994-mdp5 + - qcom,msm8996-mdp5 + - qcom,sdm630-mdp5 + - qcom,sdm660-mdp5 + - const: qcom,mdp5 + + $nodename: + pattern: '^display-controller@[0-9a-f]+$' + + reg: + maxItems: 1 + + reg-names: + items: + - const: mdp_phys + + interrupts: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 7 + + clock-names: + oneOf: + - minItems: 4 + items: + - const: iface + - const: bus + - const: core + - const: vsync + - const: lut + - const: tbu + - const: tbu_rt + #MSM8996 has additional iommu clock + - items: + - const: iface + - const: bus + - const: core + - const: iommu + - const: vsync + + interconnects: + minItems: 1 + items: + - description: Interconnect path from mdp0 (or a single mdp) port to the data bus + - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from rotator port to the data bus + + interconnect-names: + minItems: 1 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: rotator-mem + + iommus: + items: + - description: apps SMMU with the Stream-ID mask for Hard-Fail port0 + + power-domains: + maxItems: 1 + + operating-points-v2: true + opp-table: + type: object + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: > + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. MDP5 devices support up to 4 ports: + one or two DSI ports, HDMI and eDP. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/properties/port + + # at least one port is required + required: + - port@0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8916.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + display-controller@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x1a01000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index ba0460268731..20889e409430 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -15,6 +15,9 @@ description: encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. properties: + $nodename: + pattern: "^display-subsystem@[0-9a-f]+$" + compatible: enum: - qcom,mdss @@ -44,18 +47,30 @@ properties: The MDSS power domain provided by GCC clocks: - minItems: 1 - items: - - description: Display abh clock - - description: Display axi clock - - description: Display vsync clock + oneOf: + - minItems: 3 + items: + - description: Display abh clock + - description: Display axi clock + - description: Display vsync clock + - description: Display core clock + - minItems: 1 + items: + - description: Display abh clock + - description: Display core clock clock-names: - minItems: 1 - items: - - const: iface - - const: bus - - const: vsync + oneOf: + - minItems: 3 + items: + - const: iface + - const: bus + - const: vsync + - const: core + - minItems: 1 + items: + - const: iface + - const: core "#address-cells": const: 1 @@ -84,17 +99,19 @@ required: - ranges patternProperties: - "^mdp@[1-9a-f][0-9a-f]*$": + "^display-controller@[1-9a-f][0-9a-f]*$": type: object properties: compatible: - const: qcom,mdp5 + contains: + const: qcom,mdp5 "^dsi@[1-9a-f][0-9a-f]*$": type: object properties: compatible: - const: qcom,mdss-dsi-ctrl + contains: + const: qcom,mdss-dsi-ctrl "^phy@[1-9a-f][0-9a-f]*$": type: object @@ -107,12 +124,6 @@ patternProperties: - qcom,dsi-phy-20nm - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-lp - - "^hdmi-phy@[1-9a-f][0-9a-f]*$": - type: object - properties: - compatible: - enum: - qcom,hdmi-phy-8084 - qcom,hdmi-phy-8660 - qcom,hdmi-phy-8960 @@ -137,7 +148,7 @@ examples: - | #include <dt-bindings/clock/qcom,gcc-msm8916.h> #include <dt-bindings/interrupt-controller/arm-gic.h> - mdss@1a00000 { + display-subsystem@1a00000 { compatible = "qcom,mdss"; reg = <0x1a00000 0x1000>, <0x1ac8000 0x3000>; @@ -161,8 +172,8 @@ examples: #size-cells = <1>; ranges; - mdp@1a01000 { - compatible = "qcom,mdp5"; + display-controller@1a01000 { + compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml index b02adba36e9e..8d3cd46260fb 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display DPU dt properties for MSM8998 target +title: Qualcomm Display DPU on MSM8998 maintainers: - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> @@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - items: - - const: qcom,msm8998-dpu + const: qcom,msm8998-dpu reg: items: @@ -46,6 +45,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml index cf52ff77a41a..3c2b6ed98a56 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml @@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: - items: - - const: qcom,msm8998-mdss + const: qcom,msm8998-mdss clocks: items: @@ -47,7 +46,9 @@ patternProperties: type: object properties: compatible: - const: qcom,mdss-dsi-ctrl + items: + - const: qcom,msm8998-dsi-ctrl + - const: qcom,mdss-dsi-ctrl "^phy@[0-9a-f]+$": type: object @@ -55,6 +56,9 @@ patternProperties: compatible: const: qcom,dsi-phy-10nm-8998 +required: + - compatible + unevaluatedProperties: false examples: @@ -126,7 +130,7 @@ examples: }; dsi@c994000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0c994000 0x400>; reg-names = "dsi_ctrl"; @@ -196,7 +200,7 @@ examples: }; dsi@c996000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0c996000 0x400>; reg-names = "dsi_ctrl"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml index a7b382f01b56..414f4e7ebdf1 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display DPU dt properties for QCM2290 target +title: Qualcomm Display DPU on QCM2290 maintainers: - Loic Poulain <loic.poulain@linaro.org> @@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - items: - - const: qcom,qcm2290-dpu + const: qcom,qcm2290-dpu reg: items: @@ -42,6 +41,13 @@ properties: - const: lut - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index d6f043a4b08d..2995b84b2cd4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: - items: - - const: qcom,qcm2290-mdss + const: qcom,qcm2290-mdss clocks: items: @@ -61,6 +60,9 @@ patternProperties: compatible: const: qcom,dsi-phy-14nm-2290 +required: + - compatible + unevaluatedProperties: false examples: @@ -72,7 +74,7 @@ examples: #include <dt-bindings/interconnect/qcom,qcm2290.h> #include <dt-bindings/power/qcom-rpmpd.h> - mdss@5e00000 { + display-subsystem@5e00000 { #address-cells = <1>; #size-cells = <1>; compatible = "qcom,qcm2290-mdss"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index bd590a6b5b96..1fb8321d9ee8 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display DPU dt properties for SC7180 target +title: Qualcomm Display DPU on SC7180 maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> @@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - items: - - const: qcom,sc7180-dpu + const: qcom,sc7180-dpu reg: items: @@ -44,6 +43,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml index 13e396d61a51..42ef06edddc4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml @@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: - items: - - const: qcom,sc7180-mdss + const: qcom,sc7180-mdss clocks: items: @@ -59,7 +58,9 @@ patternProperties: type: object properties: compatible: - const: qcom,mdss-dsi-ctrl + items: + - const: qcom,sc7180-dsi-ctrl + - const: qcom,mdss-dsi-ctrl "^phy@[0-9a-f]+$": type: object @@ -67,6 +68,9 @@ patternProperties: compatible: const: qcom,dsi-phy-10nm +required: + - compatible + unevaluatedProperties: false examples: @@ -142,7 +146,7 @@ examples: }; dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae94000 0x400>; reg-names = "dsi_ctrl"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 924059b387b6..26dc073bd19a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display DPU dt properties for SC7280 +title: Qualcomm Display DPU on SC7280 maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> @@ -43,6 +43,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index a3de1744ba11..078e1d1a7d2f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -58,7 +58,9 @@ patternProperties: type: object properties: compatible: - const: qcom,mdss-dsi-ctrl + items: + - const: qcom,sc7280-dsi-ctrl + - const: qcom,mdss-dsi-ctrl "^edp@[0-9a-f]+$": type: object @@ -74,6 +76,9 @@ patternProperties: - qcom,sc7280-dsi-phy-7nm - qcom,sc7280-edp-phy +required: + - compatible + unevaluatedProperties: false examples: @@ -162,7 +167,7 @@ examples: }; dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae94000 0x400>; reg-names = "dsi_ctrl"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml new file mode 100644 index 000000000000..f2c8e16cf067 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Display Processing Unit + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Device tree bindings for SC8280XP Display Processing Unit. + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc8280xp.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + interrupt-parent = <&mdss0>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + endpoint { + remote-endpoint = <&mdss0_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + endpoint { + remote-endpoint = <&mdss0_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + endpoint { + remote-endpoint = <&mdss0_dp2_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml new file mode 100644 index 000000000000..c239544bc37f --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Mobile Display Subsystem + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sc8280xp-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + properties: + compatible: + enum: + - qcom,sc8280xp-dp + - qcom,sc8280xp-edp + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc8280xp.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc0 MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdss0_mdp_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + interrupt-parent = <&mdss0>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + endpoint { + remote-endpoint = <&mdss0_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + endpoint { + remote-endpoint = <&mdss0_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + endpoint { + remote-endpoint = <&mdss0_dp2_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml index 5719b45f2860..0f7765d832e7 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display DPU dt properties for SDM845 target +title: Qualcomm Display DPU on SDM845 maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> @@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - items: - - const: qcom,sdm845-dpu + const: qcom,sdm845-dpu reg: items: @@ -42,6 +41,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml index 31ca6f99fc22..6ecb00920d7f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml @@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: - items: - - const: qcom,sdm845-mdss + const: qcom,sdm845-mdss clocks: items: @@ -47,11 +46,19 @@ patternProperties: compatible: const: qcom,sdm845-dpu + "^displayport-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sdm845-dp + "^dsi@[0-9a-f]+$": type: object properties: compatible: - const: qcom,mdss-dsi-ctrl + items: + - const: qcom,sdm845-dsi-ctrl + - const: qcom,mdss-dsi-ctrl "^phy@[0-9a-f]+$": type: object @@ -59,6 +66,9 @@ patternProperties: compatible: const: qcom,dsi-phy-10nm +required: + - compatible + unevaluatedProperties: false examples: @@ -128,7 +138,7 @@ examples: }; dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae94000 0x400>; reg-names = "dsi_ctrl"; @@ -198,7 +208,7 @@ examples: }; dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae96000 0x400>; reg-names = "dsi_ctrl"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml index 4a39a3031409..bf62c2f5325a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display DPU dt properties for SM6115 target +title: Qualcomm Display DPU on SM6115 maintainers: - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> @@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - items: - - const: qcom,sm6115-dpu + const: qcom,sm6115-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml index a86d7f53fa84..2491cb100b33 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml @@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: - items: - - const: qcom,sm6115-mdss + const: qcom,sm6115-mdss clocks: items: @@ -62,7 +61,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> - mdss@5e00000 { + display-subsystem@5e00000 { #address-cells = <1>; #size-cells = <1>; compatible = "qcom,sm6115-mdss"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml new file mode 100644 index 000000000000..2b3f3fe9bdf7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8150-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display hf axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8150.h> + #include <dt-bindings/clock/qcom,gcc-sm8150.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8150.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8150-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml new file mode 100644 index 000000000000..5182e958e069 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml @@ -0,0 +1,332 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SM8150 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8150-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8150-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm8150-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8150.h> + #include <dt-bindings/clock/qcom,gcc-sm8150.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8150.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8150-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8150-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml index 9ff8a265c85f..687c8c170cd4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml @@ -39,6 +39,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml index 0d3be5386b3f..368d3db0ce96 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml @@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: - items: - - const: qcom,sm8250-mdss + const: qcom,sm8250-mdss clocks: items: @@ -55,7 +54,9 @@ patternProperties: type: object properties: compatible: - const: qcom,mdss-dsi-ctrl + items: + - const: qcom,sm8250-dsi-ctrl + - const: qcom,mdss-dsi-ctrl "^phy@[0-9a-f]+$": type: object @@ -63,6 +64,9 @@ patternProperties: compatible: const: qcom,dsi-phy-7nm +required: + - compatible + unevaluatedProperties: false examples: @@ -167,7 +171,7 @@ examples: }; dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae94000 0x400>; reg-names = "dsi_ctrl"; @@ -257,7 +261,7 @@ examples: }; dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0ae96000 0x400>; reg-names = "dsi_ctrl"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml new file mode 100644 index 000000000000..120500395c9a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display DPU + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8350.h> + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8350.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml new file mode 100644 index 000000000000..4d94dbff3054 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display MDSS + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +description: + MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: mdp0-mem + - const: mdp1-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm8350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-5nm-8350 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8350.h> + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8350.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8350-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + iommus = <&apps_smmu 0x820 0x402>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi0_phy>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml new file mode 100644 index 000000000000..0d17ece1c453 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8450-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi + - description: Display sf axi + - description: Display ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml new file mode 100644 index 000000000000..4c6929e2534c --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -0,0 +1,345 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8450-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display sf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8450-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm8450-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-5nm-8450 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160310000{ + opp-hz = /bits/ 64 <160310000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/auo,a030jtn01.yaml b/Documentation/devicetree/bindings/display/panel/auo,a030jtn01.yaml new file mode 100644 index 000000000000..86c834eb4d98 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/auo,a030jtn01.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/auo,a030jtn01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AUO A030JTN01 3.0" (320x480 pixels) 24-bit TFT LCD panel + +description: | + Delta RGB 8-bit panel found in some Retrogame handhelds + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + - Christophe Branchereau <cbranchereau@gmail.com> + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: auo,a030jtn01 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "auo,a030jtn01"; + reg = <0>; + + spi-max-frequency = <10000000>; + + reset-gpios = <&gpe 4 GPIO_ACTIVE_LOW>; + power-supply = <&lcd_power>; + + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&panel_output>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/panel/focaltech,gpt3.yaml b/Documentation/devicetree/bindings/display/panel/focaltech,gpt3.yaml new file mode 100644 index 000000000000..d54e96b2a9e1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/focaltech,gpt3.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/focaltech,gpt3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Focaltech GPT3 3.0" (640x480 pixels) IPS LCD panel + +maintainers: + - Christophe Branchereau <cbranchereau@gmail.com> + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: focaltech,gpt3 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "focaltech,gpt3"; + reg = <0>; + + spi-max-frequency = <3125000>; + + reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; + + backlight = <&backlight>; + power-supply = <&vcc>; + + port { + panel_input: endpoint { + remote-endpoint = <&panel_output>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml new file mode 100644 index 000000000000..1b2a1baa26f9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx8394.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX8394 MIPI-DSI LCD panel controller + +maintainers: + - Ondrej Jirman <megi@xff.cz> + - Javier Martinez Canillas <javierm@redhat.com> + +description: + Device tree bindings for panels based on the Himax HX8394 controller, + such as the HannStar HSD060BHW4 720x1440 TFT LCD panel connected with + a MIPI-DSI video interface. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - hannstar,hsd060bhw4 + - const: himax,hx8394 + + reg: true + + reset-gpios: true + + backlight: true + + port: true + + vcc-supply: + description: Panel power supply + + iovcc-supply: + description: I/O voltage supply + +required: + - compatible + - reg + - reset-gpios + - backlight + - port + - vcc-supply + - iovcc-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "hannstar,hsd060bhw4", "himax,hx8394"; + reg = <0>; + vcc-supply = <®_2v8_p>; + iovcc-supply = <®_1v8_p>; + reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml index c2df8d28aaf5..9b701df5e9d2 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml @@ -22,8 +22,9 @@ description: | The standard defines the following interface signals for type C: - Power: - Vdd: Power supply for display module + Called power-supply in this binding. - Vddi: Logic level supply for interface signals - Combined into one in this binding called: power-supply + Called io-supply in this binding. - Interface: - CSx: Chip select - SCL: Serial clock @@ -80,6 +81,11 @@ properties: Controller data/command selection (D/CX) in 4-line SPI mode. If not set, the controller is in 3-line SPI mode. + io-supply: + description: | + Logic level supply for interface signals (Vddi). + No need to set if this is the same as power-supply. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml b/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml new file mode 100644 index 000000000000..84562a5b710a --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,vtdr6130.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox VTDR6130 AMOLED DSI Panel + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,vtdr6130 + + reg: + maxItems: 1 + description: DSI virtual channel + + vddio-supply: true + vci-supply: true + vdd-supply: true + port: true + reset-gpios: true + +additionalProperties: false + +required: + - compatible + - reg + - vddio-supply + - vci-supply + - vdd-supply + - reset-gpios + - port + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml index b3e588022082..d4830f52c512 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -40,6 +40,7 @@ properties: - renesas,du-r8a77990 # for R-Car E3 compatible DU - renesas,du-r8a77995 # for R-Car D3 compatible DU - renesas,du-r8a779a0 # for R-Car V3U compatible DU + - renesas,du-r8a779g0 # for R-Car V4H compatible DU reg: maxItems: 1 @@ -762,6 +763,7 @@ allOf: contains: enum: - renesas,du-r8a779a0 + - renesas,du-r8a779g0 then: properties: clocks: diff --git a/Documentation/devicetree/bindings/display/simple-framebuffer.yaml b/Documentation/devicetree/bindings/display/simple-framebuffer.yaml index dd64f70b5014..3c9f29e428a4 100644 --- a/Documentation/devicetree/bindings/display/simple-framebuffer.yaml +++ b/Documentation/devicetree/bindings/display/simple-framebuffer.yaml @@ -63,6 +63,11 @@ properties: reg: description: Location and size of the framebuffer memory + memory-region: + maxItems: 1 + description: Phandle to a node describing the memory to be used for the + framebuffer. If present, overrides the "reg" property (if one exists). + clocks: description: List of clocks used by the framebuffer. @@ -94,6 +99,7 @@ properties: * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b + * `x8b8g8r8` - 32-bit pixels, d[23:16]=b, d[15:8]=g, d[7:0]=r enum: - a1r5g5b5 - a2r10g10b10 @@ -105,6 +111,7 @@ properties: - x1r5g5b5 - x2r10g10b10 - x8r8g8b8 + - x8b8g8r8 display: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml index ce5c673f940c..117c371ce24b 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml @@ -20,10 +20,10 @@ properties: - nvidia,tegra194-display '#address-cells': - const: 1 + enum: [ 1, 2 ] '#size-cells': - const: 1 + enum: [ 1, 2 ] reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml index 6eedee503aa0..69be95afd562 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -59,8 +59,7 @@ properties: iommus: maxItems: 1 - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml index 75546f250ad7..511cbe74e729 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml @@ -47,8 +47,7 @@ properties: items: - const: dsi - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml index 0d55e6206b5e..3c095a5491fe 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml @@ -46,8 +46,7 @@ properties: interconnect-names: maxItems: 4 - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml index bf38accd98eb..1026b0bc3dc8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml @@ -49,8 +49,7 @@ properties: interconnect-names: maxItems: 4 - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml index 4755a73473c7..59a52e732ca3 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml @@ -51,8 +51,7 @@ properties: minItems: 4 maxItems: 10 - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: minItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml index 035b9f1f2eb5..f65e59cfffa7 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml @@ -50,8 +50,7 @@ properties: items: - const: hdmi - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml index 913ca104c871..94c5242c03b2 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -90,8 +90,7 @@ properties: items: - const: dma-mem # read - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml index 5f4f0fb4b692..2cd3e60cd0a8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -47,8 +47,7 @@ properties: interconnect-names: maxItems: 6 - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml index 467b015e5700..6c84d8b7eb7b 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml @@ -30,8 +30,7 @@ properties: items: - description: module clock - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 782a4b10150a..a42bf33d1e7d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -55,8 +55,7 @@ properties: minItems: 4 maxItems: 5 - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml index 26d0d8ab7984..02d5bd035409 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml @@ -11,7 +11,7 @@ maintainers: - Maxime Ripard <mripard@kernel.org> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: "#dma-cells": diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index bd599bda2653..ec2d7a789ffe 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -11,7 +11,7 @@ maintainers: - Maxime Ripard <mripard@kernel.org> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: "#dma-cells": diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml index 344dc7e04931..5d554bcfab3d 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml @@ -11,7 +11,7 @@ maintainers: - Maxime Ripard <mripard@kernel.org> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: "#dma-cells": diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml index b53ac7631a76..391bf5838602 100644 --- a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml +++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml @@ -14,7 +14,7 @@ description: | intellectual property (IP) allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/apple,admac.yaml b/Documentation/devicetree/bindings/dma/apple,admac.yaml index 97282469e4af..05163d124ec3 100644 --- a/Documentation/devicetree/bindings/dma/apple,admac.yaml +++ b/Documentation/devicetree/bindings/dma/apple,admac.yaml @@ -18,7 +18,7 @@ maintainers: - Martin PoviÅ¡er <povik+lin@cutebit.org> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/arm-pl08x.yaml b/Documentation/devicetree/bindings/dma/arm-pl08x.yaml index 9193b18fb75f..ab25ae63d2c3 100644 --- a/Documentation/devicetree/bindings/dma/arm-pl08x.yaml +++ b/Documentation/devicetree/bindings/dma/arm-pl08x.yaml @@ -11,7 +11,7 @@ maintainers: allOf: - $ref: /schemas/arm/primecell.yaml# - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: diff --git a/Documentation/devicetree/bindings/dma/dma-controller.yaml b/Documentation/devicetree/bindings/dma/dma-controller.yaml index 538ebadff652..04d150d4d15d 100644 --- a/Documentation/devicetree/bindings/dma/dma-controller.yaml +++ b/Documentation/devicetree/bindings/dma/dma-controller.yaml @@ -10,7 +10,7 @@ maintainers: - Vinod Koul <vkoul@kernel.org> allOf: - - $ref: "dma-common.yaml#" + - $ref: dma-common.yaml# # Everything else is described in the common file properties: diff --git a/Documentation/devicetree/bindings/dma/dma-router.yaml b/Documentation/devicetree/bindings/dma/dma-router.yaml index f8d8c3c88bcc..346fe0fa4460 100644 --- a/Documentation/devicetree/bindings/dma/dma-router.yaml +++ b/Documentation/devicetree/bindings/dma/dma-router.yaml @@ -10,7 +10,7 @@ maintainers: - Vinod Koul <vkoul@kernel.org> allOf: - - $ref: "dma-common.yaml#" + - $ref: dma-common.yaml# description: DMA routers are transparent IP blocks used to route DMA request diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index 050e6cd57727..5fd8fc604261 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -64,7 +64,7 @@ required: - dma-channels allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml b/Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml new file mode 100644 index 000000000000..b95dd8db5a30 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX + +maintainers: + - Joy Zou <joy.zou@nxp.com> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx50-sdma + - fsl,imx51-sdma + - fsl,imx53-sdma + - fsl,imx6q-sdma + - fsl,imx7d-sdma + - const: fsl,imx35-sdma + - items: + - enum: + - fsl,imx6sx-sdma + - fsl,imx6sl-sdma + - const: fsl,imx6q-sdma + - items: + - const: fsl,imx6ul-sdma + - const: fsl,imx6q-sdma + - const: fsl,imx35-sdma + - items: + - const: fsl,imx6sll-sdma + - const: fsl,imx6ul-sdma + - items: + - const: fsl,imx8mq-sdma + - const: fsl,imx7d-sdma + - items: + - enum: + - fsl,imx8mp-sdma + - fsl,imx8mn-sdma + - fsl,imx8mm-sdma + - const: fsl,imx8mq-sdma + - items: + - enum: + - fsl,imx25-sdma + - fsl,imx31-sdma + - fsl,imx35-sdma + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + fsl,sdma-ram-script-name: + $ref: /schemas/types.yaml#/definitions/string + description: Should contain the full path of SDMA RAM scripts firmware. + + "#dma-cells": + const: 3 + description: | + The first cell: request/event ID + + The second cell: peripheral types ID + enum: + - MCU domain SSI: 0 + - Shared SSI: 1 + - MMC: 2 + - SDHC: 3 + - MCU domain UART: 4 + - Shared UART: 5 + - FIRI: 6 + - MCU domain CSPI: 7 + - Shared CSPI: 8 + - SIM: 9 + - ATA: 10 + - CCM: 11 + - External peripheral: 12 + - Memory Stick Host Controller: 13 + - Shared Memory Stick Host Controller: 14 + - DSP: 15 + - Memory: 16 + - FIFO type Memory: 17 + - SPDIF: 18 + - IPU Memory: 19 + - ASRC: 20 + - ESAI: 21 + - SSI Dual FIFO: 22 + description: needs firmware more than ver 2 + - Shared ASRC: 23 + - SAI: 24 + - HDMI Audio: 25 + + The third cell: transfer priority ID + enum: + - High: 0 + - Medium: 1 + - Low: 2 + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle to the General Purpose Register (GPR) node + + fsl,sdma-event-remap: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + maxItems: 2 + items: + items: + - description: GPR register offset + - description: GPR register shift + - description: GPR register value + description: | + Register bits of sdma event remap, the format is <reg shift val>. + The order is <RX>, <TX>. + + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: ahb + + iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle to the On-chip RAM (OCRAM) node. + +required: + - compatible + - reg + - interrupts + - fsl,sdma-ram-script-name + +additionalProperties: false + +examples: + - | + sdma: dma-controller@83fb0000 { + compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; + reg = <0x83fb0000 0x4000>; + interrupts = <6>; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "sdma-imx51.bin"; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml b/Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml new file mode 100644 index 000000000000..add9c77e8b52 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Direct Memory Access (DMA) Controller from i.MX23/i.MX28 + +maintainers: + - Marek Vasut <marex@denx.de> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx6q-dma-apbh + - fsl,imx6sx-dma-apbh + - fsl,imx7d-dma-apbh + - const: fsl,imx28-dma-apbh + - enum: + - fsl,imx23-dma-apbh + - fsl,imx23-dma-apbx + - fsl,imx28-dma-apbh + - fsl,imx28-dma-apbx + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + minItems: 4 + maxItems: 16 + + "#dma-cells": + const: 1 + + dma-channels: + enum: [4, 8, 16] + +required: + - compatible + - reg + - "#dma-cells" + - dma-channels + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-parent = <&irqc>; + + dma-controller@80004000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x80004000 0x2000>; + interrupts = <82 83 84 85 + 88 88 88 88 + 88 88 88 88 + 87 86 0 0>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dma-controller@80024000 { + compatible = "fsl,imx28-dma-apbx"; + reg = <0x80024000 0x2000>; + interrupts = <78 79 66 0 + 80 81 68 69 + 70 71 72 73 + 74 75 76 77>; + #dma-cells = <1>; + dma-channels = <16>; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt deleted file mode 100644 index 12c316ff4834..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ /dev/null @@ -1,118 +0,0 @@ -* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX - -Required properties: -- compatible : Should be one of - "fsl,imx25-sdma" - "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" - "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" - "fsl,imx51-sdma" - "fsl,imx53-sdma" - "fsl,imx6q-sdma" - "fsl,imx7d-sdma" - "fsl,imx6ul-sdma" - "fsl,imx8mq-sdma" - "fsl,imx8mm-sdma" - "fsl,imx8mn-sdma" - "fsl,imx8mp-sdma" - The -to variants should be preferred since they allow to determine the - correct ROM script addresses needed for the driver to work without additional - firmware. -- reg : Should contain SDMA registers location and length -- interrupts : Should contain SDMA interrupt -- #dma-cells : Must be <3>. - The first cell specifies the DMA request/event ID. See details below - about the second and third cell. -- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM - scripts firmware - -The second cell of dma phandle specifies the peripheral type of DMA transfer. -The full ID of peripheral types can be found below. - - ID transfer type - --------------------- - 0 MCU domain SSI - 1 Shared SSI - 2 MMC - 3 SDHC - 4 MCU domain UART - 5 Shared UART - 6 FIRI - 7 MCU domain CSPI - 8 Shared CSPI - 9 SIM - 10 ATA - 11 CCM - 12 External peripheral - 13 Memory Stick Host Controller - 14 Shared Memory Stick Host Controller - 15 DSP - 16 Memory - 17 FIFO type Memory - 18 SPDIF - 19 IPU Memory - 20 ASRC - 21 ESAI - 22 SSI Dual FIFO (needs firmware ver >= 2) - 23 Shared ASRC - 24 SAI - -The third cell specifies the transfer priority as below. - - ID transfer priority - ------------------------- - 0 High - 1 Medium - 2 Low - -Optional properties: - -- gpr : The phandle to the General Purpose Register (GPR) node. -- fsl,sdma-event-remap : Register bits of sdma event remap, the format is - <reg shift val>. - reg is the GPR register offset. - shift is the bit position inside the GPR register. - val is the value of the bit (0 or 1). - -Examples: - -sdma@83fb0000 { - compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; - reg = <0x83fb0000 0x4000>; - interrupts = <6>; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "sdma-imx51.bin"; -}; - -DMA clients connected to the i.MX SDMA controller must use the format -described in the dma.txt file. - -Examples: - -ssi2: ssi@70014000 { - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x70014000 0x4000>; - interrupts = <30>; - clocks = <&clks 49>; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; -}; - -Using the fsl,sdma-event-remap property: - -If we want to use SDMA on the SAI1 port on a MX6SX: - -&sdma { - gpr = <&gpr>; - /* SDMA events remap for SAI1_RX and SAI1_TX */ - fsl,sdma-event-remap = <0 15 1>, <0 16 1>; -}; - -The fsl,sdma-event-remap property in this case has two values: -- <0 15 1> means that the offset is 0, so GPR0 is the register of the -SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. -Setting bit 15 to 1 selects SAI1_RX. -- <0 16 1> means that the offset is 0, so GPR0 is the register of the -SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. -Setting bit 16 to 1 selects SAI1_TX. diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt deleted file mode 100644 index e30e184f50c7..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Freescale MXS DMA - -Required properties: -- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx" -- reg : Should contain registers location and length -- interrupts : Should contain the interrupt numbers of DMA channels. - If a channel is empty/reserved, 0 should be filled in place. -- #dma-cells : Must be <1>. The number cell specifies the channel ID. -- dma-channels : Number of channels supported by the DMA controller - -Optional properties: -- interrupt-names : Name of DMA channel interrupts - -Supported chips: -imx23, imx28. - -Examples: - -dma_apbh: dma-apbh@80004000 { - compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; - interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", - "gpmi0", "gmpi1", "gpmi2", "gmpi3", - "gpmi4", "gmpi5", "gpmi6", "gmpi7", - "hsadc", "lcdif", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; -}; - -dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; - interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", - "saif0", "saif1", "i2c0", "i2c1", - "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", - "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; - #dma-cells = <1>; - dma-channels = <16>; -}; - -DMA clients connected to the MXS DMA controller must use the format -described in the dma.txt file. - -Examples: - -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/dma/ingenic,dma.yaml b/Documentation/devicetree/bindings/dma/ingenic,dma.yaml index fd5b0a8eaed8..37400496e086 100644 --- a/Documentation/devicetree/bindings/dma/ingenic,dma.yaml +++ b/Documentation/devicetree/bindings/dma/ingenic,dma.yaml @@ -10,7 +10,7 @@ maintainers: - Paul Cercueil <paul@crapouillou.net> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/intel,ldma.yaml b/Documentation/devicetree/bindings/dma/intel,ldma.yaml index a5c4be783593..d6bb553a2c6f 100644 --- a/Documentation/devicetree/bindings/dma/intel,ldma.yaml +++ b/Documentation/devicetree/bindings/dma/intel,ldma.yaml @@ -11,7 +11,7 @@ maintainers: - mallikarjunax.reddy@intel.com allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index 9ab4d81ead35..dab468a88942 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -14,7 +14,7 @@ description: | for the UART peripheral bus. allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 851bd50ee67f..a790e5687844 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -16,7 +16,7 @@ maintainers: - Rajesh Gumasta <rgumasta@nvidia.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index fef804565b88..4003dbe94940 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -14,7 +14,7 @@ maintainers: - Jon Hunter <jonathanh@nvidia.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml index 93b4847554fb..ec8b3dc37ca4 100644 --- a/Documentation/devicetree/bindings/dma/owl-dma.yaml +++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml @@ -15,7 +15,7 @@ maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 003098caf709..f1ddcf672261 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -11,7 +11,7 @@ maintainers: - Bjorn Andersson <andersson@kernel.org> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index e7ba1c47a88e..fc5de7b6f19e 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -14,7 +14,7 @@ description: | peripheral buses such as I2C, UART, and SPI. allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: @@ -24,15 +24,18 @@ properties: - qcom,sm6350-gpi-dma - items: - enum: + - qcom,qdu1000-gpi-dma - qcom,sc7280-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma + - qcom,sm8550-gpi-dma - const: qcom,sm6350-gpi-dma - items: - enum: - qcom,sdm670-gpi-dma + - qcom,sm6125-gpi-dma - qcom,sm8150-gpi-dma - qcom,sm8250-gpi-dma - const: qcom,sdm845-gpi-dma diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml index 89b591a05bce..03aa067b1229 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml @@ -10,7 +10,7 @@ maintainers: - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index 1e25c5b0fb4d..f638d3934e71 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -10,7 +10,7 @@ maintainers: - Biju Das <biju.das.jz@bp.renesas.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml index d83013b0dd74..ee9833dcc36c 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml @@ -10,7 +10,7 @@ maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> allOf: - - $ref: "dma-router.yaml#" + - $ref: dma-router.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml index ab287c652b2c..17813599fccb 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml @@ -10,7 +10,7 @@ maintainers: - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index 3271755787b4..a1af0b906365 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -23,7 +23,7 @@ description: | https://static.dev.sifive.com/FU540-C000-v1.0.pdf allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml index c13649bf7f19..5da8291a7de0 100644 --- a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml @@ -11,7 +11,7 @@ maintainers: - Andy Shevchenko <andriy.shevchenko@linux.intel.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index ad107a4d3b33..5c81194e2300 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -13,7 +13,7 @@ description: Synopsys DesignWare AXI DMA Controller DT Binding allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: @@ -113,21 +113,21 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interrupt-controller/irq.h> - /* example with snps,dw-axi-dmac */ - dmac: dma-controller@80000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x80000 0x400>; - clocks = <&core_clk>, <&cfgr_clk>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <27>; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <2>; - snps,data-width = <3>; - snps,block-size = <4096 4096 4096 4096>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <16>; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + /* example with snps,dw-axi-dmac */ + dma-controller@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + clocks = <&core_clk>, <&cfgr_clk>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <27>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; diff --git a/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml index e7bf6dd7da29..23c8a7bf24de 100644 --- a/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml @@ -14,7 +14,7 @@ maintainers: - Masahiro Yamada <yamada.masahiro@socionext.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml b/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml index 371f18773198..da61d1ddc9c3 100644 --- a/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml +++ b/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml @@ -15,7 +15,7 @@ maintainers: - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 158c791d7caa..329847ef096a 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -53,7 +53,7 @@ maintainers: - Amelie Delaunay <amelie.delaunay@foss.st.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: "#dma-cells": diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index 3e0b82d277ca..e722fbcd8a5f 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -10,7 +10,7 @@ maintainers: - Amelie Delaunay <amelie.delaunay@foss.st.com> allOf: - - $ref: "dma-router.yaml#" + - $ref: dma-router.yaml# properties: "#dma-cells": diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml index 08a59bd69a2f..3874544dfa74 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml @@ -53,7 +53,7 @@ maintainers: - Amelie Delaunay <amelie.delaunay@foss.st.com> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: "#dma-cells": diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml index 8bddfb3b6fa0..64845347f44d 100644 --- a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml +++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml @@ -10,7 +10,7 @@ maintainers: - Linus Walleij <linus.walleij@linaro.org> allOf: - - $ref: "dma-controller.yaml#" + - $ref: dma-controller.yaml# properties: "#dma-cells": @@ -147,13 +147,13 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mfd/dbx500-prcmu.h> - dma-controller@801C0000 { - compatible = "stericsson,db8500-dma40", "stericsson,dma40"; - reg = <0x801C0000 0x1000>, <0x40010000 0x800>; - reg-names = "base", "lcpa"; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <3>; - memcpy-channels = <56 57 58 59 60>; - clocks = <&prcmu_clk PRCMU_DMACLK>; + dma-controller@801c0000 { + compatible = "stericsson,db8500-dma40", "stericsson,dma40"; + reg = <0x801c0000 0x1000>, <0x40010000 0x800>; + reg-names = "base", "lcpa"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <3>; + memcpy-channels = <56 57 58 59 60>; + clocks = <&prcmu_clk PRCMU_DMACLK>; }; ... diff --git a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml index a702d2c2ff8d..beecfe7a1732 100644 --- a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml +++ b/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml @@ -28,13 +28,19 @@ description: | PDMAs can be configured via BCDMA split channel's peer registers to match with the configuration of the legacy peripheral. -allOf: - - $ref: /schemas/dma/dma-controller.yaml# - - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# - properties: compatible: - const: ti,am64-dmss-bcdma + enum: + - ti,am62a-dmss-bcdma-csirx + - ti,am64-dmss-bcdma + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + maxItems: 5 "#dma-cells": const: 3 @@ -65,19 +71,13 @@ properties: cell 3: ASEL value for the channel - reg: - maxItems: 5 - - reg-names: - items: - - const: gcfg - - const: bchanrt - - const: rchanrt - - const: tchanrt - - const: ringrt - msi-parent: true + power-domains: + description: + Power domain if available + maxItems: 1 + ti,asel: $ref: /schemas/types.yaml#/definitions/uint32 description: ASEL value for non slave channels @@ -123,10 +123,51 @@ required: - msi-parent - ti,sci - ti,sci-dev-id - - ti,sci-rm-range-bchan - - ti,sci-rm-range-tchan - ti,sci-rm-range-rchan +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# + + - if: + properties: + compatible: + contains: + const: ti,am62a-dmss-bcdma-csirx + then: + properties: + ti,sci-rm-range-bchan: false + ti,sci-rm-range-tchan: false + + reg: + maxItems: 3 + + reg-names: + items: + - const: gcfg + - const: rchanrt + - const: ringrt + + required: + - power-domains + + else: + properties: + reg: + minItems: 5 + + reg-names: + items: + - const: gcfg + - const: bchanrt + - const: rchanrt + - const: tchanrt + - const: ringrt + + required: + - ti,sci-rm-range-bchan + - ti,sci-rm-range-tchan + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml index 7ff428ad3aae..97f6ae9b1236 100644 --- a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml +++ b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml @@ -44,6 +44,7 @@ description: | allOf: - $ref: "../dma-controller.yaml#" + - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# properties: "#dma-cells": @@ -78,14 +79,6 @@ properties: msi-parent: true - ti,sci: - description: phandle to TI-SCI compatible System controller node - $ref: /schemas/types.yaml#/definitions/phandle - - ti,sci-dev-id: - description: TI-SCI device id of UDMAP - $ref: /schemas/types.yaml#/definitions/uint32 - ti,ringacc: description: phandle to the ring accelerator node $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml index 3e63f79890b4..88575da1e6d5 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml @@ -15,7 +15,9 @@ description: | properties: compatible: - const: mediatek,mt8186-dsp + enum: + - mediatek,mt8186-dsp + - mediatek,mt8188-dsp reg: items: diff --git a/Documentation/devicetree/bindings/firmware/amlogic,meson-gxbb-sm.yaml b/Documentation/devicetree/bindings/firmware/amlogic,meson-gxbb-sm.yaml new file mode 100644 index 000000000000..8f50e698760e --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/amlogic,meson-gxbb-sm.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/amlogic,meson-gxbb-sm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Secure Monitor (SM) + +description: + In the Amlogic SoCs the Secure Monitor code is used to provide access to the + NVMEM, enable JTAG, set USB boot, etc... + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + oneOf: + - const: amlogic,meson-gxbb-sm + - items: + - const: amlogic,meson-gx-sm + - const: amlogic,meson-gxbb-sm + + power-controller: + type: object + $ref: /schemas/power/amlogic,meson-sec-pwrc.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + firmware { + secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + }; + }; diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 176796931a22..2f7c51c75e85 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -100,7 +100,9 @@ properties: Channel specifier required when using OP-TEE transport. protocol@11: - type: object + $ref: '#/$defs/protocol-node' + unevaluatedProperties: false + properties: reg: const: 0x11 @@ -112,7 +114,9 @@ properties: - '#power-domain-cells' protocol@13: - type: object + $ref: '#/$defs/protocol-node' + unevaluatedProperties: false + properties: reg: const: 0x13 @@ -124,7 +128,9 @@ properties: - '#clock-cells' protocol@14: - type: object + $ref: '#/$defs/protocol-node' + unevaluatedProperties: false + properties: reg: const: 0x14 @@ -136,7 +142,9 @@ properties: - '#clock-cells' protocol@15: - type: object + $ref: '#/$defs/protocol-node' + unevaluatedProperties: false + properties: reg: const: 0x15 @@ -148,7 +156,9 @@ properties: - '#thermal-sensor-cells' protocol@16: - type: object + $ref: '#/$defs/protocol-node' + unevaluatedProperties: false + properties: reg: const: 0x16 @@ -160,20 +170,31 @@ properties: - '#reset-cells' protocol@17: - type: object + $ref: '#/$defs/protocol-node' + unevaluatedProperties: false + properties: reg: const: 0x17 regulators: type: object + additionalProperties: false description: The list of all regulators provided by this SCMI controller. + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + patternProperties: - '^regulators@[0-9a-f]+$': + '^regulator@[0-9a-f]+$': type: object $ref: "../regulator/regulator.yaml#" + unevaluatedProperties: false properties: reg: @@ -184,15 +205,17 @@ properties: - reg protocol@18: - type: object + $ref: '#/$defs/protocol-node' + unevaluatedProperties: false + properties: reg: const: 0x18 additionalProperties: false -patternProperties: - '^protocol@[0-9a-f]+$': +$defs: + protocol-node: type: object description: Each sub-node represents a protocol supported. If the platform diff --git a/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt b/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt deleted file mode 100644 index c248cd44f727..000000000000 --- a/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Amlogic Secure Monitor - -In the Amlogic SoCs the Secure Monitor code is used to provide access to the -NVMEM, enable JTAG, set USB boot, etc... - -Required properties for the secure monitor node: -- compatible: Should be "amlogic,meson-gxbb-sm" - -Example: - - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - }; diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 25688571ee7c..a66e99812b1f 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -38,6 +38,8 @@ properties: - qcom,scm-msm8994 - qcom,scm-msm8996 - qcom,scm-msm8998 + - qcom,scm-qdu1000 + - qcom,scm-sa8775p - qcom,scm-sc7180 - qcom,scm-sc7280 - qcom,scm-sc8280xp @@ -53,6 +55,7 @@ properties: - qcom,scm-sm8250 - qcom,scm-sm8350 - qcom,scm-sm8450 + - qcom,scm-sm8550 - qcom,scm-qcs404 - const: qcom,scm @@ -73,6 +76,12 @@ properties: '#reset-cells': const: 1 + interrupts: + description: + The wait-queue interrupt that firmware raises as part of handshake + protocol to handle sleeping SCM calls. + maxItems: 1 + qcom,dload-mode: $ref: /schemas/types.yaml#/definitions/phandle-array items: @@ -82,6 +91,32 @@ properties: description: TCSR hardware block allOf: + # Clocks + - if: + properties: + compatible: + contains: + enum: + - qcom,scm-apq8064 + - qcom,scm-apq8084 + - qcom,scm-mdm9607 + - qcom,scm-msm8226 + - qcom,scm-msm8660 + - qcom,scm-msm8916 + - qcom,scm-msm8953 + - qcom,scm-msm8960 + - qcom,scm-msm8974 + - qcom,scm-msm8976 + - qcom,scm-sm6375 + then: + required: + - clocks + - clock-names + else: + properties: + clock-names: false + clocks: false + - if: properties: compatible: @@ -100,10 +135,6 @@ allOf: clocks: maxItems: 1 - required: - - clocks - - clock-names - - if: properties: compatible: @@ -111,6 +142,7 @@ allOf: enum: - qcom,scm-apq8084 - qcom,scm-mdm9607 + - qcom,scm-msm8226 - qcom,scm-msm8916 - qcom,scm-msm8953 - qcom,scm-msm8974 @@ -127,9 +159,31 @@ allOf: minItems: 3 maxItems: 3 - required: - - clocks - - clock-names + # Interconnects + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-sm8450 + - qcom,scm-sm8550 + then: + properties: + interconnects: false + + # Interrupts + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-sm8450 + - qcom,scm-sm8550 + then: + properties: + interrupts: false required: - compatible diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml index 481901269872..02f0b0462377 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -44,8 +44,7 @@ properties: items: - const: fuse - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.txt b/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.txt deleted file mode 100644 index bef353f370d8..000000000000 --- a/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.txt +++ /dev/null @@ -1,20 +0,0 @@ -Fujitsu MB86S7x GPIO Controller -------------------------------- - -Required properties: -- compatible: Should be "fujitsu,mb86s70-gpio" -- reg: Base address and length of register space -- clocks: Specify the clock -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be <2>. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted). - -Examples: - gpio0: gpio@31000000 { - compatible = "fujitsu,mb86s70-gpio"; - reg = <0 0x31000000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clk 0 2 1>; - }; diff --git a/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.yaml b/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.yaml new file mode 100644 index 000000000000..d18d95285465 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fujitsu,mb86s70-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fujitsu MB86S7x GPIO Controller + +maintainers: + - Jassi Brar <jaswinder.singh@linaro.org> + +properties: + compatible: + oneOf: + - items: + - const: socionext,synquacer-gpio + - const: fujitsu,mb86s70-gpio + - const: fujitsu,mb86s70-gpio + + reg: + maxItems: 1 + + '#gpio-cells': + const: 2 + + gpio-controller: true + gpio-line-names: true + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - '#gpio-cells' + - gpio-controller + - clocks + +additionalProperties: false + +examples: + - | + gpio@31000000 { + compatible = "fujitsu,mb86s70-gpio"; + reg = <0x31000000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clk 0 2 1>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt deleted file mode 100644 index 54040a2bfe3a..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt +++ /dev/null @@ -1,97 +0,0 @@ -Spreadtrum EIC controller bindings - -The EIC is the abbreviation of external interrupt controller, which can -be used only in input mode. The Spreadtrum platform has 2 EIC controllers, -one is in digital chip, and another one is in PMIC. The digital chip EIC -controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and -EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub- -module. - -The EIC-debounce sub-module provides up to 8 source input signal -connections. A debounce mechanism is used to capture the input signals' -stable status (millisecond resolution) and a single-trigger mechanism -is introduced into this sub-module to enhance the input event detection -reliability. In addition, this sub-module's clock can be shut off -automatically to reduce power dissipation. Moreover the debounce range -is from 1ms to 4s with a step size of 1ms. The input signal will be -ignored if it is asserted for less than 1 ms. - -The EIC-latch sub-module is used to latch some special power down signals -and generate interrupts, since the EIC-latch does not depend on the APB -clock to capture signals. - -The EIC-async sub-module uses a 32kHz clock to capture the short signals -(microsecond resolution) to generate interrupts by level or edge trigger. - -The EIC-sync is similar with GPIO's input function, which is a synchronized -signal input register. It can generate interrupts by level or edge trigger -when detecting input signals. - -Required properties: -- compatible: Should be one of the following: - "sprd,sc9860-eic-debounce", - "sprd,sc9860-eic-latch", - "sprd,sc9860-eic-async", - "sprd,sc9860-eic-sync", - "sprd,sc2731-eic". -- reg: Define the base and range of the I/O address space containing - the GPIO controller registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be <2>. The first cell is the gpio number and - the second cell is used to specify optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be <2>. Specifies the number of cells needed - to encode interrupt source. -- interrupts: Should be the port interrupt shared by all the gpios. - -Example: - eic_debounce: gpio@40210000 { - compatible = "sprd,sc9860-eic-debounce"; - reg = <0 0x40210000 0 0x80>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - }; - - eic_latch: gpio@40210080 { - compatible = "sprd,sc9860-eic-latch"; - reg = <0 0x40210080 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - }; - - eic_async: gpio@402100a0 { - compatible = "sprd,sc9860-eic-async"; - reg = <0 0x402100a0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - }; - - eic_sync: gpio@402100c0 { - compatible = "sprd,sc9860-eic-sync"; - reg = <0 0x402100c0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmic_eic: gpio@300 { - compatible = "sprd,sc2731-eic"; - reg = <0x300>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt deleted file mode 100644 index eca97d45388f..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt +++ /dev/null @@ -1,28 +0,0 @@ -Spreadtrum GPIO controller bindings - -The controller's registers are organized as sets of sixteen 16-bit -registers with each set controlling a bank of up to 16 pins. A single -interrupt is shared for all of the banks handled by the controller. - -Required properties: -- compatible: Should be "sprd,sc9860-gpio". -- reg: Define the base and range of the I/O address space containing -the GPIO controller registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be <2>. The first cell is the gpio number and -the second cell is used to specify optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be <2>. Specifies the number of cells needed -to encode interrupt source. -- interrupts: Should be the port interrupt shared by all the gpios. - -Example: - ap_gpio: gpio@40280000 { - compatible = "sprd,sc9860-gpio"; - reg = <0 0x40280000 0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/gpio/sprd,gpio-eic.yaml b/Documentation/devicetree/bindings/gpio/sprd,gpio-eic.yaml new file mode 100644 index 000000000000..99fcf970773a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/sprd,gpio-eic.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc EIC controller + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +description: | + The EIC is the abbreviation of external interrupt controller, which can + be used only in input mode. The Spreadtrum platform has 2 EIC controllers, + one is in digital chip, and another one is in PMIC. The digital chip EIC + controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and + EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub- + module. + + The EIC-debounce sub-module provides up to 8 source input signal + connections. A debounce mechanism is used to capture the input signals' + stable status (millisecond resolution) and a single-trigger mechanism + is introduced into this sub-module to enhance the input event detection + reliability. In addition, this sub-module's clock can be shut off + automatically to reduce power dissipation. Moreover the debounce range + is from 1ms to 4s with a step size of 1ms. The input signal will be + ignored if it is asserted for less than 1 ms. + + The EIC-latch sub-module is used to latch some special power down signals + and generate interrupts, since the EIC-latch does not depend on the APB + clock to capture signals. + + The EIC-async sub-module uses a 32kHz clock to capture the short signals + (microsecond resolution) to generate interrupts by level or edge trigger. + + The EIC-sync is similar with GPIO's input function, which is a synchronized + signal input register. It can generate interrupts by level or edge trigger + when detecting input signals. + +properties: + compatible: + oneOf: + - enum: + - sprd,sc9860-eic-debounce + - sprd,sc9860-eic-latch + - sprd,sc9860-eic-async + - sprd,sc9860-eic-sync + - sprd,sc2731-eic + - items: + - enum: + - sprd,ums512-eic-debounce + - const: sprd,sc9860-eic-debounce + - items: + - enum: + - sprd,ums512-eic-latch + - const: sprd,sc9860-eic-latch + - items: + - enum: + - sprd,ums512-eic-async + - const: sprd,sc9860-eic-async + - items: + - enum: + - sprd,ums512-eic-sync + - const: sprd,sc9860-eic-sync + - items: + - enum: + - sprd,sc2730-eic + - const: sprd,sc2731-eic + + reg: + minItems: 1 + maxItems: 3 + description: + EIC controller can support maximum 3 banks which has its own + address base. + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + description: + The interrupt shared by all GPIO lines for this controller. + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + eic_debounce: gpio@40210000 { + compatible = "sprd,sc9860-eic-debounce"; + reg = <0 0x40210000 0 0x80>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/sprd,gpio.yaml b/Documentation/devicetree/bindings/gpio/sprd,gpio.yaml new file mode 100644 index 000000000000..483168838128 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/sprd,gpio.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/sprd,gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc GPIO controller + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +description: | + The controller's registers are organized as sets of sixteen 16-bit + registers with each set controlling a bank of up to 16 pins. A single + interrupt is shared for all of the banks handled by the controller. + +properties: + compatible: + oneOf: + - const: sprd,sc9860-gpio + - items: + - enum: + - sprd,ums512-gpio + - const: sprd,sc9860-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + description: The interrupt shared by all GPIO lines for this controller. + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ap_gpio: gpio@40280000 { + compatible = "sprd,sc9860-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml index 10e5a53e447b..38478dad8b25 100644 --- a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml +++ b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml @@ -26,11 +26,15 @@ properties: resets: maxItems: 1 + '#hwlock-cells': + const: 1 + required: - compatible - reg - clocks - resets + - "#hwlock-cells" additionalProperties: false @@ -44,5 +48,6 @@ examples: reg = <0x01c18000 0x1000>; clocks = <&ccu CLK_BUS_SPINLOCK>; resets = <&ccu RST_BUS_SPINLOCK>; + #hwlock-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml index d794deb08bb7..ca2b47320689 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml @@ -52,16 +52,16 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; pwmon@5a { - compatible = "adi,adm1177"; - reg = <0x5a>; - shunt-resistor-micro-ohms = <50000>; /* 50 mOhm */ - adi,shutdown-threshold-microamp = <1059000>; /* 1.059 A */ - adi,vrange-high-enable; + compatible = "adi,adm1177"; + reg = <0x5a>; + shunt-resistor-micro-ohms = <50000>; /* 50 mOhm */ + adi,shutdown-threshold-microamp = <1059000>; /* 1.059 A */ + adi,vrange-high-enable; }; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1266.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1266.yaml index 43b4f4f57b49..4f8e11bd5142 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1266.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1266.yaml @@ -39,13 +39,13 @@ additionalProperties: false examples: - | - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; adm1266@40 { - compatible = "adi,adm1266"; - reg = <0x40>; + compatible = "adi,adm1266"; + reg = <0x40>; }; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml b/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml index f2f99afb3a3b..0cf3ed6212a6 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml @@ -49,15 +49,15 @@ additionalProperties: false examples: - | fpga_axi: fpga-axi { - #address-cells = <0x2>; - #size-cells = <0x1>; - - axi_fan_control: axi-fan-control@80000000 { - compatible = "adi,axi-fan-control-1.00.a"; - reg = <0x0 0x80000000 0x10000>; - clocks = <&clk 71>; - interrupts = <0 110 0>; - pulses-per-revolution = <2>; - }; + #address-cells = <0x2>; + #size-cells = <0x1>; + + axi_fan_control: axi-fan-control@80000000 { + compatible = "adi,axi-fan-control-1.00.a"; + reg = <0x0 0x80000000 0x10000>; + clocks = <&clk 71>; + interrupts = <0 110 0>; + pulses-per-revolution = <2>; + }; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc2945.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc2945.yaml new file mode 100644 index 000000000000..5cb66e97e816 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc2945.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,ltc2945.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices LTC2945 wide range i2c power monitor + +maintainers: + - Guenter Roeck <linux@roeck-us.net> + +description: | + Analog Devices LTC2945 wide range i2c power monitor over I2C. + + https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2945.pdf + +properties: + compatible: + enum: + - adi,ltc2945 + + reg: + maxItems: 1 + + shunt-resistor-micro-ohms: + description: + Shunt resistor value in micro-Ohms + default: 1000 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + power-monitor@6e { + compatible = "adi,ltc2945"; + reg = <0x6e>; + /* 10 milli-Ohm shunt resistor */ + shunt-resistor-micro-ohms = <10000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml index bf04151b63d2..152935334c76 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml @@ -87,15 +87,15 @@ additionalProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - - ltc2947_spi: ltc2947@0 { - compatible = "adi,ltc2947"; - reg = <0>; - /* accumulation takes place always for energ1/charge1. */ - /* accumulation only on positive current for energy2/charge2. */ - adi,accumulator-ctl-pol = <0 1>; - }; + #address-cells = <1>; + #size-cells = <0>; + + ltc2947_spi: ltc2947@0 { + compatible = "adi,ltc2947"; + reg = <0>; + /* accumulation takes place always for energ1/charge1. */ + /* accumulation only on positive current for energy2/charge2. */ + adi,accumulator-ctl-pol = <0 1>; + }; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml index 64a8fcb7bc46..dba74f400bc2 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml @@ -55,26 +55,26 @@ additionalProperties: false examples: - | - i2c1 { + i2c { #address-cells = <1>; #size-cells = <0>; - ltc2992@6F { - #address-cells = <1>; - #size-cells = <0>; + ltc2992@6f { + #address-cells = <1>; + #size-cells = <0>; - compatible = "adi,ltc2992"; - reg = <0x6F>; + compatible = "adi,ltc2992"; + reg = <0x6f>; - channel@0 { - reg = <0x0>; - shunt-resistor-micro-ohms = <10000>; - }; + channel@0 { + reg = <0x0>; + shunt-resistor-micro-ohms = <10000>; + }; - channel@1 { - reg = <0x1>; - shunt-resistor-micro-ohms = <10000>; - }; + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <10000>; + }; }; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml index 7598b083979c..353d81d89bf5 100644 --- a/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml +++ b/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml @@ -41,13 +41,13 @@ additionalProperties: false examples: - | - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; sbrmi@3c { - compatible = "amd,sbrmi"; - reg = <0x3c>; + compatible = "amd,sbrmi"; + reg = <0x3c>; }; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml index 446b09f1ce94..75088244a274 100644 --- a/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml +++ b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml @@ -42,13 +42,13 @@ additionalProperties: false examples: - | - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; sbtsi@4c { - compatible = "amd,sbtsi"; - reg = <0x4c>; + compatible = "amd,sbtsi"; + reg = <0x4c>; }; }; ... diff --git a/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml b/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml new file mode 100644 index 000000000000..4a52aac6be72 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/hpe,gxp-fan-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE GXP Fan Controller + +maintainers: + - Nick Hawkins <nick.hawkins@hpe.com> + +description: | + The HPE GXP fan controller controls the fans through an external CPLD + device that connects to the fans. + +properties: + compatible: + const: hpe,gxp-fan-ctrl + + reg: + items: + - description: Fan controller PWM + - description: Programmable logic + - description: Function 2 + + reg-names: + items: + - const: base + - const: pl + - const: fn2 + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + fan-controller@1000c00 { + compatible = "hpe,gxp-fan-ctrl"; + reg = <0x1000c00 0x200>, <0xd1000000 0xff>, <0x80200000 0x100000>; + reg-names = "base", "pl", "fn2"; + }; diff --git a/Documentation/devicetree/bindings/hwmon/iio-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/iio-hwmon.yaml index e1ccbd30e0eb..c54b5986b365 100644 --- a/Documentation/devicetree/bindings/hwmon/iio-hwmon.yaml +++ b/Documentation/devicetree/bindings/hwmon/iio-hwmon.yaml @@ -31,7 +31,7 @@ additionalProperties: false examples: - | - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 1>, <&adc 2>; - }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 1>, <&adc 2>; + }; diff --git a/Documentation/devicetree/bindings/hwmon/national,lm90.yaml b/Documentation/devicetree/bindings/hwmon/national,lm90.yaml index e1719839faf0..7b9d48d6d6da 100644 --- a/Documentation/devicetree/bindings/hwmon/national,lm90.yaml +++ b/Documentation/devicetree/bindings/hwmon/national,lm90.yaml @@ -198,30 +198,30 @@ examples: }; - | i2c { - #address-cells = <1>; - #size-cells = <0>; - - sensor@4c { - compatible = "adi,adt7481"; - reg = <0x4c>; #address-cells = <1>; #size-cells = <0>; - channel@0 { - reg = <0x0>; - label = "local"; - }; - - channel@1 { - reg = <0x1>; - label = "front"; - temperature-offset-millicelsius = <4000>; - }; - - channel@2 { - reg = <0x2>; - label = "back"; - temperature-offset-millicelsius = <750>; + sensor@4c { + compatible = "adi,adt7481"; + reg = <0x4c>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + label = "local"; + }; + + channel@1 { + reg = <0x1>; + label = "front"; + temperature-offset-millicelsius = <4000>; + }; + + channel@2 { + reg = <0x2>; + label = "back"; + temperature-offset-millicelsius = <750>; + }; }; - }; }; diff --git a/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml b/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml index 6a1920712fb9..3d0146e20d3e 100644 --- a/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml +++ b/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml @@ -131,7 +131,7 @@ additionalProperties: false examples: - | - thermistor0 { + thermistor { compatible = "murata,ncp18wb473"; io-channels = <&gpadc 0x06>; pullup-uv = <1800000>; diff --git a/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml b/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml index 2f0620ecccc9..cd8dcd797031 100644 --- a/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml +++ b/Documentation/devicetree/bindings/hwmon/nuvoton,nct7802.yaml @@ -123,23 +123,23 @@ examples: #size-cells = <0>; channel@0 { /* LTD */ - reg = <0>; + reg = <0>; }; channel@1 { /* RTD1 */ - reg = <1>; - sensor-type = "voltage"; + reg = <1>; + sensor-type = "voltage"; }; channel@2 { /* RTD2 */ - reg = <2>; - sensor-type = "temperature"; - temperature-mode = "thermal-diode"; + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermal-diode"; }; channel@3 { /* RTD3 */ - reg = <3>; - sensor-type = "temperature"; + reg = <3>; + sensor-type = "temperature"; }; }; }; diff --git a/Documentation/devicetree/bindings/hwmon/nxp,mc34vr500.yaml b/Documentation/devicetree/bindings/hwmon/nxp,mc34vr500.yaml new file mode 100644 index 000000000000..306f67315835 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/nxp,mc34vr500.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/nxp,mc34vr500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP MC34VR500 hwmon sensor + +maintainers: + - Mario Kicherer <dev@kicherer.org> + +properties: + compatible: + enum: + - nxp,mc34vr500 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@8 { + compatible = "nxp,mc34vr500"; + reg = <0x08>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml index 1502b22c77cc..fde5225ce012 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml @@ -77,15 +77,15 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; - - tmp513@5c { - compatible = "ti,tmp513"; - reg = <0x5C>; - shunt-resistor-micro-ohms = <330000>; - ti,bus-range-microvolt = <32000000>; - ti,pga-gain = <8>; - ti,nfactor = <0x1 0xF3 0x00>; - }; + #address-cells = <1>; + #size-cells = <0>; + + tmp513@5c { + compatible = "ti,tmp513"; + reg = <0x5c>; + shunt-resistor-micro-ohms = <330000>; + ti,bus-range-microvolt = <32000000>; + ti,pga-gain = <8>; + ti,nfactor = <0x1 0xf3 0x00>; + }; }; diff --git a/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml b/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml index 3bc8e73dfbf0..bce68a326919 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml @@ -40,12 +40,12 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; - - tps23861@30 { - compatible = "ti,tps23861"; - reg = <0x30>; - shunt-resistor-micro-ohms = <255000>; - }; + #address-cells = <1>; + #size-cells = <0>; + + tps23861@30 { + compatible = "ti,tps23861"; + reg = <0x30>; + shunt-resistor-micro-ohms = <255000>; + }; }; diff --git a/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml new file mode 100644 index 000000000000..6604dcd47251 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/hpe,gxp-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE GXP SoC I2C Controller + +maintainers: + - Nick Hawkins <nick.hawkins@hpe.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: hpe,gxp-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + default: 100000 + + hpe,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the global status and enable interrupt registers shared + between each I2C engine controller instance. It enables the I2C + engine controller to act as both a master or slave by being able to + arm and respond to interrupts from its engine. Each bit in the + registers represent the respective bit position. + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2c@2600 { + compatible = "hpe,gxp-i2c"; + reg = <0x2500 0x70>; + interrupts = <9>; + #address-cells = <1>; + #size-cells = <0>; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <10000>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml b/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml index e0d76d5eb103..afd4925c2a7d 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml @@ -33,6 +33,10 @@ properties: open drain. maxItems: 1 + i2c-gpio,sda-output-only: + description: sda as output only + type: boolean + i2c-gpio,scl-output-only: description: scl as output only type: boolean @@ -63,6 +67,28 @@ properties: GPIO line used for SCL into open drain mode, and that something is not the GPIO chip. It is essentially an inconsistency flag. + i2c-gpio,sda-has-no-pullup: + type: boolean + description: sda is used in a non-compliant way and has no pull-up. + Therefore disable open-drain. This property is mutually-exclusive + with i2c-gpio,sda-open-drain. + + i2c-gpio,scl-has-no-pullup: + type: boolean + description: scl is used in a non-compliant way and has no pull-up. + Therefore disable open-drain. This property is mutually-exclusive + with i2c-gpio,scl-open-drain. + +dependencies: + i2c-gpio,sda-has-no-pullup: + not: + required: + - i2c-gpio,sda-open-drain + i2c-gpio,scl-has-no-pullup: + not: + required: + - i2c-gpio,scl-open-drain + required: - compatible - sda-gpios diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 421563bf576c..72ae2e01cf22 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -43,6 +43,10 @@ properties: - const: mediatek,mt6577-i2c - items: - enum: + - mediatek,mt8365-i2c + - const: mediatek,mt8168-i2c + - items: + - enum: - mediatek,mt8195-i2c - const: mediatek,mt8192-i2c diff --git a/Documentation/devicetree/bindings/i2c/i2c-st.txt b/Documentation/devicetree/bindings/i2c/i2c-st.txt deleted file mode 100644 index 4c26fda3844a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-st.txt +++ /dev/null @@ -1,41 +0,0 @@ -ST SSC binding, for I2C mode operation - -Required properties : -- compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c" -- reg : Offset and length of the register set for the device -- interrupts : the interrupt specifier -- clock-names: Must contain "ssc". -- clocks: Must contain an entry for each name in clock-names. See the common - clock bindings. -- A pinctrl state named "default" must be defined to set pins in mode of - operation for I2C transfer. - -Optional properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, - the default 100 kHz frequency will be used. As only Normal and Fast modes - are supported, possible values are 100000 and 400000. -- st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is - allowed through the deglitch circuit. In units of us. -- st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is - allowed through the deglitch circuit. In units of us. -- A pinctrl state named "idle" could be defined to set pins in idle state - when I2C instance is not performing a transfer. -- A pinctrl state named "sleep" could be defined to set pins in sleep state - when driver enters in suspend. - - - -Example : - -i2c0: i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt deleted file mode 100644 index 72f4a2f0fedc..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt +++ /dev/null @@ -1,29 +0,0 @@ -Socionext SynQuacer I2C - -Required properties: -- compatible : Must be "socionext,synquacer-i2c" -- reg : Offset and length of the register set for the device -- interrupts : A single interrupt specifier -- #address-cells : Must be <1>; -- #size-cells : Must be <0>; -- clock-names : Must contain "pclk". -- clocks : Must contain an entry for each name in clock-names. - (See the common clock bindings.) - -Optional properties: -- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and - Fast modes are supported, possible values are 100000 and - 400000. - -Example : - - i2c@51210000 { - compatible = "socionext,synquacer-i2c"; - reg = <0x51210000 0x1000>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "pclk"; - clocks = <&clk_i2c>; - clock-frequency = <400000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml new file mode 100644 index 000000000000..67882ec6e06a --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/loongson,ls2x-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS2X I2C Controller + +maintainers: + - Binbin Zhou <zhoubinbin@loongson.cn> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - loongson,ls2k-i2c + - loongson,ls7a-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c0: i2c@1fe21000 { + compatible = "loongson,ls2k-i2c"; + reg = <0x1fe21000 0x8>; + interrupt-parent = <&extioiic>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c16"; + reg = <0x57>; + pagesize = <16>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index cf9f8fda595f..ec79b7270437 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -12,14 +12,24 @@ maintainers: properties: compatible: - enum: - - qcom,msm8226-cci - - qcom,msm8916-cci - - qcom,msm8974-cci - - qcom,msm8996-cci - - qcom,sdm845-cci - - qcom,sm8250-cci - - qcom,sm8450-cci + oneOf: + - enum: + - qcom,msm8226-cci + - qcom,msm8974-cci + - qcom,msm8996-cci + + - items: + - enum: + - qcom,msm8916-cci + - const: qcom,msm8226-cci # CCI v1 + + - items: + - enum: + - qcom,sdm845-cci + - qcom,sm6350-cci + - qcom,sm8250-cci + - qcom,sm8450-cci + - const: qcom,msm8996-cci # CCI v2 "#address-cells": const: 1 @@ -88,10 +98,12 @@ allOf: - if: properties: compatible: - contains: - enum: - - qcom,msm8226-cci - - qcom,msm8974-cci + oneOf: + - contains: + enum: + - qcom,msm8974-cci + + - const: qcom,msm8226-cci then: properties: clocks: @@ -105,10 +117,12 @@ allOf: - if: properties: compatible: - contains: - enum: - - qcom,msm8916-cci - - qcom,msm8996-cci + oneOf: + - contains: + enum: + - qcom,msm8916-cci + + - const: qcom,msm8996-cci then: properties: clocks: @@ -126,6 +140,7 @@ allOf: contains: enum: - qcom,sdm845-cci + - qcom,sm6350-cci then: properties: clocks: @@ -169,7 +184,7 @@ examples: cci@ac4a000 { reg = <0x0ac4a000 0x4000>; - compatible = "qcom,sdm845-cci"; + compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index f5f7dc8f325c..0e88c85985b5 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -46,6 +46,8 @@ properties: interrupts: maxItems: 1 + operating-points-v2: true + pinctrl-0: true pinctrl-1: true diff --git a/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml index c46378efc123..92e899905ef8 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml @@ -16,7 +16,7 @@ properties: compatible: items: - enum: - - renesas,i2c-r9a09g011 # RZ/V2M + - renesas,r9a09g011-i2c # RZ/V2M - const: renesas,rzv2m-i2c reg: @@ -66,7 +66,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> i2c0: i2c@a4030000 { - compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; + compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; reg = <0xa4030000 0x80>; interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; diff --git a/Documentation/devicetree/bindings/i2c/socionext,synquacer-i2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,synquacer-i2c.yaml new file mode 100644 index 000000000000..f9d6e2038bb4 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/socionext,synquacer-i2c.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/socionext,synquacer-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext SynQuacer I2C Controller + +maintainers: + - Ard Biesheuvel <ardb@kernel.org> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: socionext,synquacer-i2c + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: pclk + + clock-frequency: + minimum: 100000 + maximum: 400000 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i2c@51210000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x51210000 0x1000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "pclk"; + clocks = <&clk_i2c>; + clock-frequency = <400000>; + }; +... diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml index c76131902b77..4bbe9e775da1 100644 --- a/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml @@ -29,6 +29,9 @@ properties: minimum: 100000 maximum: 400000 + resets: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml index ddde08636ab0..5abf496edb59 100644 --- a/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml @@ -29,6 +29,9 @@ properties: minimum: 100000 maximum: 400000 + resets: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml new file mode 100644 index 000000000000..08f9c1e446fd --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/st,sti-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C controller embedded in STMicroelectronics STi platform + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - st,comms-ssc-i2c + - st,comms-ssc4-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + clock-frequency: + enum: [ 100000, 400000 ] + default: 100000 + + st,i2c-min-scl-pulse-width-us: + description: + The minimum valid SCL pulse width that is allowed through the + deglitch circuit. In units of us. + + st,i2c-min-sda-pulse-width-us: + description: + The minimum valid SDA pulse width that is allowed through the + deglitch circuit. In units of us. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stih407-clks.h> + i2c@fed40000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed40000 0x110>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; diff --git a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml index 8d241a703d85..1b598638d457 100644 --- a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +++ b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: xlnx,xps-iic-2.00.a + enum: + - xlnx,axi-iic-2.1 + - xlnx,xps-iic-2.00.a reg: maxItems: 1 @@ -30,6 +32,13 @@ properties: description: | Input clock name. + clock-frequency: + description: + Optional I2C SCL clock frequency. If not specified, do not configure + in software, rely only on hardware design value. + default: 100000 + enum: [ 100000, 400000, 1000000 ] + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml index 7332442e5661..b6ba7ad1a8d5 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml @@ -41,7 +41,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml index f6f97164c2ca..5887021cc90f 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml @@ -39,7 +39,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml index 185b68ffb536..0c5b64cae965 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml @@ -59,7 +59,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index 346abfb13a3a..07cacc3f6a97 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -49,7 +49,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; @@ -64,7 +64,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml index 6b03c4efbb08..c07261c71013 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml @@ -58,34 +58,34 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interrupt-controller/irq.h> - i2c { - #address-cells = <1>; - #size-cells = <0>; + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; - /* Example for a I2C device node */ - accelerometer@1d { - compatible = "adi,adxl355"; - reg = <0x1d>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "DRDY"; - }; + /* Example for a I2C device node */ + accelerometer@1d { + compatible = "adi,adxl355"; + reg = <0x1d>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "DRDY"; }; + }; - | - #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interrupt-controller/irq.h> - spi { - #address-cells = <1>; - #size-cells = <0>; + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; - accelerometer@0 { - compatible = "adi,adxl355"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "DRDY"; - }; + accelerometer@0 { + compatible = "adi,adxl355"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "DRDY"; }; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml index 73a5c8f814cc..62465e36a590 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml @@ -37,32 +37,32 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { - #address-cells = <1>; - #size-cells = <0>; + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; - /* Example for a I2C device node */ - accelerometer@53 { - compatible = "adi,adxl372"; - reg = <0x53>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - }; + /* Example for a I2C device node */ + accelerometer@53 { + compatible = "adi,adxl372"; + reg = <0x53>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; }; + }; - | - #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interrupt-controller/irq.h> - spi0 { - #address-cells = <1>; - #size-cells = <0>; + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; - accelerometer@0 { - compatible = "adi,adxl372"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - }; + accelerometer@0 { + compatible = "adi,adxl372"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; }; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml index 5dd06f5905b4..ec643de031a3 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml @@ -36,7 +36,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml index 714e48e613de..6ddb03f61bd9 100644 --- a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml +++ b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml @@ -44,7 +44,7 @@ examples: accel@f { compatible = "kionix,kxtf9"; - reg = <0x0F>; + reg = <0xf>; mount-matrix = "0", "1", "0", "1", "0", "0", "0", "0", "1"; diff --git a/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml b/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml index 23528dcaa073..d530ec041fe7 100644 --- a/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml +++ b/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml @@ -1,9 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause - %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/accel/memsensing,msa311.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/accel/memsensing,msa311.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MEMSensing digital 3-Axis accelerometer diff --git a/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml b/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml index 65ce8ea14b52..783c7ddfcd90 100644 --- a/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml +++ b/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml @@ -50,7 +50,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; @@ -65,7 +65,7 @@ examples: }; - | #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml index b97559f23b3a..ce7ba634643c 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml @@ -44,11 +44,11 @@ examples: #size-cells = <0>; adc@2f { - compatible = "adi,ad7091r5"; - reg = <0x2f>; + compatible = "adi,ad7091r5"; + reg = <0x2f>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml index 75a7184a4735..35ed04350e28 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml @@ -61,7 +61,7 @@ required: patternProperties: "^channel@([0-9]|1[0-5])$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index cc347dade4ef..d521d516088b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -99,26 +99,26 @@ unevaluatedProperties: false examples: - | - spi0 { - #address-cells = <1>; - #size-cells = <0>; - - adc@0 { - compatible = "adi,ad7192"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - spi-cpha; - clocks = <&ad7192_mclk>; - clock-names = "mclk"; - interrupts = <25 0x2>; - interrupt-parent = <&gpio>; - dvdd-supply = <&dvdd>; - avdd-supply = <&avdd>; - - adi,refin2-pins-enable; - adi,rejection-60-Hz-enable; - adi,buffer-enable; - adi,burnout-currents-enable; + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7192"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + clocks = <&ad7192_mclk>; + clock-names = "mclk"; + interrupts = <25 0x2>; + interrupt-parent = <&gpio>; + dvdd-supply = <&dvdd>; + avdd-supply = <&avdd>; + + adi,refin2-pins-enable; + adi,rejection-60-Hz-enable; + adi,buffer-enable; + adi,burnout-currents-enable; }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml index 1bfbeed6f299..7cc4ddc4e9b7 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml @@ -43,7 +43,7 @@ required: patternProperties: "^channel@[0-7]$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index ac5a47c8f070..7fa46df1f4fb 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -112,30 +112,30 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; adc@0 { - compatible = "adi,ad7606-8"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - spi-cpha; - - avcc-supply = <&adc_vref>; - - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio>; - - adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; - adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>, - <&gpio 23 GPIO_ACTIVE_HIGH>, - <&gpio 26 GPIO_ACTIVE_HIGH>; - standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - adi,sw-mode; + compatible = "adi,ad7606-8"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + + avcc-supply = <&adc_vref>; + + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + + adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>, + <&gpio 23 GPIO_ACTIVE_HIGH>, + <&gpio 26 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + adi,sw-mode; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml index a67ba67dab51..5fcc8dd012f1 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml @@ -72,7 +72,7 @@ additionalProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml index 29641ce7175b..433ed2c9295f 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml @@ -57,17 +57,17 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - adc1: adc@28 { - reg = <0x28>; - compatible = "adi,ad7991"; - interrupts = <13 2>; - interrupt-parent = <&gpio6>; + adc1: adc@28 { + reg = <0x28>; + compatible = "adi,ad7991"; + interrupts = <13 2>; + interrupt-parent = <&gpio6>; - vcc-supply = <&vcc_3v3>; - vref-supply = <&adc_vref>; + vcc-supply = <&vcc_3v3>; + vref-supply = <&adc_vref>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml index 2d72ff6bcbc0..7aa748d6b7a0 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml @@ -64,10 +64,10 @@ examples: #size-cells = <0>; adc@0 { - compatible = "adi,ad9467"; - reg = <0>; - clocks = <&adc_clk>; - clock-names = "adc-clk"; + compatible = "adi,ad9467"; + reg = <0>; + clocks = <&adc_clk>; + clock-names = "adc-clk"; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index 8e25773d69be..9996dd93f84b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -51,11 +51,11 @@ additionalProperties: false examples: - | axi-adc@44a00000 { - compatible = "adi,axi-adc-10.0.a"; - reg = <0x44a00000 0x10000>; - dmas = <&rx_dma 0>; - dma-names = "rx"; + compatible = "adi,axi-adc-10.0.a"; + reg = <0x44a00000 0x10000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; - adi,adc-dev = <&spi_adc>; + adi,adc-dev = <&spi_adc>; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml index 31f840d59303..4817b840977a 100644 --- a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml @@ -41,7 +41,7 @@ properties: description: Startup time expressed in ms, it depends on SoC. atmel,trigger-edge-type: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: One of possible edge types for the ADTRG hardware trigger pin. When the specific edge type is detected, the conversion will diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml index 77605f17901c..9c57eb13f892 100644 --- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml +++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/avia-hx711.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/avia-hx711.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: AVIA HX711 ADC chip for weight cells diff --git a/Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml b/Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml new file mode 100644 index 000000000000..6d4fb3e1d2a2 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/cirrus,ep9301-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP930x internal ADC + +description: | + Cirrus Logic EP9301/EP9302 SoCs' internal ADC block. + + User's manual: + https://cdn.embeddedts.com/resource-attachments/ts-7000_ep9301-ug.pdf + +maintainers: + - Alexander Sverdlin <alexander.sverdlin@gmail.com> + +properties: + compatible: + const: cirrus,ep9301-adc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + adc: adc@80900000 { + compatible = "cirrus,ep9301-adc"; + reg = <0x80900000 0x28>; + clocks = <&syscon 24>; + interrupt-parent = <&vic1>; + interrupts = <30>; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml index 517e8b1fcb73..9cd0fd539782 100644 --- a/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml @@ -2,8 +2,8 @@ # Copyright 2019-2020 Artur Rojek %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Ingenic JZ47xx ADC controller IIO @@ -78,14 +78,14 @@ examples: #include <dt-bindings/iio/adc/ingenic,adc.h> adc@10070000 { - compatible = "ingenic,jz4740-adc"; - #io-channel-cells = <1>; + compatible = "ingenic,jz4740-adc"; + #io-channel-cells = <1>; - reg = <0x10070000 0x30>; + reg = <0x10070000 0x30>; - clocks = <&cgu JZ4740_CLK_ADC>; - clock-names = "adc"; + clocks = <&cgu JZ4740_CLK_ADC>; + clock-names = "adc"; - interrupt-parent = <&intc>; - interrupts = <18>; + interrupt-parent = <&intc>; + interrupts = <18>; }; diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml index d0a7ed26d9ea..e4b362113509 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml @@ -54,8 +54,8 @@ examples: - | #include <dt-bindings/interrupt-controller/irq.h> spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; maxadc: adc@0 { compatible = "maxim,max1027"; reg = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml index 50bcd72ac9d6..60d7b34e3286 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml @@ -10,7 +10,7 @@ maintainers: - Jonathan Cameron <jic23@kernel.org> description: | - Family of simple ADCs with i2c inteface and internal references. + Family of simple ADCs with i2c interface and internal references. properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml index 58b12fe8070c..ef8d51e74c08 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml @@ -54,8 +54,8 @@ examples: - | #include <dt-bindings/gpio/gpio.h> spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; adc@0 { compatible = "maxim,max1241"; diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml index e04f09f35601..96f3f535fe34 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml @@ -10,7 +10,7 @@ maintainers: - Jonathan Cameron <jic23@kernel.org> description: | - Family of ADCs with i2c inteface, internal references and threshold + Family of ADCs with i2c interface, internal references and threshold monitoring. properties: diff --git a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml index 2c93fb41f172..f7b3fde4115a 100644 --- a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml +++ b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Marcus Folkesson <marcus.folkesson@gmail.com> %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip MCP3911 Dual channel analog front end (ADC) diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml new file mode 100644 index 000000000000..dacc526dc695 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nxp,imx93-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP iMX93 ADC + +maintainers: + - Haibo Chen <haibo.chen@nxp.com> + +description: + The ADC on iMX93 is a 8-channel 12-bit 1MS/s ADC with 4 channels + connected to pins. it support normal and inject mode, include + One-Shot and Scan (continuous) conversions. Programmable DMA + enables for each channel Also this ADC contain alternate analog + watchdog thresholds, select threshold through input ports. And + also has Self-test logic and Software-initiated calibration. + +properties: + compatible: + const: nxp,imx93-adc + + reg: + maxItems: 1 + + interrupts: + items: + - description: WDGnL, watchdog threshold interrupt requests. + - description: WDGnH, watchdog threshold interrupt requests. + - description: normal conversion, include EOC (End of Conversion), + ECH (End of Chain), JEOC (End of Injected Conversion) and + JECH (End of injected Chain). + - description: Self-testing Interrupts. + + clocks: + maxItems: 1 + + clock-names: + const: ipg + + vref-supply: + description: + The reference voltage which used to establish channel scaling. + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - vref-supply + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx93-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + soc { + #address-cells = <1>; + #size-cells = <1>; + adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + vref-supply = <®_vref_1v8>; + #io-channel-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml index d186b713d6a7..58ea1ca4a5ee 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml @@ -160,7 +160,7 @@ examples: }; ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; - }; + }; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml index fa855baa368c..73def67fbe01 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml @@ -20,6 +20,7 @@ properties: compatible: items: - enum: + - qcom,pm8226-iadc - qcom,pm8941-iadc - const: qcom,spmi-iadc @@ -49,7 +50,7 @@ additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> - spmi_bus { + spmi { #address-cells = <1>; #size-cells = <0>; pmic_iadc: adc@3600 { diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml index c8cbfd3444be..b3a626389870 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -40,12 +40,12 @@ additionalProperties: false examples: - | pmic { - #address-cells = <1>; - #size-cells = <0>; - - pmic_rradc: adc@4500 { - compatible = "qcom,pmi8998-rradc"; - reg = <0x4500>; - #io-channel-cells = <1>; - }; + #address-cells = <1>; + #size-cells = <0>; + + pmic_rradc: adc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml index 8b743742a5f9..ba86c7b7d622 100644 --- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml @@ -69,7 +69,7 @@ required: patternProperties: "^channel@[0-7]$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml index 81c87295912c..582d0a03b814 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -52,7 +52,7 @@ properties: vdd-supply: true samsung,syscon-phandle: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (to access the ADC_PHY register on Exynos3250/4x12/5250/5420/5800). @@ -142,7 +142,7 @@ examples: pullup-ohm = <47000>; pulldown-ohm = <0>; io-channels = <&adc 4>; - }; + }; }; - | @@ -150,7 +150,7 @@ examples: adc@126c0000 { compatible = "samsung,exynos3250-adc"; - reg = <0x126C0000 0x100>; + reg = <0x126c0000 0x100>; interrupts = <0 137 0>; #io-channel-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index 1c340c95df16..995cbf8cefc6 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 ADC @@ -80,7 +80,7 @@ properties: description: Phandle to system configuration controller. It can be used to control the analog circuitry on stm32mp1. - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array interrupt-controller: true @@ -341,7 +341,7 @@ patternProperties: patternProperties: "^channel@([0-9]|1[0-9])$": type: object - $ref: "adc.yaml" + $ref: adc.yaml description: Represents the external channels which are connected to the ADC. properties: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml index 333744a2159c..474e35c49348 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml @@ -35,10 +35,8 @@ additionalProperties: false examples: - | - stmpe { - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */ - }; + adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0f>; /* dont use ADC CH3-0 */ }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml b/Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml new file mode 100644 index 000000000000..caaad777580c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,adc081c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Single-channel I2C ADCs + +maintainers: + - Jonathan Cameron <jic23@kernel.org> + - Lars-Peter Clausen <lars@metafoo.de> + +description: | + Single-channel ADC supporting 8, 10, or 12-bit samples and high/low alerts. + +properties: + compatible: + enum: + - ti,adc081c + - ti,adc101c + - ti,adc121c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vref-supply: + description: + Regulator for the combined power supply and voltage reference + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - vref-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@52 { + compatible = "ti,adc081c"; + reg = <0x52>; + vref-supply = <®_2p5v>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml index 2c3c2cf2145c..2127d639a768 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml @@ -104,12 +104,12 @@ examples: #address-cells = <1>; #size-cells = <0>; channel@0 { - reg = <0>; + reg = <0>; }; channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <5>; + reg = <4>; + ti,gain = <3>; + ti,datarate = <5>; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml index 55c2c73626f4..890f125d422c 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml @@ -77,7 +77,7 @@ required: patternProperties: "^channel@([0-7])$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml new file mode 100644 index 000000000000..0d8d06afed8b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads7924.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI ADS7924 4 channels 12 bits I2C analog to digital converter + +maintainers: + - Hugo Villeneuve <hvilleneuve@dimonoff.com> + +description: | + Texas Instruments ADS7924 4 channels 12 bits I2C analog to digital converter + + Specifications: + https://www.ti.com/lit/gpn/ads7924 + +properties: + compatible: + const: ti,ads7924 + + reg: + maxItems: 1 + + vref-supply: + description: + The regulator supply for the ADC reference voltage (AVDD) + + reset-gpios: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + +patternProperties: + "^channel@[0-3]+$": + $ref: adc.yaml + + description: | + Represents the external channels which are connected to the ADC. + + properties: + reg: + description: | + The channel number. It can have up to 4 channels numbered from 0 to 3. + items: + - minimum: 0 + maximum: 3 + + label: true + + required: + - reg + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - vref-supply + - "#address-cells" + - "#size-cells" + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@48 { + compatible = "ti,ads7924"; + reg = <0x48>; + vref-supply = <&ads7924_reg>; + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + label = "CH0"; + }; + channel@1 { + reg = <1>; + label = "CH1"; + }; + channel@2 { + reg = <2>; + label = "CH2"; + }; + channel@3 { + reg = <3>; + label = "CH3"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml b/Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml new file mode 100644 index 000000000000..5fb65bf7749d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,lmp92064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments LMP92064 Precision Current and Voltage Sensor. + +maintainers: + - Leonard Göhrs <l.goehrs@pengutronix.de> + +description: | + The LMP92064 is a two channel ADC intended for combined voltage and current + measurements. + + The device contains two ADCs to allow simultaneous sampling of voltage and + current and thus of instantaneous power consumption. + +properties: + compatible: + enum: + - ti,lmp92064 + + reg: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the main part of the chip + + vdig-supply: + description: | + Regulator that provides power to the digital I/O part of the chip + + shunt-resistor-micro-ohms: + description: | + Value of the shunt resistor (in µΩ) connected between INCP and INCN, + across which current is measured. Used to provide correct scaling of the + raw ADC measurement. + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - shunt-resistor-micro-ohms + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "ti,lmp92064"; + reg = <0>; + vdd-supply = <&vdd>; + vdig-supply = <&vdd>; + spi-max-frequency = <20000000>; + shunt-resistor-micro-ohms = <15000>; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml b/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml index bdf3bba2d750..866a05c9db36 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml @@ -41,7 +41,7 @@ required: patternProperties: "^channel@[0-7]$": - $ref: "adc.yaml" + $ref: adc.yaml type: object properties: @@ -83,36 +83,36 @@ examples: #size-cells = <0>; channel@0 { - reg = <0>; + reg = <0>; }; channel@1 { - reg = <1>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@2 { - reg = <2>; + reg = <2>; }; channel@3 { - reg = <3>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@4 { - reg = <4>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@5 { - reg = <5>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@6 { - reg = <6>; + reg = <6>; }; channel@7 { - reg = <7>; + reg = <7>; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index fee0f023a8c8..96340a05754c 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -192,26 +192,26 @@ additionalProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - ad3552r@0 { - compatible = "adi,ad3552r"; - reg = <0>; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - adi,output-range-microvolt = <0 10000000>; - }; - channel@1 { - reg = <1>; - custom-output-range-config { - adi,gain-offset = <5>; - adi,gain-scaling-p-inv-log2 = <1>; - adi,gain-scaling-n-inv-log2 = <2>; - adi,rfb-ohms = <1>; - }; + #address-cells = <1>; + #size-cells = <0>; + ad3552r@0 { + compatible = "adi,ad3552r"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + adi,output-range-microvolt = <0 10000000>; + }; + channel@1 { + reg = <1>; + custom-output-range-config { + adi,gain-offset = <5>; + adi,gain-scaling-p-inv-log2 = <1>; + adi,gain-scaling-n-inv-log2 = <2>; + adi,rfb-ohms = <1>; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml index ff50c72c62b5..9eb9928500e2 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml @@ -12,6 +12,7 @@ maintainers: description: | DAC devices supporting both SPI and I2C interfaces. + properties: compatible: enum: diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml index 13f214234b8e..b4400c52bec3 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml @@ -33,6 +33,7 @@ properties: - description: I2C devices enum: - adi,ad5311r + - adi,ad5337r - adi,ad5338r - adi,ad5671r - adi,ad5675r diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml index 3c8784a54d2c..212c936bab8d 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml @@ -51,15 +51,15 @@ additionalProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ad5766@0 { - compatible = "adi,ad5766"; - output-range-microvolts = <(-5000000) 5000000>; - reg = <0>; - spi-cpol; - spi-max-frequency = <1000000>; - reset-gpios = <&gpio 22 0>; - }; - }; + ad5766@0 { + compatible = "adi,ad5766"; + output-range-microvolts = <(-5000000) 5000000>; + reg = <0>; + spi-cpol; + spi-max-frequency = <1000000>; + reset-gpios = <&gpio 22 0>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml index 8e7da0de918f..82b0eed6a7b7 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml @@ -147,49 +147,49 @@ unevaluatedProperties: false examples: - | - spi { - #address-cells = <1>; - #size-cells = <0>; - - ad5770r@0 { - compatible = "adi,ad5770r"; - reg = <0>; - spi-max-frequency = <1000000>; - vref-supply = <&vref>; - adi,external-resistor; - reset-gpios = <&gpio 22 0>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0>; - adi,range-microamp = <0 300000>; - }; - - channel@1 { - reg = <1>; - adi,range-microamp = <0 140000>; - }; - - channel@2 { - reg = <2>; - adi,range-microamp = <0 55000>; - }; - - channel@3 { - reg = <3>; - adi,range-microamp = <0 45000>; - }; - - channel@4 { - reg = <4>; - adi,range-microamp = <0 45000>; - }; - - channel@5 { - reg = <5>; - adi,range-microamp = <0 45000>; - }; - }; + spi { + #address-cells = <1>; + #size-cells = <0>; + + ad5770r@0 { + compatible = "adi,ad5770r"; + reg = <0>; + spi-max-frequency = <1000000>; + vref-supply = <&vref>; + adi,external-resistor; + reset-gpios = <&gpio 22 0>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + adi,range-microamp = <0 300000>; + }; + + channel@1 { + reg = <1>; + adi,range-microamp = <0 140000>; + }; + + channel@2 { + reg = <2>; + adi,range-microamp = <0 55000>; + }; + + channel@3 { + reg = <3>; + adi,range-microamp = <0 45000>; + }; + + channel@4 { + reg = <4>; + adi,range-microamp = <0 45000>; + }; + + channel@5 { + reg = <5>; + adi,range-microamp = <0 45000>; + }; }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml index 15cc6bf59b13..f22ef710ecde 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml @@ -116,32 +116,32 @@ examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - ltc2688: ltc2688@0 { - compatible = "adi,ltc2688"; - reg = <0>; - - vcc-supply = <&vcc>; - iovcc-supply = <&vcc>; - vref-supply = <&vref>; - - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - adi,toggle-mode; - adi,overrange; - }; - - channel@1 { - reg = <1>; - adi,output-range-microvolt = <0 10000000>; - - clocks = <&clock_tgp3>; - adi,toggle-dither-input = <2>; - }; - }; + #address-cells = <1>; + #size-cells = <0>; + ltc2688: ltc2688@0 { + compatible = "adi,ltc2688"; + reg = <0>; + + vcc-supply = <&vcc>; + iovcc-supply = <&vcc>; + vref-supply = <&vref>; + + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + adi,toggle-mode; + adi,overrange; + }; + + channel@1 { + reg = <1>; + adi,output-range-microvolt = <0 10000000>; + + clocks = <&clock_tgp3>; + adi,toggle-dither-input = <2>; + }; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml index 133b0f867992..c9f51d00fa8f 100644 --- a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml +++ b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Marcus Folkesson <marcus.folkesson@gmail.com> %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc1660.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/dac/lltc,ltc1660.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Linear Technology Micropower octal 8-Bit and 10-Bit DACs diff --git a/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml b/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml index b1eb77335d05..733edc7d6d17 100644 --- a/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml +++ b/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Linear Technology LTC263x 12-/10-/8-Bit Rail-to-Rail DAC @@ -64,14 +64,14 @@ examples: }; spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dac@0 { - compatible = "lltc,ltc2632-l12"; - reg = <0>; /* CS0 */ - spi-max-frequency = <1000000>; - vref-supply = <&vref>; - }; + dac@0 { + compatible = "lltc,ltc2632-l12"; + reg = <0>; /* CS0 */ + spi-max-frequency = <1000000>; + vref-supply = <&vref>; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml b/Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml new file mode 100644 index 000000000000..24830f56c501 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/maxim,max5522.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX5522 Dual 10-bit Voltage-Output SPI DACs + +maintainers: + - Angelo Dureghello <angelo.dureghello@timesys.com> + - Jonathan Cameron <jic23@kernel.org> + +description: | + Datasheet available at: + https://www.analog.com/en/products/max5522.html + +properties: + compatible: + const: maxim,max5522 + + reg: + maxItems: 1 + + vdd-supply: true + vrefin-supply: true + +required: + - compatible + - reg + - vrefin-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "maxim,max5522"; + reg = <0>; + vrefin-supply = <&vref>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 0f1bf1110122..04045b932bd2 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DAC diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml index 88298bc43b81..79da0323c327 100644 --- a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml +++ b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml @@ -46,7 +46,7 @@ examples: dac@4c { compatible = "ti,dac5571"; - reg = <0x4C>; + reg = <0x4c>; vref-supply = <&vdd_supply>; }; }; diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml index 0144f74a4768..1cb2adaf66f9 100644 --- a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml +++ b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml @@ -53,16 +53,16 @@ unevaluatedProperties: false examples: - | - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; frequency@0 { - compatible = "adi,adf4371"; - reg = <0>; - spi-max-frequency = <1000000>; - clocks = <&adf4371_clkin>; - clock-names = "clkin"; + compatible = "adi,adf4371"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&adf4371_clkin>; + clock-names = "clkin"; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml b/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml index 0ae2464b9bc4..3d94dd4612c4 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml +++ b/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml @@ -50,13 +50,13 @@ examples: #address-cells = <1>; #size-cells = <0>; gyro@0 { - compatible = "adi,adxrs290"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpol; - spi-cpha; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; + compatible = "adi,adxrs290"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpol; + spi-cpha; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml b/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml index 2c900e9dddc6..297d519d68f2 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml +++ b/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml @@ -65,34 +65,34 @@ examples: - | #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; gyroscope@20 { - compatible = "nxp,fxas21002c"; - reg = <0x20>; + compatible = "nxp,fxas21002c"; + reg = <0x20>; - vdd-supply = <®_peri_3p15v>; - vddio-supply = <®_peri_3p15v>; + vdd-supply = <®_peri_3p15v>; + vddio-supply = <®_peri_3p15v>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT1"; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; }; }; - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; gyroscope@0 { - compatible = "nxp,fxas21002c"; - reg = <0x0>; + compatible = "nxp,fxas21002c"; + reg = <0x0>; - spi-max-frequency = <2000000>; + spi-max-frequency = <2000000>; - interrupt-parent = <&gpio2>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; }; }; diff --git a/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml b/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml index 6c5ad426a016..b9b5beac33b2 100644 --- a/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml +++ b/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml @@ -42,7 +42,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - heart_mon@0 { + heart-mon@0 { compatible = "ti,afe4403"; reg = <0>; spi-max-frequency = <10000000>; diff --git a/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml b/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml index c0e815d9999e..2958c4ca75b4 100644 --- a/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml +++ b/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml @@ -39,7 +39,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - heart_mon@58 { + heart-mon@58 { compatible = "ti,afe4404"; reg = <0x58>; tx-supply = <&vbat>; diff --git a/Documentation/devicetree/bindings/iio/humidity/dht11.yaml b/Documentation/devicetree/bindings/iio/humidity/dht11.yaml index 2247481d0203..0103f4238942 100644 --- a/Documentation/devicetree/bindings/iio/humidity/dht11.yaml +++ b/Documentation/devicetree/bindings/iio/humidity/dht11.yaml @@ -34,7 +34,7 @@ additionalProperties: false examples: - | - humidity_sensor { + humidity-sensor { compatible = "dht11"; gpios = <&gpio0 6 0>; }; diff --git a/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml b/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml index 88384b69f917..a2bc1fa92da0 100644 --- a/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml +++ b/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml @@ -35,12 +35,12 @@ additionalProperties: false examples: - | - i2c0 { - #address-cells = <1>; - #size-cells = <0>; - - humidity@40 { - compatible = "ti,hdc2010"; - reg = <0x40>; - }; + i2c { + #address-cells = <1>; + #size-cells = <0>; + + humidity@40 { + compatible = "ti,hdc2010"; + reg = <0x40>; + }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml index d166dbca18c3..4e43c80e5119 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml @@ -42,7 +42,7 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml index 5dbfae80bb28..c73533c54588 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml @@ -114,17 +114,17 @@ examples: - | #include <dt-bindings/interrupt-controller/irq.h> spi { - #address-cells = <1>; - #size-cells = <0>; - - adis16475: adis16475-3@0 { - compatible = "adi,adis16475-3"; - reg = <0>; - spi-cpha; - spi-cpol; - spi-max-frequency = <2000000>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio>; - }; + #address-cells = <1>; + #size-cells = <0>; + + adis16475: adis16475-3@0 { + compatible = "adi,adis16475-3"; + reg = <0>; + spi-cpha; + spi-cpol; + spi-max-frequency = <2000000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio>; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml index a0760382548d..47cfba939ca6 100644 --- a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml +++ b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml @@ -64,16 +64,16 @@ examples: #size-cells = <0>; bmi160@68 { - compatible = "bosch,bmi160"; - reg = <0x68>; - vdd-supply = <&pm8916_l17>; - vddio-supply = <&pm8916_l6>; - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT1"; - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "1"; + compatible = "bosch,bmi160"; + reg = <0x68>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; }; }; - | @@ -84,11 +84,11 @@ examples: #size-cells = <0>; bmi160@0 { - compatible = "bosch,bmi160"; - reg = <0>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; + compatible = "bosch,bmi160"; + reg = <0>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml index 13c9abdd3131..7cd05bcbee31 100644 --- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml @@ -65,35 +65,35 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; icm42605@68 { - compatible = "invensense,icm42605"; - reg = <0x68>; - interrupt-parent = <&gpio2>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&vdd>; - vddio-supply = <&vddio>; + compatible = "invensense,icm42605"; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; }; }; - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; icm42602@0 { - compatible = "invensense,icm42602"; - reg = <0>; - spi-max-frequency = <24000000>; - spi-cpha; - spi-cpol; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&vdd>; - vddio-supply = <&vddio>; + compatible = "invensense,icm42602"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-cpha; + spi-cpol; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml index 24416b59b782..688100b240bc 100644 --- a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml +++ b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml @@ -49,33 +49,33 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; + compatible = "nxp,fxos8700"; + reg = <0x1e>; - interrupt-parent = <&gpio2>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT1"; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; }; }; - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; fxos8700@0 { - compatible = "nxp,fxos8700"; - reg = <0>; + compatible = "nxp,fxos8700"; + reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml index 68b481c63318..decf022335d8 100644 --- a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml +++ b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml @@ -63,7 +63,7 @@ properties: description: if defined provides VDD IO power to the sensor. st,drdy-int-pin: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: | The pin on the package that will be used to signal data ready enum: diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml b/Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml new file mode 100644 index 000000000000..121d540b7b6e --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/ti,tmag5273.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor + +maintainers: + - Gerald Loacker <gerald.loacker@wolfvision.net> + +description: + The TI TMAG5273 is a low-power linear 3D Hall-effect sensor. This device + integrates three independent Hall-effect sensors in the X, Y, and Z axes. + The device has an integrated temperature sensor available. The TMAG5273 + can be configured through the I2C interface to enable any combination of + magnetic axes and temperature measurements. An integrated angle calculation + engine (CORDIC) provides full 360° angular position information for both + on-axis and off-axis angle measurement topologies. The angle calculation is + performed using two user-selected magnetic axes. + +properties: + compatible: + const: ti,tmag5273 + + reg: + maxItems: 1 + + "#io-channel-cells": + const: 1 + + ti,angle-measurement: + $ref: /schemas/types.yaml#/definitions/string + description: + Enables angle measurement in the selected plane. + If not specified, "x-y" will be anables as default. + enum: + - off + - x-y + - y-z + - x-z + + vcc-supply: + description: + A regulator providing 1.7 V to 3.6 V supply voltage on the VCC pin, + typically 3.3 V. + + interrupts: + description: + The low active interrupt can be configured to be fixed width or latched. + Interrupt events can be configured to be generated from magnetic + thresholds or when a conversion is completed. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@35 { + compatible = "ti,tmag5273"; + reg = <0x35>; + #io-channel-cells = <1>; + ti,angle-measurement = "x-z"; + vcc-supply = <&vcc3v3>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml b/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml index 9438fffaf0ba..877226e9219b 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml +++ b/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml @@ -91,12 +91,12 @@ examples: #size-cells = <0>; magnetometer@2e { - compatible = "yamaha,yas530"; - reg = <0x2e>; - vdd-supply = <&ldo1_reg>; - iovdd-supply = <&ldo2_reg>; - reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - interrupts = <13 IRQ_TYPE_EDGE_RISING>; + compatible = "yamaha,yas530"; + reg = <0x2e>; + vdd-supply = <&ldo1_reg>; + iovdd-supply = <&ldo2_reg>; + reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>; }; }; @@ -105,8 +105,8 @@ examples: #size-cells = <0>; magnetometer@2e { - compatible = "yamaha,yas539"; - reg = <0x2e>; - vdd-supply = <&ldo1_reg>; + compatible = "yamaha,yas539"; + reg = <0x2e>; + vdd-supply = <&ldo1_reg>; }; }; diff --git a/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml b/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml index 0ebb6725a1af..b8d7083c97f8 100644 --- a/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml +++ b/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml @@ -44,7 +44,7 @@ examples: potentiometer@2f { compatible = "adi,ad5272-020"; - reg = <0x2F>; + reg = <0x2f>; reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; }; }; diff --git a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml index 1f9fe15b4b3c..9fb8d773efa3 100644 --- a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml @@ -39,7 +39,7 @@ examples: - | #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml index 72cd2c2d3f17..63885af6a74b 100644 --- a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml @@ -60,16 +60,16 @@ examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c0 { - #address-cells = <1>; - #size-cells = <0>; - pressure@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - vddd-supply = <&foo>; - vdda-supply = <&bar>; - }; + i2c { + #address-cells = <1>; + #size-cells = <0>; + pressure@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + interrupt-parent = <&gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + vddd-supply = <&foo>; + vdda-supply = <&bar>; + }; }; diff --git a/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml b/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml index 710d3b9a86d9..c999994e19e3 100644 --- a/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml @@ -60,7 +60,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - lightning@0 { + lightning@0 { compatible = "ams,as3935"; reg = <0>; spi-max-frequency = <400000>; diff --git a/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml b/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml index 00e3b59641d2..d4e09d2dcd21 100644 --- a/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml index f088c5d2be99..ad0bb44f41b6 100644 --- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml @@ -36,7 +36,7 @@ properties: const: 1 semtech,resolution: - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32 enum: [8, 16, 32, 64, 128, 256, 512, 1024] description: Capacitance measurement resolution. For both phases, "reference" and diff --git a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml index 250439b13152..c6201976378f 100644 --- a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml +++ b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml @@ -39,6 +39,7 @@ properties: - st,lis3lv02dl-accel - st,lng2dm-accel - st,lsm303agr-accel + - st,lsm303c-accel - st,lsm303dl-accel - st,lsm303dlh-accel - st,lsm303dlhc-accel @@ -66,6 +67,7 @@ properties: - st,lis2mdl - st,lis3mdl-magn - st,lsm303agr-magn + - st,lsm303c-magn - st,lsm303dlh-magn - st,lsm303dlhc-magn - st,lsm303dlm-magn diff --git a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml index b69813f281da..f44fc32ce87e 100644 --- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml @@ -472,75 +472,74 @@ examples: #size-cells = <0>; temperature-sensor@0 { - compatible = "adi,ltc2983"; - reg = <0>; - - #address-cells = <1>; - #size-cells = <0>; - - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio>; - - thermocouple@18 { - reg = <18>; - adi,sensor-type = <8>; //Type B - adi,sensor-oc-current-microamp = <10>; - adi,cold-junction-handle = <&diode5>; - }; - - diode5: diode@5 { - reg = <5>; - adi,sensor-type = <28>; - }; - - rsense2: rsense@2 { - reg = <2>; - adi,sensor-type = <29>; - adi,rsense-val-milli-ohms = <1200000>; //1.2Kohms - }; - - rtd@14 { - reg = <14>; - adi,sensor-type = <15>; //PT1000 - /*2-wire, internal gnd, no current rotation*/ - adi,number-of-wires = <2>; - adi,rsense-share; - adi,excitation-current-microamp = <500>; - adi,rsense-handle = <&rsense2>; - }; - - adc@10 { - reg = <10>; - adi,sensor-type = <30>; - adi,single-ended; - }; - - thermistor@12 { - reg = <12>; - adi,sensor-type = <26>; //Steinhart - adi,rsense-handle = <&rsense2>; - adi,custom-steinhart = <0x00F371EC 0x12345678 - 0x2C0F8733 0x10018C66 0xA0FEACCD - 0x90021D99>; //6 entries - }; - - thermocouple@20 { - reg = <20>; - adi,sensor-type = <9>; //custom thermocouple - adi,single-ended; - adi,custom-thermocouple = - /bits/ 64 <(-50220000) 0>, - /bits/ 64 <(-30200000) 99100000>, - /bits/ 64 <(-5300000) 135400000>, - /bits/ 64 <0 273150000>, - /bits/ 64 <40200000 361200000>, - /bits/ 64 <55300000 522100000>, - /bits/ 64 <88300000 720300000>, - /bits/ 64 <132200000 811200000>, - /bits/ 64 <188700000 922500000>, - /bits/ 64 <460400000 1000000000>; //10 pairs - }; - + compatible = "adi,ltc2983"; + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio>; + + thermocouple@18 { + reg = <18>; + adi,sensor-type = <8>; //Type B + adi,sensor-oc-current-microamp = <10>; + adi,cold-junction-handle = <&diode5>; + }; + + diode5: diode@5 { + reg = <5>; + adi,sensor-type = <28>; + }; + + rsense2: rsense@2 { + reg = <2>; + adi,sensor-type = <29>; + adi,rsense-val-milli-ohms = <1200000>; //1.2Kohms + }; + + rtd@14 { + reg = <14>; + adi,sensor-type = <15>; //PT1000 + /*2-wire, internal gnd, no current rotation*/ + adi,number-of-wires = <2>; + adi,rsense-share; + adi,excitation-current-microamp = <500>; + adi,rsense-handle = <&rsense2>; + }; + + adc@10 { + reg = <10>; + adi,sensor-type = <30>; + adi,single-ended; + }; + + thermistor@12 { + reg = <12>; + adi,sensor-type = <26>; //Steinhart + adi,rsense-handle = <&rsense2>; + adi,custom-steinhart = <0x00f371ec 0x12345678 + 0x2c0f8733 0x10018c66 0xa0feaccd + 0x90021d99>; //6 entries + }; + + thermocouple@20 { + reg = <20>; + adi,sensor-type = <9>; //custom thermocouple + adi,single-ended; + adi,custom-thermocouple = + /bits/ 64 <(-50220000) 0>, + /bits/ 64 <(-30200000) 99100000>, + /bits/ 64 <(-5300000) 135400000>, + /bits/ 64 <0 273150000>, + /bits/ 64 <40200000 361200000>, + /bits/ 64 <55300000 522100000>, + /bits/ 64 <88300000 720300000>, + /bits/ 64 <132200000 811200000>, + /bits/ 64 <188700000 922500000>, + /bits/ 64 <460400000 1000000000>; //10 pairs + }; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml b/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml index a2823ed6867b..7cc365e0ebc8 100644 --- a/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml @@ -43,12 +43,12 @@ examples: #address-cells = <1>; #size-cells = <0>; - temp_sensor@0 { - compatible = "maxim,max31865"; - reg = <0>; - spi-max-frequency = <400000>; - spi-cpha; - maxim,3-wire; + temperature-sensor@0 { + compatible = "maxim,max31865"; + reg = <0>; + spi-max-frequency = <400000>; + spi-cpha; + maxim,3-wire; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml index 347bc16a4671..c4f1c69f9330 100644 --- a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# -title: "TI TMP117 - Digital temperature sensor with integrated NV memory" +title: TI TMP117 - Digital temperature sensor with integrated NV memory description: | TI TMP117 - Digital temperature sensor with integrated NV memory that supports diff --git a/Documentation/devicetree/bindings/input/goodix,gt7375p.yaml b/Documentation/devicetree/bindings/input/goodix,gt7375p.yaml index 1c191bc5a178..ce18d7dadae2 100644 --- a/Documentation/devicetree/bindings/input/goodix,gt7375p.yaml +++ b/Documentation/devicetree/bindings/input/goodix,gt7375p.yaml @@ -36,6 +36,13 @@ properties: vdd-supply: description: The 3.3V supply to the touchscreen. + mainboard-vddio-supply: + description: + The supply on the main board needed to power up IO signals going + to the touchscreen. This supply need not go to the touchscreen + itself as long as it allows the main board to make signals compatible + with what the touchscreen is expecting for its IO rails. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index 2f72ec418415..037c3ae9f1c3 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -26,6 +26,7 @@ properties: enum: - mediatek,mt6323-keys - mediatek,mt6331-keys + - mediatek,mt6357-keys - mediatek,mt6358-keys - mediatek,mt6397-keys diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 0c720dbde36e..12a0d3ecbabb 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -27,11 +27,13 @@ properties: - qcom,sc7280-cpu-bwmon - qcom,sc8280xp-cpu-bwmon - qcom,sdm845-bwmon + - qcom,sm8550-cpu-bwmon - const: qcom,msm8998-bwmon - const: qcom,msm8998-bwmon # BWMON v4 - items: - enum: - qcom,sc8280xp-llcc-bwmon + - qcom,sm8550-llcc-bwmon - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index aadae4424ba9..576992a6dc5a 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -22,6 +22,7 @@ properties: - qcom,sc7180-osm-l3 - qcom,sc8180x-osm-l3 - qcom,sdm845-osm-l3 + - qcom,sm6350-osm-l3 - qcom,sm8150-osm-l3 - const: qcom,osm-l3 - items: diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml new file mode 100644 index 000000000000..0070b0396e31 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000 + +maintainers: + - Georgi Djakov <djakov@kernel.org> + - Odelu Kukatla <quic_okukatla@quicinc.com> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + compatible: + enum: + - qcom,qdu1000-clk-virt + - qcom,qdu1000-gem-noc + - qcom,qdu1000-mc-virt + - qcom,qdu1000-system-noc + + '#interconnect-cells': true + + reg: + maxItems: 1 + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,qdu1000-clk-virt + - qcom,qdu1000-mc-virt + then: + properties: + reg: false + else: + required: + - reg + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> + + system_noc: interconnect@1640000 { + compatible = "qcom,qdu1000-system-noc"; + reg = <0x1640000 0x45080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,qdu1000-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 4b37aa88a375..d9d243c5514b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -62,6 +62,37 @@ properties: power-domains: maxItems: 1 +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + snoc-mm is a child of snoc, sharing snoc's register address space. + + properties: + compatible: + enum: + - qcom,msm8939-snoc-mm + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + + required: + - compatible + - '#interconnect-cells' + - clock-names + - clocks + required: - compatible - reg @@ -84,7 +115,6 @@ allOf: - qcom,msm8939-pcnoc - qcom,msm8939-snoc - qcom,msm8996-a1noc - - qcom,msm8996-a2noc - qcom,msm8996-bimc - qcom,msm8996-cnoc - qcom,msm8996-pnoc @@ -109,37 +139,6 @@ allOf: - description: Bus Clock - description: Bus A Clock - # Child node's properties - patternProperties: - '^interconnect-[a-z0-9]+$': - type: object - description: - snoc-mm is a child of snoc, sharing snoc's register address space. - - properties: - compatible: - enum: - - qcom,msm8939-snoc-mm - - '#interconnect-cells': - const: 1 - - clock-names: - items: - - const: bus - - const: bus_a - - clocks: - items: - - description: Bus Clock - - description: Bus A Clock - - required: - - compatible - - '#interconnect-cells' - - clock-names - - clocks - - if: properties: compatible: @@ -191,6 +190,29 @@ allOf: compatible: contains: enum: + - qcom,msm8996-a2noc + + then: + properties: + clock-names: + items: + - const: bus + - const: bus_a + - const: aggre2_ufs_axi + - const: ufs_axi + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + - description: Aggregate2 NoC UFS AXI Clock + - description: UFS AXI Clock + + - if: + properties: + compatible: + contains: + enum: - qcom,sdm660-a2noc then: @@ -215,6 +237,17 @@ allOf: - description: Aggregate2 USB3 AXI Clock. - description: Config NoC USB2 AXI Clock. + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,msm8939-snoc + then: + patternProperties: + '^interconnect-[a-z0-9]+$': false + examples: - | #include <dt-bindings/clock/qcom,rpmcc.h> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index a429a1ed1006..4d93ad415e0b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -39,18 +39,6 @@ properties: - qcom,sc7180-npu-noc - qcom,sc7180-qup-virt - qcom,sc7180-system-noc - - qcom,sc7280-aggre1-noc - - qcom,sc7280-aggre2-noc - - qcom,sc7280-clk-virt - - qcom,sc7280-cnoc2 - - qcom,sc7280-cnoc3 - - qcom,sc7280-dc-noc - - qcom,sc7280-gem-noc - - qcom,sc7280-lpass-ag-noc - - qcom,sc7280-mc-virt - - qcom,sc7280-mmss-noc - - qcom,sc7280-nsp-noc - - qcom,sc7280-system-noc - qcom,sc8180x-aggre1-noc - qcom,sc8180x-aggre2-noc - qcom,sc8180x-camnoc-virt @@ -58,23 +46,18 @@ properties: - qcom,sc8180x-config-noc - qcom,sc8180x-dc-noc - qcom,sc8180x-gem-noc - - qcom,sc8180x-ipa-virt - qcom,sc8180x-mc-virt - qcom,sc8180x-mmss-noc - qcom,sc8180x-qup-virt - qcom,sc8180x-system-noc - - qcom,sc8280xp-aggre1-noc - - qcom,sc8280xp-aggre2-noc - - qcom,sc8280xp-clk-virt - - qcom,sc8280xp-config-noc - - qcom,sc8280xp-dc-noc - - qcom,sc8280xp-gem-noc - - qcom,sc8280xp-lpass-ag-noc - - qcom,sc8280xp-mc-virt - - qcom,sc8280xp-mmss-noc - - qcom,sc8280xp-nspa-noc - - qcom,sc8280xp-nspb-noc - - qcom,sc8280xp-system-noc + - qcom,sdm670-aggre1-noc + - qcom,sdm670-aggre2-noc + - qcom,sdm670-config-noc + - qcom,sdm670-dc-noc + - qcom,sdm670-gladiator-noc + - qcom,sdm670-mem-noc + - qcom,sdm670-mmss-noc + - qcom,sdm670-system-noc - qcom,sdm845-aggre1-noc - qcom,sdm845-aggre2-noc - qcom,sdm845-config-noc @@ -96,7 +79,6 @@ properties: - qcom,sm8150-config-noc - qcom,sm8150-dc-noc - qcom,sm8150-gem-noc - - qcom,sm8150-ipa-virt - qcom,sm8150-mc-virt - qcom,sm8150-mmss-noc - qcom,sm8150-system-noc @@ -106,7 +88,6 @@ properties: - qcom,sm8250-config-noc - qcom,sm8250-dc-noc - qcom,sm8250-gem-noc - - qcom,sm8250-ipa-virt - qcom,sm8250-mc-virt - qcom,sm8250-mmss-noc - qcom,sm8250-npu-noc @@ -121,17 +102,6 @@ properties: - qcom,sm8350-mmss-noc - qcom,sm8350-compute-noc - qcom,sm8350-system-noc - - qcom,sm8450-aggre1-noc - - qcom,sm8450-aggre2-noc - - qcom,sm8450-clk-virt - - qcom,sm8450-config-noc - - qcom,sm8450-gem-noc - - qcom,sm8450-lpass-ag-noc - - qcom,sm8450-mc-virt - - qcom,sm8450-mmss-noc - - qcom,sm8450-nsp-noc - - qcom,sm8450-pcie-anoc - - qcom,sm8450-system-noc '#interconnect-cells': true diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml new file mode 100644 index 000000000000..2e0c0bc7a376 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sa8775p-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SA8775P + +maintainers: + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sa8775p.h + +properties: + compatible: + enum: + - qcom,sa8775p-aggre1-noc + - qcom,sa8775p-aggre2-noc + - qcom,sa8775p-clk-virt + - qcom,sa8775p-config-noc + - qcom,sa8775p-dc-noc + - qcom,sa8775p-gem-noc + - qcom,sa8775p-gpdsp-anoc + - qcom,sa8775p-lpass-ag-noc + - qcom,sa8775p-mc-virt + - qcom,sa8775p-mmss-noc + - qcom,sa8775p-nspa-noc + - qcom,sa8775p-nspb-noc + - qcom,sa8775p-pcie-anoc + - qcom,sa8775p-system-noc + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + +unevaluatedProperties: false + +examples: + - | + aggre1_noc: interconnect-aggre1-noc { + compatible = "qcom,sa8775p-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml new file mode 100644 index 000000000000..b135597d9489 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sc7280.h + +properties: + compatible: + enum: + - qcom,sc7280-aggre1-noc + - qcom,sc7280-aggre2-noc + - qcom,sc7280-clk-virt + - qcom,sc7280-cnoc2 + - qcom,sc7280-cnoc3 + - qcom,sc7280-dc-noc + - qcom,sc7280-gem-noc + - qcom,sc7280-lpass-ag-noc + - qcom,sc7280-mc-virt + - qcom,sc7280-mmss-noc + - qcom,sc7280-nsp-noc + - qcom,sc7280-system-noc + + reg: + maxItems: 1 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-clk-virt + then: + properties: + reg: false + else: + required: + - reg + +unevaluatedProperties: false + +examples: + - | + interconnect { + compatible = "qcom,sc7280-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@9100000 { + reg = <0x9100000 0xe2200>; + compatible = "qcom,sc7280-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml new file mode 100644 index 000000000000..6c2da03f0cd2 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-aggre1-noc + - qcom,sc8280xp-aggre2-noc + - qcom,sc8280xp-clk-virt + - qcom,sc8280xp-config-noc + - qcom,sc8280xp-dc-noc + - qcom,sc8280xp-gem-noc + - qcom,sc8280xp-lpass-ag-noc + - qcom,sc8280xp-mc-virt + - qcom,sc8280xp-mmss-noc + - qcom,sc8280xp-nspa-noc + - qcom,sc8280xp-nspb-noc + - qcom,sc8280xp-system-noc + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + +unevaluatedProperties: false + +examples: + - | + interconnect-0 { + compatible = "qcom,sc8280xp-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml new file mode 100644 index 000000000000..3cff7e662255 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sm8450.h + +properties: + compatible: + enum: + - qcom,sm8450-aggre1-noc + - qcom,sm8450-aggre2-noc + - qcom,sm8450-clk-virt + - qcom,sm8450-config-noc + - qcom,sm8450-gem-noc + - qcom,sm8450-lpass-ag-noc + - qcom,sm8450-mc-virt + - qcom,sm8450-mmss-noc + - qcom,sm8450-nsp-noc + - qcom,sm8450-pcie-anoc + - qcom,sm8450-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-clk-virt + - qcom,sm8450-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe 0 AXI clock + - description: aggre-NOC PCIe 1 AXI clock + - description: aggre UFS PHY AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-aggre1-noc + - qcom,sm8450-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + interconnect-0 { + compatible = "qcom,sm8450-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@1700000 { + compatible = "qcom,sm8450-aggre2-noc"; + reg = <0x01700000 0x31080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml new file mode 100644 index 000000000000..716bd21f6041 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550 + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + - Neil Armstrong <neil.armstrong@linaro.org> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h + +properties: + compatible: + enum: + - qcom,sm8550-aggre1-noc + - qcom,sm8550-aggre2-noc + - qcom,sm8550-clk-virt + - qcom,sm8550-cnoc-main + - qcom,sm8550-config-noc + - qcom,sm8550-gem-noc + - qcom,sm8550-lpass-ag-noc + - qcom,sm8550-lpass-lpiaon-noc + - qcom,sm8550-lpass-lpicx-noc + - qcom,sm8550-mc-virt + - qcom,sm8550-mmss-noc + - qcom,sm8550-nsp-noc + - qcom,sm8550-pcie-anoc + - qcom,sm8550-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-clk-virt + - qcom,sm8550-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-aggre1-noc + - qcom,sm8550-aggre2-noc + - qcom,sm8550-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + + clk_virt: interconnect-0 { + compatible = "qcom,sm8550-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8550-aggre1-noc"; + reg = <0x016e0000 0x14400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml b/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml index ad9ed596dfef..5e26e48c7217 100644 --- a/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml +++ b/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml @@ -196,6 +196,8 @@ properties: maxItems: 2 operating-points-v2: true + opp-table: + type: object samsung,data-clock-ratio: $ref: /schemas/types.yaml#/definitions/uint32 @@ -227,6 +229,31 @@ examples: operating-points-v2 = <&bus_dmc_opp_table>; devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; vdd-supply = <&buck1_reg>; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <800000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; }; ppmu_dmc0: ppmu@106a0000 { diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 9f7d3e11aacb..8449e14af9f3 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -108,7 +108,7 @@ properties: msi-controller: description: - Only present if the Message Based Interrupt functionnality is + Only present if the Message Based Interrupt functionality is being exposed by the HW, and the mbi-ranges property present. mbi-ranges: diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml index 46b2eb3c43ee..c680de1cbd56 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml @@ -109,7 +109,8 @@ properties: for system suspend/resume. brcm,int-fwd-mask: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 description: > if present, a bit mask to configure the interrupts which have a mux gate, typically UARTs. Setting these bits will make their respective interrupt diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt deleted file mode 100644 index a63ed9fcb535..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt +++ /dev/null @@ -1,24 +0,0 @@ -Loongson ls1x Interrupt Controller - -Required properties: - -- compatible : should be "loongson,ls1x-intc". Valid strings are: - -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. -- interrupts : Specifies the CPU interrupt the controller is connected to. - -Example: - -intc: interrupt-controller@1fd01040 { - compatible = "loongson,ls1x-intc"; - reg = <0x1fd01040 0x18>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&cpu_intc>; - interrupts = <2>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.yaml new file mode 100644 index 000000000000..c60125fb1cbf --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/loongson,ls1x-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 Interrupt Controller + +maintainers: + - Keguang Zhang <keguang.zhang@gmail.com> + +description: + Loongson-1 interrupt controller is connected to the MIPS core interrupt + controller, which controls several groups of interrupts. + +properties: + compatible: + const: loongson,ls1x-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + intc0: interrupt-controller@1fd01040 { + compatible = "loongson,ls1x-intc"; + reg = <0x1fd01040 0x18>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt deleted file mode 100644 index c54c5a9a2a90..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt +++ /dev/null @@ -1,53 +0,0 @@ -Samsung S3C24XX Interrupt Controllers - -The S3C24XX SoCs contain a custom set of interrupt controllers providing a -varying number of interrupt sources. The set consists of a main- and sub- -controller and on newer SoCs even a second main controller. - -Required properties: -- compatible: Compatible property value should be "samsung,s3c2410-irq" - for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. - -- reg: Physical base address of the controller and length of memory mapped - region. - -- interrupt-controller : Identifies the node as an interrupt controller - -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 4 and interrupt descriptor shall - have the following format: - <ctrl_num parent_irq ctrl_irq type> - - ctrl_num contains the controller to use: - - 0 ... main controller - - 1 ... sub controller - - 2 ... second main controller on s3c2416 and s3c2450 - parent_irq contains the parent bit in the main controller and will be - ignored in main controllers - ctrl_irq contains the interrupt bit of the controller - type contains the trigger type to use - -Example: - - interrupt-controller@4a000000 { - compatible = "samsung,s3c2410-irq"; - reg = <0x4a000000 0x100>; - interrupt-controller; - #interrupt-cells=<4>; - }; - - [...] - - serial@50000000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50000000 0x4000>; - interrupt-parent = <&subintc>; - interrupts = <1 28 0 4>, <1 28 1 4>; - }; - - rtc@57000000 { - compatible = "samsung,s3c2410-rtc"; - reg = <0x57000000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 30 0 3>, <0 8 0 3>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 99e01f4d0a69..63bc89e13480 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -45,7 +45,6 @@ description: from S-mode. So add thead,c900-plic to distinguish them. maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> - Palmer Dabbelt <palmer@dabbelt.com> diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt deleted file mode 100644 index dac0846fe789..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt +++ /dev/null @@ -1,31 +0,0 @@ -Socionext SynQuacer External Interrupt Unit (EXIU) - -The Socionext Synquacer SoC has an external interrupt unit (EXIU) -that forwards a block of 32 configurable input lines to 32 adjacent -level-high type GICv3 SPIs. - -Required properties: - -- compatible : Should be "socionext,synquacer-exiu". -- reg : Specifies base physical address and size of the - control registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. -- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent - ones the EXIU forwards its interrups to. - -Notes: - -- Only SPIs can use the EXIU as an interrupt parent. - -Example: - - exiu: interrupt-controller@510c0000 { - compatible = "socionext,synquacer-exiu"; - reg = <0x0 0x510c0000 0x0 0x20>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <3>; - socionext,spi-base = <112>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.yaml b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.yaml new file mode 100644 index 000000000000..92cec2255cca --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext SynQuacer External Interrupt Unit (EXIU) + +maintainers: + - Ard Biesheuvel <ardb@kernel.org> + +description: |+ + The Socionext SynQuacer SoC has an external interrupt unit (EXIU) + that forwards a block of 32 configurable input lines to 32 adjacent + level-high type GICv3 SPIs. + +properties: + compatible: + const: socionext,synquacer-exiu + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 3 + + interrupt-controller: true + + socionext,spi-base: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The SPI number of the first SPI of the 32 adjacent ones the + EXIU forwards its interrupts to. + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - socionext,spi-base + +unevaluatedProperties: false + +examples: + - | + interrupt-controller@510c0000 { + compatible = "socionext,synquacer-exiu"; + reg = <0x510c0000 0x20>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + socionext,spi-base = <112>; + }; +... diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 06af2bacbe97..903edf85d72e 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -24,6 +24,7 @@ properties: compatible: enum: - apple,t8103-dart + - apple,t8110-dart - apple,t6000-dart reg: diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index b28c5c2b0ff2..807cb511fe18 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -36,13 +36,17 @@ properties: - enum: - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 + - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 - qcom,sdm670-smmu-500 - qcom,sdm845-smmu-500 + - qcom,sdx55-smmu-500 + - qcom,sdx65-smmu-500 - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8150-smmu-500 @@ -52,14 +56,6 @@ properties: - const: qcom,smmu-500 - const: arm,mmu-500 - - description: Qcom SoCs implementing "arm,mmu-500" (non-qcom implementation) - deprecated: true - items: - - enum: - - qcom,sdx55-smmu-500 - - qcom,sdx65-smmu-500 - - const: arm,mmu-500 - - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) deprecated: true items: @@ -84,6 +80,7 @@ properties: items: - enum: - qcom,sc7280-smmu-500 + - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: qcom,adreno-smmu - const: arm,mmu-500 @@ -201,7 +198,8 @@ properties: maxItems: 7 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 nvidia,memory-controller: description: | @@ -366,6 +364,56 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + # Disallow clocks for all other platforms with specific compatibles + - if: + properties: + compatible: + contains: + enum: + - cavium,smmu-v2 + - marvell,ap806-smmu-500 + - nvidia,smmu-500 + - qcom,qcm2290-smmu-500 + - qcom,qdu1000-smmu-500 + - qcom,sa8775p-smmu-500 + - qcom,sc7180-smmu-500 + - qcom,sc8180x-smmu-500 + - qcom,sc8280xp-smmu-500 + - qcom,sdm670-smmu-500 + - qcom,sdm845-smmu-500 + - qcom,sdx55-smmu-500 + - qcom,sdx65-smmu-500 + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 + - qcom,sm6350-smmu-500 + - qcom,sm6375-smmu-500 + - qcom,sm8350-smmu-500 + - qcom,sm8450-smmu-500 + then: + properties: + clock-names: false + clocks: false + + - if: + properties: + compatible: + contains: + const: qcom,sm6375-smmu-500 + then: + properties: + power-domains: + items: + - description: SNoC MMU TBU RT GDSC + - description: SNoC MMU TBU NRT GDSC + - description: SNoC TURING MMU TBU0 GDSC + + required: + - power-domains + else: + properties: + power-domains: + maxItems: 1 + examples: - |+ /* SMMU with stream matching or stream indexing */ diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt index 059139abce35..e6cecfd360eb 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -10,6 +10,7 @@ to non-secure vs secure interrupt line. - compatible : Should be one of: "qcom,msm8916-iommu" + "qcom,msm8953-iommu" Followed by "qcom,msm-iommu-v1". diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml index 26d0a5121f02..72308a4c14e7 100644 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml @@ -49,6 +49,7 @@ properties: - enum: - renesas,ipmmu-r8a779a0 # R-Car V3U - renesas,ipmmu-r8a779f0 # R-Car S4-8 + - renesas,ipmmu-r8a779g0 # R-Car V4H - const: renesas,rcar-gen4-ipmmu-vmsa # R-Car Gen4 reg: diff --git a/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml b/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml new file mode 100644 index 000000000000..e1191453c2f0 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/kinetic,ktz8866.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/kinetic,ktz8866.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kinetic Technologies KTZ8866 backlight + +maintainers: + - Jianhua Lu <lujianhua000@gmail.com> + +description: | + The Kinetic Technologies KTZ8866 is a high efficiency 6-channels-current-sinks + led backlight with dual lcd bias power. + https://www.kinet-ic.com/ktz8866/ + +allOf: + - $ref: common.yaml# + +properties: + compatible: + const: kinetic,ktz8866 + + vddpos-supply: + description: positive boost supply regulator. + + vddneg-supply: + description: negative boost supply regulator. + + enable-gpios: + description: GPIO to use to enable/disable the backlight (HWEN pin). + maxItems: 1 + + current-num-sinks: + description: number of the LED current sinks' channels. + enum: [1, 2, 3, 4, 5, 6] + + kinetic,current-ramp-delay-ms: + description: | + LED current ramping delay time in milliseconds, note that the + case 1 will be mapped to 1μs. + enum: [1, 2, 4, 8, 16, 32, 64, 128, 192, 256, 320, 384, 448, 512, 576, 640] + + kinetic,led-enable-ramp-delay-ms: + description: | + LED on/off ramping delay time in milliseconds, note that the case 0 will be + mapped to 512μs because ktz8866 can't ramp faster than it. + enum: [0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384] + + kinetic,enable-lcd-bias: + description: Set if we want to output bias power supply for LCD. + type: boolean + +required: + - compatible + - vddpos-supply + - vddneg-supply + - enable-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + backlight { + compatible = "kinetic,ktz8866"; + + vddpos-supply = <&bl_vddpos_5p5>; + vddneg-supply = <&bl_vddneg_5p5>; + enable-gpios = <&tlmm 139 GPIO_ACTIVE_HIGH>; + current-num-sinks = <5>; + kinetic,current-ramp-delay-ms = <128>; + kinetic,led-enable-ramp-delay-ms = <1>; + kinetic,enable-lcd-bias; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml b/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml index 9acdb7895514..5f1849bdabba 100644 --- a/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml +++ b/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - qcom,pm8941-wled + - qcom,pmi8950-wled - qcom,pmi8994-wled - qcom,pmi8998-wled - qcom,pm660l-wled diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index f5c57a580078..15e3f6645682 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -90,17 +90,22 @@ properties: - heartbeat # LED indicates disk activity - disk-activity - # LED indicates IDE disk activity (deprecated), in new implementations - # use "disk-activity" - - ide-disk + - disk-read + - disk-write # LED flashes at a fixed, configurable rate - timer # LED alters the brightness for the specified duration with one software # timer (requires "led-pattern" property) - pattern - # LED is triggered by SD/MMC activity - - pattern: "^mmc[0-9]+$" + - usb-gadget + - usb-host - pattern: "^cpu[0-9]*$" + - pattern: "^hci[0-9]+-power$" + # LED is triggered by Bluetooth activity + - pattern: "^mmc[0-9]+$" + # LED is triggered by SD/MMC activity + - pattern: "^phy[0-9]+tx$" + # LED is triggered by WLAN activity led-pattern: description: | diff --git a/Documentation/devicetree/bindings/leds/leds-mt6323.txt b/Documentation/devicetree/bindings/leds/leds-mt6323.txt index 45bf9f7d85f3..73353692efa1 100644 --- a/Documentation/devicetree/bindings/leds/leds-mt6323.txt +++ b/Documentation/devicetree/bindings/leds/leds-mt6323.txt @@ -9,7 +9,7 @@ MT6323 PMIC hardware. For MT6323 MFD bindings see: Documentation/devicetree/bindings/mfd/mt6397.txt For MediaTek PMIC wrapper bindings see: -Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml Required properties: - compatible : Must be "mediatek,mt6323-led" diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 943f9472ae10..d888ead09282 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -18,9 +18,12 @@ properties: oneOf: - items: - enum: + - qcom,ipq5332-apcs-apps-global + - const: qcom,ipq6018-apcs-apps-global + - items: + - enum: - qcom,ipq6018-apcs-apps-global - qcom,ipq8074-apcs-apps-global - - qcom,msm8976-apcs-kpss-global - qcom,msm8996-apcs-hmss-global - qcom,msm8998-apcs-hmss-global - qcom,qcm2290-apcs-hmss-global @@ -37,8 +40,10 @@ properties: - qcom,msm8916-apcs-kpss-global - qcom,msm8939-apcs-kpss-global - qcom,msm8953-apcs-kpss-global + - qcom,msm8976-apcs-kpss-global - qcom,msm8994-apcs-kpss-global - qcom,qcs404-apcs-apps-global + - qcom,sdx55-apcs-gcc - const: syscon reg: maxItems: 1 @@ -71,15 +76,8 @@ allOf: compatible: enum: - qcom,msm8916-apcs-kpss-global - - qcom,msm8994-apcs-kpss-global - - qcom,msm8996-apcs-hmss-global - - qcom,msm8998-apcs-hmss-global + - qcom,msm8939-apcs-kpss-global - qcom,qcs404-apcs-apps-global - - qcom,sc7180-apss-shared - - qcom,sdm660-apcs-hmss-global - - qcom,sdm845-apss-shared - - qcom,sm6125-apcs-hmss-global - - qcom,sm8150-apss-shared then: properties: clocks: @@ -110,9 +108,10 @@ allOf: - if: properties: compatible: - enum: - - qcom,ipq6018-apcs-apps-global - - qcom,ipq8074-apcs-apps-global + contains: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global then: properties: clocks: @@ -123,12 +122,37 @@ allOf: items: - const: pll - const: xo + - if: properties: compatible: enum: - - qcom,ipq6018-apcs-apps-global - - qcom,ipq8074-apcs-apps-global + - qcom,msm8953-apcs-kpss-global + - qcom,msm8976-apcs-kpss-global + - qcom,msm8994-apcs-kpss-global + - qcom,msm8996-apcs-hmss-global + - qcom,msm8998-apcs-hmss-global + - qcom,qcm2290-apcs-hmss-global + - qcom,sc7180-apss-shared + - qcom,sc8180x-apss-shared + - qcom,sdm660-apcs-hmss-global + - qcom,sdm845-apss-shared + - qcom,sm4250-apcs-hmss-global + - qcom,sm6115-apcs-hmss-global + - qcom,sm6125-apcs-hmss-global + - qcom,sm8150-apss-shared + then: + properties: + clocks: false + clock-names: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global then: properties: '#clock-cells': @@ -148,6 +172,7 @@ examples: reg = <0x9820000 0x1000>; #mbox-cells = <1>; + #clock-cells = <0>; }; rpm-glink { @@ -155,7 +180,6 @@ examples: interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; - mbox-names = "rpm_hlos"; }; # Example apcs with qcs404 diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index f5c73437fef4..cc6f66eccc84 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,8 @@ properties: compatible: items: - enum: + - qcom,qdu1000-ipcc + - qcom,sa8775p-ipcc - qcom,sc7280-ipcc - qcom,sc8280xp-ipcc - qcom,sm6350-ipcc diff --git a/Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml new file mode 100644 index 000000000000..a023c28dff49 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/st,sti-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics Mailbox Driver for STi platform + +description: + Each ST Mailbox IP currently consists of 4 instances of 32 channels. + Messages are passed between Application and Remote processors using + shared memory. + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +properties: + compatible: + const: st,stih407-mailbox + + reg: + maxItems: 1 + + mbox-name: + $ref: /schemas/types.yaml#/definitions/string + description: name of the mailbox IP + + interrupts: + description: the irq line for the RX mailbox + maxItems: 1 + + "#mbox-cells": + const: 2 + +required: + - compatible + - reg + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + mailbox0: mailbox@8f00000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f00000 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + mbox-name = "a9"; + }; + +... diff --git a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt deleted file mode 100644 index 351f612673fc..000000000000 --- a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt +++ /dev/null @@ -1,51 +0,0 @@ -ST Microelectronics Mailbox Driver - -Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages -are passed between Application and Remote processors using shared memory. - -Controller ----------- - -Required properties: -- compatible : Should be "st,stih407-mailbox" -- reg : Offset and length of the device's register set -- mbox-name : Name of the mailbox -- #mbox-cells: : Must be 2 - <&phandle instance channel direction> - phandle : Label name of controller - instance : Instance number - channel : Channel number - -Optional properties -- interrupts : Contains the IRQ line for a Rx mailbox - -Example: - -mailbox0: mailbox@0 { - compatible = "st,stih407-mailbox"; - reg = <0x08f00000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>; - #mbox-cells = <2>; - mbox-name = "a9"; -}; - -Client ------- - -Required properties: -- compatible : Many (See the client docs) -- reg : Shared (between Application and Remote) memory address -- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) - Cells must match 'mbox-cells' (See Controller docs above) - -Optional properties -- mbox-names : Name given to channels seen in the 'mboxes' property. - -Example: - -mailbox_test { - compatible = "mailbox-test"; - reg = <0x[shared_memory_address], [shared_memory_size]>; - mboxes = <&mailbox2 0 1>, <&mailbox0 2 1>; - mbox-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/media/cec-gpio.txt b/Documentation/devicetree/bindings/media/cec-gpio.txt deleted file mode 100644 index 47e8d73d32a3..000000000000 --- a/Documentation/devicetree/bindings/media/cec-gpio.txt +++ /dev/null @@ -1,42 +0,0 @@ -* HDMI CEC GPIO driver - -The HDMI CEC GPIO module supports CEC implementations where the CEC line -is hooked up to a pull-up GPIO line and - optionally - the HPD line is -hooked up to another GPIO line. - -Please note: the maximum voltage for the CEC line is 3.63V, for the HPD and -5V lines it is 5.3V. So you may need some sort of level conversion circuitry -when connecting them to a GPIO line. - -Required properties: - - compatible: value must be "cec-gpio". - - cec-gpios: gpio that the CEC line is connected to. The line should be - tagged as open drain. - -If the CEC line is associated with an HDMI receiver/transmitter, then the -following property is also required: - - - hdmi-phandle - phandle to the HDMI controller, see also cec.txt. - -If the CEC line is not associated with an HDMI receiver/transmitter, then -the following property is optional and can be used for debugging HPD changes: - - - hpd-gpios: gpio that the HPD line is connected to. - -This property is optional and can be used for debugging changes on the 5V line: - - - v5-gpios: gpio that the 5V line is connected to. - -Example for the Raspberry Pi 3 where the CEC line is connected to -pin 26 aka BCM7 aka CE1 on the GPIO pin header, the HPD line is -connected to pin 11 aka BCM17 and the 5V line is connected to pin -15 aka BCM22 (some level shifter is needed for the HPD and 5V lines!): - -#include <dt-bindings/gpio/gpio.h> - -cec-gpio { - compatible = "cec-gpio"; - cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - v5-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/media/cec.txt b/Documentation/devicetree/bindings/media/cec.txt deleted file mode 100644 index 22d7aae3d3d7..000000000000 --- a/Documentation/devicetree/bindings/media/cec.txt +++ /dev/null @@ -1,8 +0,0 @@ -Common bindings for HDMI CEC adapters - -- hdmi-phandle: phandle to the HDMI controller. - -- needs-hpd: if present the CEC support is only available when the HPD - is high. Some boards only let the CEC pin through if the HPD is high, - for example if there is a level converter that uses the HPD to power - up or down. diff --git a/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml b/Documentation/devicetree/bindings/media/cec/amlogic,meson-gx-ao-cec.yaml index 8d844f4312d1..b1fab53418f9 100644 --- a/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/amlogic,meson-gx-ao-cec.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/media/amlogic,meson-gx-ao-cec.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/media/cec/amlogic,meson-gx-ao-cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson AO-CEC Controller @@ -33,11 +33,8 @@ properties: interrupts: maxItems: 1 - hdmi-phandle: - description: phandle to the HDMI controller - $ref: /schemas/types.yaml#/definitions/phandle - allOf: + - $ref: cec-common.yaml# - if: properties: compatible: @@ -81,7 +78,7 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/media/cec/cec-common.yaml b/Documentation/devicetree/bindings/media/cec/cec-common.yaml new file mode 100644 index 000000000000..af6ee5f1c73f --- /dev/null +++ b/Documentation/devicetree/bindings/media/cec/cec-common.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cec/cec-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HDMI CEC Adapters Common Properties + +maintainers: + - Hans Verkuil <hverkuil@xs4all.nl> + +properties: + $nodename: + pattern: "^cec(@[0-9a-f]+|-[0-9]+)?$" + + hdmi-phandle: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the HDMI controller. + + needs-hpd: + type: boolean + description: + The CEC support is only available when the HPD is high. Some boards only + let the CEC pin through if the HPD is high, for example if there is a + level converter that uses the HPD to power up or down. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml new file mode 100644 index 000000000000..64d7ec057672 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cec/cec-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HDMI CEC GPIO + +maintainers: + - Hans Verkuil <hverkuil-cisco@xs4all.nl> + +description: | + The HDMI CEC GPIO module supports CEC implementations where the CEC line is + hooked up to a pull-up GPIO line and - optionally - the HPD line is hooked up + to another GPIO line. + + Please note:: the maximum voltage for the CEC line is 3.63V, for the HPD and + 5V lines it is 5.3V. So you may need some sort of level conversion + circuitry when connecting them to a GPIO line. + +properties: + compatible: + const: cec-gpio + + cec-gpios: + maxItems: 1 + description: + GPIO that the CEC line is connected to. The line should be tagged as open + drain. + + hpd-gpios: + maxItems: 1 + description: + GPIO that the HPD line is connected to. Used for debugging HPD changes + when the CEC line is not associated with an HDMI receiver/transmitter. + + v5-gpios: + maxItems: 1 + description: + GPIO that the 5V line is connected to. Used for debugging changes on the + 5V line. + +required: + - compatible + - cec-gpios + +allOf: + - $ref: cec-common.yaml# + - if: + required: + - hdmi-phandle + then: + properties: + hpd-gpios: false + + - if: + required: + - hpd-gpios + then: + properties: + hdmi-phandle: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + cec { + compatible = "cec-gpio"; + cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + v5-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml new file mode 100644 index 000000000000..369c48fd9bf9 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cec/nvidia,tegra114-cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra HDMI CEC + +maintainers: + - Hans Verkuil <hverkuil-cisco@xs4all.nl> + +allOf: + - $ref: cec-common.yaml# + +properties: + compatible: + enum: + - nvidia,tegra114-cec + - nvidia,tegra124-cec + - nvidia,tegra210-cec + + clocks: + maxItems: 1 + + clock-names: + items: + - const: cec + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - hdmi-phandle + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra124-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x70015000 0x00001000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + hdmi-phandle = <&hdmi>; + }; diff --git a/Documentation/devicetree/bindings/media/cec/samsung,s5p-cec.yaml b/Documentation/devicetree/bindings/media/cec/samsung,s5p-cec.yaml new file mode 100644 index 000000000000..016c8a77c1a6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cec/samsung,s5p-cec.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cec/samsung,s5p-cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5PV210 and Exynos HDMI CEC + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Marek Szyprowski <m.szyprowski@samsung.com> + +allOf: + - $ref: cec-common.yaml# + +properties: + compatible: + const: samsung,s5p-cec + + clocks: + maxItems: 1 + + clock-names: + items: + - const: hdmicec + + interrupts: + maxItems: 1 + + samsung,syscon-phandle: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU system controller interface + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - hdmi-phandle + - interrupts + - samsung,syscon-phandle + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5420.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + cec@101b0000 { + compatible = "samsung,s5p-cec"; + reg = <0x101B0000 0x200>; + + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + hdmi-phandle = <&hdmi>; + needs-hpd; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + samsung,syscon-phandle = <&pmu_system_controller>; + }; diff --git a/Documentation/devicetree/bindings/media/cec/st,stih-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stih-cec.yaml new file mode 100644 index 000000000000..aeddf16ed339 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cec/st,stih-cec.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cec/st,stih-cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STIH4xx HDMI CEC + +maintainers: + - Alain Volmat <alain.volmat@foss.st.com> + +allOf: + - $ref: cec-common.yaml# + +properties: + compatible: + const: st,stih-cec + + clocks: + maxItems: 1 + + clock-names: + items: + - const: cec-clk + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: cec-irq + + resets: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - hdmi-phandle + - interrupts + - resets + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/stih407-resets.h> + + cec@94a087c { + compatible = "st,stih-cec"; + reg = <0x94a087c 0x64>; + + clocks = <&clk_sysin>; + clock-names = "cec-clk"; + hdmi-phandle = <&sti_hdmi>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cec-irq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cec0_default>; + resets = <&softreset STIH407_LPM_SOFTRESET>; + }; diff --git a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml new file mode 100644 index 000000000000..2314a9a14650 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cec/st,stm32-cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 CEC + +maintainers: + - Yannick Fertre <yannick.fertre@foss.st.com> + +properties: + compatible: + const: st,stm32-cec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Module Clock + - description: Bus Clock + + clock-names: + items: + - const: cec + - const: hdmi-cec + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006c00 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CEC_K>, <&clk_lse>; + clock-names = "cec", "hdmi-cec"; + }; + +... diff --git a/Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml b/Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml new file mode 100644 index 000000000000..84a5e894ace4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Pixel Pipeline + +maintainers: + - Philipp Zabel <p.zabel@pengutronix.de> + - Michael Tretter <m.tretter@pengutronix.de> + +description: + The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine + that supports scaling, colorspace conversion, alpha blending, rotation, and + pixel conversion via lookup table. Different versions are present on various + i.MX SoCs from i.MX23 to i.MX7. + +properties: + compatible: + oneOf: + - enum: + - fsl,imx6ul-pxp + - fsl,imx6ull-pxp + - fsl,imx7d-pxp + - items: + - enum: + - fsl,imx6sll-pxp + - fsl,imx6sx-pxp + - const: fsl,imx6ull-pxp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + const: axi + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pxp + - fsl,imx6ul-pxp + then: + properties: + interrupts: + maxItems: 1 + else: + properties: + interrupts: + minItems: 2 + maxItems: 2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6ul-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pxp: pxp@21cc000 { + compatible = "fsl,imx6ull-pxp"; + reg = <0x021cc000 0x4000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "axi"; + clocks = <&clks IMX6UL_CLK_PXP>; + }; diff --git a/Documentation/devicetree/bindings/media/fsl-pxp.txt b/Documentation/devicetree/bindings/media/fsl-pxp.txt deleted file mode 100644 index f8090e06530d..000000000000 --- a/Documentation/devicetree/bindings/media/fsl-pxp.txt +++ /dev/null @@ -1,26 +0,0 @@ -Freescale Pixel Pipeline -======================== - -The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine -that supports scaling, colorspace conversion, alpha blending, rotation, and -pixel conversion via lookup table. Different versions are present on various -i.MX SoCs from i.MX23 to i.MX7. - -Required properties: -- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28, - imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d. -- reg: the register base and size for the device registers -- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d. -- clock-names: should be "axi" -- clocks: the PXP AXI clock - -Example: - -pxp@21cc000 { - compatible = "fsl,imx6ull-pxp"; - reg = <0x021cc000 0x4000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "axi"; - clocks = <&clks IMX6UL_CLK_PXP>; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ak7375.txt b/Documentation/devicetree/bindings/media/i2c/ak7375.txt deleted file mode 100644 index aa3e24b41241..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ak7375.txt +++ /dev/null @@ -1,8 +0,0 @@ -Asahi Kasei Microdevices AK7375 voice coil lens driver - -AK7375 is a camera voice coil lens. - -Mandatory properties: - -- compatible: "asahi-kasei,ak7375" -- reg: I2C slave address diff --git a/Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml b/Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml new file mode 100644 index 000000000000..22a810fc7222 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/asahi-kasei,ak7375.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/asahi-kasei,ak7375.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Asahi Kasei Microdevices AK7375 voice coil lens actuator + +maintainers: + - Tianshu Qiu <tian.shu.qiu@intel.com> + +description: + AK7375 is a voice coil motor (VCM) camera lens actuator that + is controlled over I2C. + +properties: + compatible: + const: asahi-kasei,ak7375 + + reg: + maxItems: 1 + + vdd-supply: + description: VDD supply + + vio-supply: + description: I/O pull-up supply + +required: + - compatible + - reg + - vdd-supply + - vio-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ak7375: camera-lens@c { + compatible = "asahi-kasei,ak7375"; + reg = <0x0c>; + + vdd-supply = <&vreg_l23a_2p8>; + vio-supply = <&vreg_lvs1a_1p8>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml index 63e5b89d2e0b..af8ada55b3f2 100644 --- a/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml +++ b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml @@ -13,6 +13,9 @@ description: The Chrontel CH7322 is a discrete HDMI-CEC controller. It is programmable through I2C and drives a single CEC line. +allOf: + - $ref: /schemas/media/cec/cec-common.yaml# + properties: compatible: const: chrontel,ch7322 @@ -40,16 +43,12 @@ properties: if in auto mode. maxItems: 1 - # see ../cec.txt - hdmi-phandle: - description: phandle to the HDMI controller - required: - compatible - reg - interrupts -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -58,7 +57,7 @@ examples: i2c { #address-cells = <1>; #size-cells = <0>; - ch7322@75 { + cec@75 { compatible = "chrontel,ch7322"; reg = <0x75>; interrupts = <47 IRQ_TYPE_EDGE_RISING>; diff --git a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml index 90315e217003..0c4213adbf6a 100644 --- a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml +++ b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml @@ -39,7 +39,7 @@ properties: maxItems: 1 poc-supply: - description: Regulator providing Power over Coax to the cameras + description: Regulator providing Power over Coax to all the ports enable-gpios: description: GPIO connected to the \#PWDN pin with inverted polarity @@ -50,6 +50,21 @@ properties: '#gpio-cells': const: 2 + maxim,bus-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 24, 27, 32 ] + description: | + The GMSL serial data bus width. This setting is normally controlled by + the BWS pin, but may be overridden with this property. The value must + match the configuration of the remote serializers. + + maxim,i2c-remote-bus-hz: + enum: [ 8470, 28300, 84700, 105000, 173000, 339000, 533000, 837000 ] + default: 105000 + description: | + The I2C clock frequency for the remote I2C buses. The value must match + the configuration of the remote serializers. + maxim,reverse-channel-microvolt: minimum: 30000 maximum: 200000 @@ -182,21 +197,36 @@ properties: additionalProperties: false +patternProperties: + "^port[0-3]-poc-supply$": + description: Regulator providing Power over Coax for a particular port + required: - compatible - reg - ports - i2c-mux -# If 'maxim,gpio-poc' is present, then 'poc-supply' and 'gpio-controller' -# are not allowed. -if: - required: - - maxim,gpio-poc -then: - properties: - poc-supply: false - gpio-controller: false +allOf: + # Only one way of specifying power supplies is allowed: 'maxim,gpio-poc', + # 'poc-supply' or per-port poc-supply. Additionally, if 'maxim,gpio-poc' is + # present, then 'gpio-controller' isn't allowed. + - if: + required: + - maxim,gpio-poc + then: + properties: + poc-supply: false + gpio-controller: false + patternProperties: + "^port[0-3]-poc-supply$": false + + - if: + required: + - poc-supply + then: + patternProperties: + "^port[0-3]-poc-supply$": false additionalProperties: false @@ -219,6 +249,7 @@ examples: gpio-controller; #gpio-cells = <2>; + maxim,i2c-remote-bus-hz = <339000>; maxim,reverse-channel-microvolt = <170000>; ports { diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov5670.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov5670.yaml new file mode 100644 index 000000000000..6e089fe1d613 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov5670.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov5670.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OV5670 5 Megapixels raw image sensor + +maintainers: + - Jacopo Mondi <jacopo.mondi@ideasonboard.com> + +description: |- + The OV5670 is a 5 Megapixels raw image sensor which provides images in 10-bits + RAW BGGR Bayer format on a 2 data lanes MIPI CSI-2 serial interface and is + controlled through an I2C compatible control bus. + +properties: + compatible: + const: ovti,ov5670 + + reg: + maxItems: 1 + + clocks: + description: System clock. From 6 to 27 MHz. + maxItems: 1 + + powerdown-gpios: + description: Reference to the GPIO connected to the PWDNB pin. Active low. + + reset-gpios: + description: Reference to the GPIO connected to the XSHUTDOWN pin. Active low. + maxItems: 1 + + avdd-supply: + description: Analog circuit power. Typically 2.8V. + + dvdd-supply: + description: Digital circuit power. Typically 1.2V. + + dovdd-supply: + description: Digital I/O circuit power. Typically 2.8V or 1.8V. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + additionalProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 2 + items: + enum: [1, 2] + + clock-noncontinuous: true + remote-endpoint: true + +required: + - compatible + - reg + - clocks + - port + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov5670: sensor@36 { + compatible = "ovti,ov5670"; + reg = <0x36>; + + clocks = <&sensor_xclk>; + + port { + ov5670_ep: endpoint { + remote-endpoint = <&csi_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov5675.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov5675.yaml new file mode 100644 index 000000000000..ad07204057f9 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov5675.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov5675.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OV5675 CMOS Sensor + +maintainers: + - Quentin Schulz <quentin.schulz@theobroma-systems.com> + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +description: | + The Omnivision OV5675 is a high performance, 1/5-inch, 5 megapixel, CMOS + image sensor that delivers 2592x1944 at 30fps. It provides full-frame, + sub-sampled, and windowed 10-bit MIPI images in various formats via the + Serial Camera Control Bus (SCCB) interface. + + This chip is programmable through I2C and two-wire SCCB. The sensor output + is available via CSI-2 serial data output (up to 2-lane). + +properties: + compatible: + const: ovti,ov5675 + + reg: + maxItems: 1 + + clocks: + description: + System input clock (aka XVCLK). From 6 to 27 MHz. + maxItems: 1 + + dovdd-supply: + description: + Digital I/O voltage supply, 1.8 volts. + + avdd-supply: + description: + Analog voltage supply, 2.8 volts. + + dvdd-supply: + description: + Digital core voltage supply, 1.2 volts. + + reset-gpios: + description: + The phandle and specifier for the GPIO that controls sensor reset. + This corresponds to the hardware pin XSHUTDN which is physically + active low. + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 2 + + # Supports max data transfer of 900 Mbps per lane + link-frequencies: true + +required: + - compatible + - reg + - clocks + - dovdd-supply + - avdd-supply + - dvdd-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/px30-cru.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/pinctrl/rockchip.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov5675: camera@36 { + compatible = "ovti,ov5675"; + reg = <0x36>; + + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + assigned-clocks = <&cru SCLK_CIF_OUT>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vcc_1v8>; + dvdd-supply = <&vcc_1v2>; + dovdd-supply = <&vcc_2v8>; + + rotation = <90>; + orientation = <0>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <450000000>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov8858.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov8858.yaml new file mode 100644 index 000000000000..a65f921ec0fd --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov8858.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov8858.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV8858 Image Sensor + +maintainers: + - Jacopo Mondi <jacopo.mondi@ideasonboard.com> + - Nicholas Roth <nicholas@rothemail.net> + +description: | + The OmniVision OV8858 is a color CMOS 8 Megapixels (3264x2448) image sensor + controlled through an I2C-compatible SCCB bus. The sensor transmits images + on a MIPI CSI-2 output interface with up to 4 data lanes. + +properties: + compatible: + const: ovti,ov8858 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: XVCLK external clock + + clock-names: + const: xvclk + + dvdd-supply: + description: Digital Domain Power Supply + + avdd-supply: + description: Analog Domain Power Supply + + dovdd-supply: + description: I/O Domain Power Supply + + powerdown-gpios: + description: PWDNB powerdown GPIO (active low) + + reset-gpios: + maxItems: 1 + description: XSHUTDN reset GPIO (active low) + + port: + description: MIPI CSI-2 transmitter port + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - clocks + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov8858: camera@36 { + compatible = "ovti,ov8858"; + reg = <0x36>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + assigned-clocks = <&cru SCLK_CIF_OUT>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vcc1v8_dvp>; + + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml new file mode 100644 index 000000000000..65ad9c100e45 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx296.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX296 1/2.8-Inch CMOS Image Sensor + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> + +description: |- + The Sony IMX296 is a 1/2.9-Inch active pixel type CMOS Solid-state image + sensor with square pixel array and 1.58 M effective pixels. This chip + features a global shutter with variable charge-integration time. It is + programmable through I2C and 4-wire interfaces. The sensor output is + available via CSI-2 serial data output (1 Lane). + +properties: + compatible: + enum: + - sony,imx296 + - sony,imx296ll + - sony,imx296lq + description: + The IMX296 sensor exists in two different models, a colour variant + (IMX296LQ) and a monochrome variant (IMX296LL). The device exposes the + model through registers, allowing for auto-detection with a common + "sony,imx296" compatible string. However, some camera modules disable the + ability to read the sensor model register, which disables this feature. + In those cases, the exact model needs to be specified as "sony,imx296ll" + or "sony,imx296lq". + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: Input clock (37.125 MHz, 54 MHz or 74.25 MHz) + items: + - const: inck + + avdd-supply: + description: Analog power supply (3.3V) + + dvdd-supply: + description: Digital power supply (1.2V) + + ovdd-supply: + description: Interface power supply (1.8V) + + reset-gpios: + description: Sensor reset (XCLR) GPIO + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - avdd-supply + - dvdd-supply + - ovdd-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imx296: camera-sensor@1a { + compatible = "sony,imx296"; + reg = <0x1a>; + + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc 90>; + clock-names = "inck"; + + avdd-supply = <&camera_vdda_3v3>; + dvdd-supply = <&camera_vddd_1v2>; + ovdd-supply = <&camera_vddo_1v8>; + + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + + port { + imx296_ep: endpoint { + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml new file mode 100644 index 000000000000..ffccf5f3c9e3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx415.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX415 CMOS Image Sensor + +maintainers: + - Michael Riesch <michael.riesch@wolfvision.net> + +description: |- + The Sony IMX415 is a diagonal 6.4 mm (Type 1/2.8) CMOS active pixel type + solid-state image sensor with a square pixel array and 8.46 M effective + pixels. This chip operates with analog 2.9 V, digital 1.1 V, and interface + 1.8 V triple power supply, and has low power consumption. + The IMX415 is programmable through I2C interface. The sensor output is + available via CSI-2 serial data output (two or four lanes). + +allOf: + - $ref: ../video-interface-devices.yaml# + +properties: + compatible: + const: sony,imx415 + + reg: + maxItems: 1 + + clocks: + description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz) + maxItems: 1 + + avdd-supply: + description: Analog power supply (2.9 V) + + dvdd-supply: + description: Digital power supply (1.1 V) + + ovdd-supply: + description: Interface power supply (1.8 V) + + reset-gpios: + description: Sensor reset (XCLR) GPIO + maxItems: 1 + + flash-leds: true + + lens-focus: true + + orientation: true + + rotation: true + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + oneOf: + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + - link-frequencies + + required: + - endpoint + +required: + - compatible + - reg + - clocks + - avdd-supply + - dvdd-supply + - ovdd-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imx415: camera-sensor@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + avdd-supply = <&vcc2v9_cam>; + clocks = <&clock_cam>; + dvdd-supply = <&vcc1v1_cam>; + lens-focus = <&vcm>; + orientation = <2>; + ovdd-supply = <&vcc1v8_cam>; + reset-gpios = <&gpio_expander 14 GPIO_ACTIVE_LOW>; + rotation = <180>; + + port { + imx415_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&mipi_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml b/Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml index 4f7b78265336..358019e85d90 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml @@ -37,6 +37,9 @@ properties: items: - const: mclk + power-domains: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port @@ -50,6 +53,18 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-csi + - fsl,imx8mm-csi + then: + required: + - power-domains + examples: - | #include <dt-bindings/clock/imx7d-clock.h> diff --git a/Documentation/devicetree/bindings/media/s5p-cec.txt b/Documentation/devicetree/bindings/media/s5p-cec.txt deleted file mode 100644 index e847291d4aff..000000000000 --- a/Documentation/devicetree/bindings/media/s5p-cec.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Samsung HDMI CEC driver - -The HDMI CEC module is present is Samsung SoCs and its purpose is to -handle communication between HDMI connected devices over the CEC bus. - -Required properties: - - compatible : value should be following - "samsung,s5p-cec" - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : HDMI CEC interrupt number to the CPU. - - clocks : from common clock binding: handle to HDMI CEC clock. - - clock-names : from common clock binding: must contain "hdmicec", - corresponding to entry in the clocks property. - - samsung,syscon-phandle - phandle to the PMU system controller - - hdmi-phandle - phandle to the HDMI controller, see also cec.txt. - -Optional: - - needs-hpd : if present the CEC support is only available when the HPD - is high. See cec.txt for more details. - -Example: - -hdmicec: cec@100b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x100B0000 0x200>; - interrupts = <0 114 0>; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; -}; diff --git a/Documentation/devicetree/bindings/media/stih-cec.txt b/Documentation/devicetree/bindings/media/stih-cec.txt deleted file mode 100644 index ece0832fdeaf..000000000000 --- a/Documentation/devicetree/bindings/media/stih-cec.txt +++ /dev/null @@ -1,27 +0,0 @@ -STMicroelectronics STIH4xx HDMI CEC driver - -Required properties: - - compatible : value should be "st,stih-cec" - - reg : Physical base address of the IP registers and length of memory - mapped region. - - clocks : from common clock binding: handle to HDMI CEC clock - - interrupts : HDMI CEC interrupt number to the CPU. - - pinctrl-names: Contains only one value - "default" - - pinctrl-0: Specifies the pin control groups used for CEC hardware. - - resets: Reference to a reset controller - - hdmi-phandle: Phandle to the HDMI controller, see also cec.txt. - -Example for STIH407: - -sti-cec@94a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - hdmi-phandle = <&hdmi>; -}; diff --git a/Documentation/devicetree/bindings/media/tegra-cec.txt b/Documentation/devicetree/bindings/media/tegra-cec.txt deleted file mode 100644 index c503f06f3b84..000000000000 --- a/Documentation/devicetree/bindings/media/tegra-cec.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Tegra HDMI CEC hardware - -The HDMI CEC module is present in Tegra SoCs and its purpose is to -handle communication between HDMI connected devices over the CEC bus. - -Required properties: - - compatible : value should be one of the following: - "nvidia,tegra114-cec" - "nvidia,tegra124-cec" - "nvidia,tegra210-cec" - - reg : Physical base address of the IP registers and length of memory - mapped region. - - interrupts : HDMI CEC interrupt number to the CPU. - - clocks : from common clock binding: handle to HDMI CEC clock. - - clock-names : from common clock binding: must contain "cec", - corresponding to the entry in the clocks property. - - hdmi-phandle : phandle to the HDMI controller, see also cec.txt. - -Example: - -cec@70015000 { - compatible = "nvidia,tegra124-cec"; - reg = <0x0 0x70015000 0x0 0x00001000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA124_CLK_CEC>; - clock-names = "cec"; -}; diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml index 5fb4e7bfa4da..188db821dff3 100644 --- a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml# +$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx Expansion Bus Controller @@ -56,69 +56,7 @@ patternProperties: description: Devices attached to chip selects are represented as subnodes. type: object - - properties: - intel,ixp4xx-eb-t1: - description: Address timing, extend address phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t2: - description: Setup chip select timing, extend setup phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t3: - description: Strobe timing, extend strobe phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 15 - - intel,ixp4xx-eb-t4: - description: Hold timing, extend hold phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t5: - description: Recovery timing, extend recovery phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 15 - - intel,ixp4xx-eb-cycle-type: - description: The type of cycles to use on the expansion bus for this - chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] - - intel,ixp4xx-eb-byte-access-on-halfword: - description: Allow byte read access on half word devices. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-hpi-hrdy-pol-high: - description: Set HPI HRDY polarity to active high when using HPI. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-mux-address-and-data: - description: Multiplex address and data on the data bus. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-ahb-split-transfers: - description: Enable AHB split transfers. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-write-enable: - description: Enable write cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-byte-access: - description: Expansion bus uses only 8 bits. The default is to use - 16 bits. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] + $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml new file mode 100644 index 000000000000..d1479a7b9c8d --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral properties for Intel IXP4xx Expansion Bus + +description: + The IXP4xx expansion bus controller handles access to devices on the + memory-mapped expansion bus on the Intel IXP4xx family of system on chips, + including IXP42x, IXP43x, IXP45x and IXP46x. + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + intel,ixp4xx-eb-t1: + description: Address timing, extend address phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t2: + description: Setup chip select timing, extend setup phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t3: + description: Strobe timing, extend strobe phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + intel,ixp4xx-eb-t4: + description: Hold timing, extend hold phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t5: + description: Recovery timing, extend recovery phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + intel,ixp4xx-eb-cycle-type: + description: The type of cycles to use on the expansion bus for this + chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + intel,ixp4xx-eb-byte-access-on-halfword: + description: Allow byte read access on half word devices. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-hpi-hrdy-pol-high: + description: Set HPI HRDY polarity to active high when using HPI. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-mux-address-and-data: + description: Multiplex address and data on the data bus. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-ahb-split-transfers: + description: Enable AHB split transfers. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-write-enable: + description: Enable write cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + intel,ixp4xx-eb-byte-access: + description: Expansion bus uses only 8 bits. The default is to use + 16 bits. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 53ae995462db..5acfcad12bb7 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -34,5 +34,6 @@ required: # The controller specific properties go here. allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# + - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml index 4f30173ad747..bc9406929f6c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml @@ -90,7 +90,7 @@ properties: interrupt-controller: description: | - The GPMC driver implements and interrupt controller for + The GPMC driver implements an interrupt controller for the NAND events "fifoevent" and "termcount" plus the rising/falling edges on the GPMC_WAIT pins. The interrupt number mapping is as follows diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml new file mode 100644 index 000000000000..ca9fc747bf4f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynqmp OCM(On-Chip Memory) Controller + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> + +description: | + The OCM supports 64-bit wide ECC functionality to detect multi-bit errors + and recover from a single-bit memory fault.On a write, if all bytes are + being written, the ECC is generated and written into the ECC RAM along with + the write-data that is written into the data RAM. If one or more bytes are + not written, then the read operation results in an correctable error or + uncorrectable error. + +properties: + compatible: + const: xlnx,zynqmp-ocmc-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0xff960000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml index 3d5efa5578d1..cdf1d719efe9 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -33,6 +33,9 @@ properties: - description: For implementations of the EC connected through RPMSG. const: google,cros-ec-rpmsg + - description: + For implementations of the EC connected through UART. + const: google,cros-ec-uart controller-data: true @@ -187,6 +190,15 @@ allOf: properties: mediatek,rpmsg-name: false + - if: + properties: + compatible: + not: + contains: + enum: + - google,cros-ec-rpmsg + - google,cros-ec-uart + then: required: - reg - interrupts @@ -299,4 +311,12 @@ examples: vdd-supply = <&pp3300_fp_mcu>; }; }; + + # Example for UART + - | + serial { + cros-ec { + compatible = "google,cros-ec-uart"; + }; + }; ... diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml new file mode 100644 index 000000000000..837a77013d57 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6357 PMIC + +maintainers: + - Flora Fu <flora.fu@mediatek.com> + - Alexandre Mergnat <amergnat@baylibre.com> + +description: | + MT6357 is a power management system chip containing 5 buck + converters and 29 LDOs. Supported features are audio codec, + USB battery charging, fuel gauge, RTC + + This is a multifunction device with the following sub modules: + - Regulator + - RTC + - Keys + + It is interfaced to host controller using SPI interface by a proprietary hardware + called PMIC wrapper or pwrap. This MFD is a child device of pwrap. + See the following for pwrap node definitions: + Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml + +properties: + compatible: + const: mediatek,mt6357 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + regulators: + type: object + $ref: /schemas/regulator/mediatek,mt6357-regulator.yaml + description: + List of MT6357 BUCKs and LDOs regulators. + + rtc: + type: object + $ref: /schemas/rtc/rtc.yaml# + description: + MT6357 Real Time Clock. + properties: + compatible: + const: mediatek,mt6357-rtc + start-year: true + required: + - compatible + + keys: + type: object + $ref: /schemas/input/mediatek,pmic-keys.yaml + description: + MT6357 power and home keys. + +required: + - compatible + - regulators + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pwrap { + pmic { + compatible = "mediatek,mt6357"; + + interrupt-parent = <&pio>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name = "vproc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + // ... + + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + rtc { + compatible = "mediatek,mt6357-rtc"; + }; + + keys { + compatible = "mediatek,mt6357-keys"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml index 1d1fee1a16c1..8bd1abfc44d9 100644 --- a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml +++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml @@ -57,6 +57,15 @@ patternProperties: enum: - mscc,ocelot-miim + "^ethernet-switch@[0-9a-f]+$": + type: object + $ref: /schemas/net/mscc,vsc7514-switch.yaml + unevaluatedProperties: false + properties: + compatible: + enum: + - mscc,vsc7512-switch + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index 518986c44880..294693a8906c 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -13,7 +13,7 @@ MT6397/MT6323 is a multifunction device with the following sub modules: It is interfaced to host controller using SPI interface by a proprietary hardware called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap. See the following for pwarp node definitions: -../soc/mediatek/pwrap.txt +../soc/mediatek/mediatek,pwrap.yaml This document describes the binding for MFD device and its sub module. diff --git a/Documentation/devicetree/bindings/mfd/nxp,bbnsm.yaml b/Documentation/devicetree/bindings/mfd/nxp,bbnsm.yaml new file mode 100644 index 000000000000..b1ade64a1554 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/nxp,bbnsm.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/nxp,bbnsm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Battery-Backed Non-Secure Module + +maintainers: + - Jacky Bai <ping.bai@nxp.com> + +description: | + NXP BBNSM serves as non-volatile logic and storage for the system. + it Intergrates RTC & ON/OFF control. + The RTC can retain its state and continues counting even when the + main chip is power down. A time alarm is generated once the most + significant 32 bits of the real-time counter match the value in the + Time Alarm register. + The ON/OFF logic inside the BBNSM allows for connecting directly to + a PMIC or other voltage regulator device. both smart PMIC mode and + Dumb PMIC mode supported. + +properties: + compatible: + items: + - enum: + - nxp,imx93-bbnsm + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + rtc: + type: object + $ref: /schemas/rtc/rtc.yaml# + + properties: + compatible: + enum: + - nxp,imx93-bbnsm-rtc + + interrupts: + maxItems: 1 + + start-year: true + + required: + - compatible + - interrupts + + additionalProperties: false + + pwrkey: + type: object + $ref: /schemas/input/input.yaml# + + properties: + compatible: + enum: + - nxp,imx93-bbnsm-pwrkey + + interrupts: + maxItems: 1 + + linux,code: true + + required: + - compatible + - interrupts + + additionalProperties: false + +required: + - compatible + - reg + - rtc + - pwrkey + +additionalProperties: false + +examples: + - | + #include <dt-bindings/input/linux-event-codes.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bbnsm: bbnsm@44440000 { + compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,imx93-bbnsm-rtc"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,imx93-bbnsm-pwrkey"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + linux,code = <KEY_POWER>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt index aa1eaa59581b..a0d8c30c2631 100644 --- a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt +++ b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt @@ -64,8 +64,8 @@ Required properties if child node exists: Properties for children: The OMAP HS USB Host subsystem contains EHCI and OHCI controllers. -See Documentation/devicetree/bindings/usb/ehci-omap.txt and -Documentation/devicetree/bindings/usb/ohci-omap3.txt. +See Documentation/devicetree/bindings/usb/generic-ehci.yaml and +Documentation/devicetree/bindings/usb/generic-ohci.yaml. Example for OMAP4: @@ -78,14 +78,14 @@ usbhshost: usbhshost@4a064000 { ranges; usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3", "usb-ohci"; + compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; interrupt-parent = <&gic>; interrupts = <0 76 0x4>; }; usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap", "usb-ehci"; + compatible = "ti,ehci-omap"; reg = <0x4a064c00 0x400>; interrupt-parent = <&gic>; interrupts = <0 77 0x4>; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 37d16e16f444..adf88245c409 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -44,6 +44,7 @@ properties: - qcom,pm8004 - qcom,pm8005 - qcom,pm8009 + - qcom,pm8010 - qcom,pm8019 - qcom,pm8028 - qcom,pm8110 @@ -55,6 +56,10 @@ properties: - qcom,pm8350 - qcom,pm8350b - qcom,pm8350c + - qcom,pm8550 + - qcom,pm8550b + - qcom,pm8550ve + - qcom,pm8550vs - qcom,pm8841 - qcom,pm8909 - qcom,pm8916 @@ -71,10 +76,12 @@ properties: - qcom,pmi8998 - qcom,pmk8002 - qcom,pmk8350 + - qcom,pmk8550 - qcom,pmm8155au - qcom,pmp8074 - qcom,pmr735a - qcom,pmr735b + - qcom,pmr735d - qcom,pms405 - qcom,pmx55 - qcom,pmx65 diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index adcae6c007d9..2eeebe920e6e 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -28,9 +28,11 @@ properties: - qcom,sm8150-tcsr - qcom,tcsr-apq8064 - qcom,tcsr-apq8084 + - qcom,tcsr-ipq5332 - qcom,tcsr-ipq6018 - qcom,tcsr-ipq8064 - qcom,tcsr-mdm9615 + - qcom,tcsr-msm8226 - qcom,tcsr-msm8660 - qcom,tcsr-msm8916 - qcom,tcsr-msm8953 diff --git a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt deleted file mode 100644 index b823b8625243..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt +++ /dev/null @@ -1,283 +0,0 @@ -Qualcomm Resource Power Manager (RPM) - -This driver is used to interface with the Resource Power Manager (RPM) found in -various Qualcomm platforms. The RPM allows each component in the system to vote -for state of the system resources, such as clocks, regulators and bus -frequencies. - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,rpm-apq8064" - "qcom,rpm-msm8660" - "qcom,rpm-msm8960" - "qcom,rpm-ipq8064" - "qcom,rpm-mdm9615" - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: base address and size of the RPM's message ram - -- interrupts: - Usage: required - Value type: <prop-encoded-array> - Definition: three entries specifying the RPM's: - 1. acknowledgement interrupt - 2. error interrupt - 3. wakeup interrupt - -- interrupt-names: - Usage: required - Value type: <string-array> - Definition: must be the three strings "ack", "err" and "wakeup", in order - -- qcom,ipc: - Usage: required - Value type: <prop-encoded-array> - - Definition: three entries specifying the outgoing ipc bit used for - signaling the RPM: - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - - -= SUBNODES - -The RPM exposes resources to its subnodes. The below bindings specify the set -of valid subnodes that can operate on these resources. - -== Regulators - -Regulator nodes are identified by their compatible: - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,rpm-pm8058-regulators" - "qcom,rpm-pm8901-regulators" - "qcom,rpm-pm8921-regulators" - "qcom,rpm-pm8018-regulators" - "qcom,rpm-smb208-regulators" - -- vdd_l0_l1_lvs-supply: -- vdd_l2_l11_l12-supply: -- vdd_l3_l4_l5-supply: -- vdd_l6_l7-supply: -- vdd_l8-supply: -- vdd_l9-supply: -- vdd_l10-supply: -- vdd_l13_l16-supply: -- vdd_l14_l15-supply: -- vdd_l17_l18-supply: -- vdd_l19_l20-supply: -- vdd_l21-supply: -- vdd_l22-supply: -- vdd_l23_l24_l25-supply: -- vdd_ncp-supply: -- vdd_s0-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: - Usage: optional (pm8058 only) - Value type: <phandle> - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- lvs0_in-supply: -- lvs1_in-supply: -- lvs2_in-supply: -- lvs3_in-supply: -- mvs_in-supply: -- vdd_l0-supply: -- vdd_l1-supply: -- vdd_l2-supply: -- vdd_l3-supply: -- vdd_l4-supply: -- vdd_l5-supply: -- vdd_l6-supply: -- vdd_s0-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: - Usage: optional (pm8901 only) - Value type: <phandle> - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_l1_l2_l12_l18-supply: -- vdd_l3_l15_l17-supply: -- vdd_l4_l14-supply: -- vdd_l5_l8_l16-supply: -- vdd_l6_l7-supply: -- vdd_l9_l11-supply: -- vdd_l10_l22-supply: -- vdd_l21_l23_l29-supply: -- vdd_l24-supply: -- vdd_l25-supply: -- vdd_l26-supply: -- vdd_l27-supply: -- vdd_l28-supply: -- vdd_ncp-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vin_5vs-supply: -- vin_lvs1_3_6-supply: -- vin_lvs2-supply: -- vin_lvs4_5_7-supply: - Usage: optional (pm8921 only) - Value type: <phandle> - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vin_lvs1-supply: -- vdd_l7-supply: -- vdd_l8-supply: -- vdd_l9_l10_l11_l12-supply: - Usage: optional (pm8018 only) - Value type: <phandle> - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -The regulator node houses sub-nodes for each regulator within the device. Each -sub-node is identified using the node's name, with valid values listed for each -of the pmics below. - -pm8058: - l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, - l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, s0, s1, s2, s3, s4, - lvs0, lvs1, ncp - -pm8901: - l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3, - mvs - -pm8921: - s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, l15, l16, l17, l18, l21, l22, l23, l24, l25, l26, l27, l28, - l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch, - ncp - -pm8018: - s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, lvs1 - -smb208: - s1a, s1b, s2a, s2b - -The content of each sub-node is defined by the standard binding for regulators - -see regulator.txt - with additional custom properties described below: - -=== Switch-mode Power Supply regulator custom properties - -- bias-pull-down: - Usage: optional - Value type: <empty> - Definition: enable pull down of the regulator when inactive - -- qcom,switch-mode-frequency: - Usage: required - Value type: <u32> - Definition: Frequency (Hz) of the switch-mode power supply; - must be one of: - 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, - 2740000, 2400000, 2130000, 1920000, 1750000, 1600000, - 1480000, 1370000, 1280000, 1200000 - -- qcom,force-mode: - Usage: optional (default if no other qcom,force-mode is specified) - Value type: <u32> - Definition: indicates that the regulator should be forced to a - particular mode, valid values are: - QCOM_RPM_FORCE_MODE_NONE - do not force any mode - QCOM_RPM_FORCE_MODE_LPM - force into low power mode - QCOM_RPM_FORCE_MODE_HPM - force into high power mode - QCOM_RPM_FORCE_MODE_AUTO - allow regulator to automatically - select its own mode based on - realtime current draw, only for: - pm8921 smps and ftsmps - -- qcom,power-mode-hysteretic: - Usage: optional - Value type: <empty> - Definition: select that the power supply should operate in hysteretic - mode, instead of the default pwm mode - -=== Low-dropout regulator custom properties - -- bias-pull-down: - Usage: optional - Value type: <empty> - Definition: enable pull down of the regulator when inactive - -- qcom,force-mode: - Usage: optional - Value type: <u32> - Definition: indicates that the regulator should not be forced to any - particular mode, valid values are: - QCOM_RPM_FORCE_MODE_NONE - do not force any mode - QCOM_RPM_FORCE_MODE_LPM - force into low power mode - QCOM_RPM_FORCE_MODE_HPM - force into high power mode - QCOM_RPM_FORCE_MODE_BYPASS - set regulator to use bypass - mode, i.e. to act as a switch - and not regulate, only for: - pm8921 pldo, nldo and nldo1200 - -=== Negative Charge Pump custom properties - -- qcom,switch-mode-frequency: - Usage: required - Value type: <u32> - Definition: Frequency (Hz) of the switch mode power supply; - must be one of: - 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, - 2740000, 2400000, 2130000, 1920000, 1750000, 1600000, - 1480000, 1370000, 1280000, 1200000 - -= EXAMPLE - - #include <dt-bindings/mfd/qcom-rpm.h> - - rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&apcs 0x8 2>; - - interrupts = <0 19 0>, <0 21 0>, <0 22 0>; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - - s1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - bias-pull-down; - - qcom,switch-mode-frequency = <3200000>; - }; - - pm8921_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - - qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 1b01bd010431..c828c4f5e4a7 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - amd,pensando-elba-syscon - brcm,cru-clkset - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg @@ -46,10 +47,12 @@ properties: - hisilicon,hi6220-sramctrl - hisilicon,pcie-sas-subctrl - hisilicon,peri-subctrl + - hpe,gxp-sysreg - intel,lgm-syscon - marvell,armada-3700-usb2-host-misc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep @@ -64,12 +67,6 @@ properties: - rockchip,rk3568-qos - rockchip,rk3588-qos - rockchip,rv1126-qos - - samsung,exynos3-sysreg - - samsung,exynos4-sysreg - - samsung,exynos5-sysreg - - samsung,exynos5433-sysreg - - samsung,exynos850-sysreg - - samsung,exynosautov9-sysreg - const: syscon @@ -87,6 +84,9 @@ properties: on the device. enum: [1, 2, 4, 8] + resets: + maxItems: 1 + hwlocks: maxItems: 1 description: diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml new file mode 100644 index 000000000000..1b6020e4ec27 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Inject IP + +maintainers: + - Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> + +description: | + The Triple Modular Redundancy(TMR) Inject core provides functional fault + injection by changing selected MicroBlaze instructions, which provides the + possibility to verify that the TMR subsystem error detection and fault + recovery logic is working properly. + +properties: + compatible: + enum: + - xlnx,tmr-inject-1.0 + + reg: + maxItems: 1 + + xlnx,magic: + minimum: 0 + maximum: 255 + description: | + Magic number, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic + +additionalProperties: false + +examples: + - | + fault-inject@44a30000 { + compatible = "xlnx,tmr-inject-1.0"; + reg = <0x44a10000 0x10000>; + xlnx,magic = <0x46>; + }; diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml new file mode 100644 index 000000000000..27de12147a52 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Manager IP + +maintainers: + - Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> + +description: | + The Triple Modular Redundancy(TMR) Manager is responsible for handling the + TMR subsystem state, including fault detection and error recovery. The core + is triplicated in each of the sub-blocks in the TMR subsystem, and provides + majority voting of its internal state. + +properties: + compatible: + enum: + - xlnx,tmr-manager-1.0 + + reg: + maxItems: 1 + + xlnx,magic1: + minimum: 0 + maximum: 255 + description: + Magic byte 1, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic1 + +additionalProperties: false + +examples: + - | + tmr-manager@44a10000 { + compatible = "xlnx,tmr-manager-1.0"; + reg = <0x44a10000 0x10000>; + xlnx,magic1 = <0x46>; + }; diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 02ecc93417ef..0ccd632d5620 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A10 MMC Controller allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml new file mode 100644 index 000000000000..bc403ae9e5d9 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/amlogic,meson-gx-mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic SD / eMMC controller for S905/GXBB family SoCs + +description: + The MMC 5.1 compliant host controller on Amlogic provides the + interface for SD, eMMC and SDIO devices + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + oneOf: + - const: amlogic,meson-axg-mmc + - items: + - const: amlogic,meson-gx-mmc + - const: amlogic,meson-gxbb-mmc + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: mmc controller instance + - description: card detect + + clocks: + maxItems: 3 + + clock-names: + items: + - const: core + - const: clkin0 + - const: clkin1 + + resets: + maxItems: 1 + + amlogic,dram-access-quirk: + type: boolean + description: + set when controller's internal DMA engine cannot access the DRAM memory, + like on the G12A dedicated SDIO controller. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + mmc@70000 { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x70000 0x2000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; + clocks = <&clk_mmc>, <&xtal>, <&clk_div>; + clock-names = "core", "clkin0", "clkin1"; + pinctrl-0 = <&emm_pins>; + resets = <&reset_mmc>; + }; diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt deleted file mode 100644 index ccc5358db131..000000000000 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt +++ /dev/null @@ -1,39 +0,0 @@ -Amlogic SD / eMMC controller for S905/GXBB family SoCs - -The MMC 5.1 compliant host controller on Amlogic provides the -interface for SD, eMMC and SDIO devices. - -This file documents the properties in addition to those available in -the MMC core bindings, documented by mmc.txt. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gx-mmc" - - "amlogic,meson-gxbb-mmc" - - "amlogic,meson-gxl-mmc" - - "amlogic,meson-gxm-mmc" - - "amlogic,meson-axg-mmc" -- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. -- clock-names: Should contain the following: - "core" - Main peripheral bus clock - "clkin0" - Parent clock of internal mux - "clkin1" - Other parent clock of internal mux - The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the - clock rate requested by the MMC core. -- resets : phandle of the internal reset line - -Optional properties: -- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the - DRAM memory, like on the G12A dedicated SDIO controller. - -Example: - - sd_emmc_a: mmc@70000 { - compatible = "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x2000>; - interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - pinctrl-0 = <&emmc_pins>; - resets = <&reset RESET_SD_EMMC_A>; - }; diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml index 1c391bec43dc..1a6cda82f296 100644 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson SDHC controller allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml maintainers: - Martin Blumenstingl <martin.blumenstingl@googlemail.com> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index 4053de758db6..8296c34cfa00 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Arasan SDHCI Controller @@ -10,7 +10,7 @@ maintainers: - Adrian Hunter <adrian.hunter@intel.com> allOf: - - $ref: "mmc-controller.yaml#" + - $ref: mmc-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index 8b1a0fdcb5e3..adacd0535c14 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -29,6 +29,9 @@ properties: clocks: maxItems: 1 + resets: + maxItems: 1 + # PHY DLL input delays: # They are used to delay the data valid window, and align the window to # sampling clock. The delay starts from 5ns (for delay parameter equal to 0) @@ -36,43 +39,43 @@ properties: cdns,phy-input-delay-sd-highspeed: description: Value of the delay in the input path for SD high-speed timing - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f cdns,phy-input-delay-legacy: description: Value of the delay in the input path for legacy timing - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f cdns,phy-input-delay-sd-uhs-sdr12: description: Value of the delay in the input path for SD UHS SDR12 timing - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f cdns,phy-input-delay-sd-uhs-sdr25: description: Value of the delay in the input path for SD UHS SDR25 timing - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f cdns,phy-input-delay-sd-uhs-sdr50: description: Value of the delay in the input path for SD UHS SDR50 timing - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f cdns,phy-input-delay-sd-uhs-ddr50: description: Value of the delay in the input path for SD UHS DDR50 timing - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f cdns,phy-input-delay-mmc-highspeed: description: Value of the delay in the input path for MMC high-speed timing - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f @@ -83,7 +86,7 @@ properties: # Each delay property represents the fraction of the clock period. # The approximate delay value will be # (<delay property value>/128)*sdmclk_clock_period. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x1f @@ -91,7 +94,7 @@ properties: description: | Value of the delay introduced on the sdclk output for all modes except HS200, HS400 and HS400_ES. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x7f @@ -99,7 +102,7 @@ properties: description: | Value of the delay introduced on the sdclk output for HS200, HS400 and HS400_ES speed modes. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x7f @@ -107,7 +110,7 @@ properties: description: | Value of the delay introduced on the dat_strobe input used in HS400 / HS400_ES speed modes. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 0x7f diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index dc6256f04b42..7f721fbfb009 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -10,7 +10,7 @@ maintainers: - Shawn Guo <shawnguo@kernel.org> allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml description: | The Enhanced Secure Digital Host Controller on Freescale i.MX family @@ -29,15 +29,24 @@ properties: - fsl,imx53-esdhc - fsl,imx6q-usdhc - fsl,imx6sl-usdhc - - fsl,imx6sll-usdhc - fsl,imx6sx-usdhc - - fsl,imx6ull-usdhc - fsl,imx7d-usdhc - fsl,imx7ulp-usdhc - fsl,imx8mm-usdhc - fsl,imxrt1050-usdhc - nxp,s32g2-usdhc - items: + - const: fsl,imx50-esdhc + - const: fsl,imx53-esdhc + - items: + - enum: + - fsl,imx6sll-usdhc + - fsl,imx6ull-usdhc + - const: fsl,imx6sx-usdhc + - items: + - const: fsl,imx7d-usdhc + - const: fsl,imx6sl-usdhc + - items: - enum: - fsl,imx8mq-usdhc - const: fsl,imx7d-usdhc @@ -98,12 +107,12 @@ properties: Specify the number of delay cells for override mode. This is used to set the clock delay for DLL(Delay Line) on override mode to select a proper data sampling window in case the clock quality is not good - due to signal path is too long on the board. Please refer to eSDHC/uSDHC + because the signal path is too long on the board. Please refer to eSDHC/uSDHC chapter, DLL (Delay Line) section in RM for details. default: 0 voltage-ranges: - $ref: '/schemas/types.yaml#/definitions/uint32-matrix' + $ref: /schemas/types.yaml#/definitions/uint32-matrix description: | Specify the voltage range in case there are software transparent level shifters on the outputs of the controller. Two cells are required, first @@ -127,7 +136,7 @@ properties: Specify the increasing delay cell steps in tuning procedure. The uSDHC use one delay cell as default increasing step to do tuning process. This property allows user to change the tuning step to more than one delay - cells which is useful for some special boards or cards when the default + cell which is useful for some special boards or cards when the default tuning step can't find the proper delay window within limited tuning retries. default: 0 diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml index ffa162722b8e..221f5bc047bd 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml @@ -10,7 +10,7 @@ maintainers: - Markus Pargmann <mpa@pengutronix.de> allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml properties: compatible: diff --git a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml index fa6cfe092fc9..1f63faf17743 100644 --- a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip Sparx5 Mobile Storage Host Controller allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml maintainers: - Lars Povlsen <lars.povlsen@microchip.com> @@ -35,7 +35,7 @@ properties: microchip,clock-delay: description: Delay clock to card to meet setup time requirements. Each step increase by 1.25ns. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 15 diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml index 911a5996e099..588be73168fa 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml @@ -41,7 +41,7 @@ additionalProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - sdhci0_pwrseq { + pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; }; diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml index 3397dbff88c2..b35e00e8c65e 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml @@ -35,7 +35,7 @@ additionalProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - wifi_pwrseq: wifi_pwrseq { + pwrseq { compatible = "mmc-pwrseq-sd8787"; powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml index 64e3644eefeb..00feaafc1063 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml @@ -55,7 +55,7 @@ additionalProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - sdhci0_pwrseq { + pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; clocks = <&clk_32768_ck>; diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml index c0662ce9946d..36acc40c7d18 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml @@ -10,7 +10,7 @@ maintainers: - Ulf Hansson <ulf.hansson@linaro.org> allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml - $ref: /schemas/spi/spi-peripheral-props.yaml description: | diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.yaml b/Documentation/devicetree/bindings/mmc/mxs-mmc.yaml index bec8f8c71ff2..32e512a68ed6 100644 --- a/Documentation/devicetree/bindings/mmc/mxs-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/mxs-mmc.yaml @@ -17,7 +17,7 @@ description: | and the properties used by the mxsmmc driver. allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml properties: compatible: diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index fe0270207622..72987f0326a1 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -82,8 +82,7 @@ properties: iommus: maxItems: 1 - operating-points-v2: - $ref: "/schemas/types.yaml#/definitions/phandle" + operating-points-v2: true power-domains: items: @@ -100,53 +99,53 @@ properties: The DQS trim values are only used on controllers which support HS400 timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,default-trim: description: Specify the default outbound clock trimmer value. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,dqs-trim: description: Specify DQS trim value for HS400 timing. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-down-offset-1v8: description: Specify drive strength calibration offsets for 1.8 V signaling modes. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-down-offset-1v8-timeout: description: Specify drive strength used as a fallback in case the automatic calibration times out on a 1.8 V signaling mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-down-offset-3v3: description: Specify drive strength calibration offsets for 3.3 V signaling modes. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-down-offset-3v3-timeout: description: Specify drive strength used as a fallback in case the automatic calibration times out on a 3.3 V signaling mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-down-offset-sdr104: description: Specify drive strength calibration offsets for SDR104 mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-down-offset-hs400: description: Specify drive strength calibration offsets for HS400 mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-up-offset-1v8: description: Specify drive strength calibration offsets for 1.8 V signaling modes. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-up-offset-1v8-timeout: description: Specify drive strength used as a fallback in case the automatic calibration times out on a 1.8 V signaling mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-up-offset-3v3: description: Specify drive strength calibration offsets for 3.3 V @@ -158,25 +157,25 @@ properties: refer to the reference manual of the SoC for correct values. The SDR104 and HS400 timing specific values are used in corresponding modes if specified. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-up-offset-3v3-timeout: description: Specify drive strength used as a fallback in case the automatic calibration times out on a 3.3 V signaling mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-up-offset-sdr104: description: Specify drive strength calibration offsets for SDR104 mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,pad-autocal-pull-up-offset-hs400: description: Specify drive strength calibration offsets for HS400 mode. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,only-1-8v: description: The presence of this property indicates that the controller operates at a 1.8 V fixed I/O voltage. - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag required: - compatible @@ -187,7 +186,7 @@ required: - reset-names allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml index b0d81ebe0f6e..1b7d88ed3799 100644 --- a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Actions Semi Owl SoCs SD/MMC/SDIO controller allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.yaml b/Documentation/devicetree/bindings/mmc/renesas,mmcif.yaml index c36ba561c387..024313b79ec9 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.yaml @@ -10,7 +10,7 @@ maintainers: - Wolfram Sang <wsa+renesas@sang-engineering.com> allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml properties: compatible: diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 7bfb10c62566..7756a8687eaf 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas SDHI SD/MMC controller @@ -59,6 +59,7 @@ properties: - renesas,sdhi-r9a07g043 # RZ/G2UL - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} - renesas,sdhi-r9a07g054 # RZ/V2L + - renesas,sdhi-r9a09g011 # RZ/V2M - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 - items: - enum: @@ -111,7 +112,7 @@ properties: max-frequency: true allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml - if: properties: @@ -121,6 +122,7 @@ allOf: - renesas,sdhi-r9a07g043 - renesas,sdhi-r9a07g044 - renesas,sdhi-r9a07g054 + - renesas,sdhi-r9a09g011 then: properties: clocks: diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml index c7e14b7dba9e..211cd0b0bc5f 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml @@ -14,7 +14,7 @@ description: file and the Rockchip specific extensions. allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" + - $ref: synopsys-dw-mshc-common.yaml# maintainers: - Heiko Stuebner <heiko@sntech.de> @@ -39,6 +39,7 @@ properties: - rockchip,rk3368-dw-mshc - rockchip,rk3399-dw-mshc - rockchip,rk3568-dw-mshc + - rockchip,rk3588-dw-mshc - rockchip,rv1108-dw-mshc - rockchip,rv1126-dw-mshc - const: rockchip,rk3288-dw-mshc diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index fdaa18481aa0..6ee78a38bd74 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -112,7 +112,7 @@ required: - samsung,dw-mshc-sdr-timing allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" + - $ref: synopsys-dw-mshc-common.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt b/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt deleted file mode 100644 index 5f68feb9f9d6..000000000000 --- a/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings - -Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface -with external MMC, SD and SDIO storage mediums. - -This file documents differences between the core mmc properties described by -mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller -implementation. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "samsung,s3c2410-sdi": for controllers compatible with s3c2410 - - "samsung,s3c2412-sdi": for controllers compatible with s3c2412 - - "samsung,s3c2440-sdi": for controllers compatible with s3c2440 -- reg: register location and length -- interrupts: mmc controller interrupt -- clocks: Should reference the controller clock -- clock-names: Should contain "sdi" - -Required Board Specific Properties: -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". - -Optional Properties: -- bus-width: number of data lines (see mmc.txt) -- cd-gpios: gpio for card detection (see mmc.txt) -- wp-gpios: gpio for write protection (see mmc.txt) - -Example: - - mmc0: mmc@5a000000 { - compatible = "samsung,s3c2440-sdi"; - pinctrl-names = "default"; - pinctrl-0 = <&sdi_pins>; - reg = <0x5a000000 0x100000>; - interrupts = <0 0 21 3>; - clocks = <&clocks PCLK_SDI>; - clock-names = "sdi"; - bus-width = <4>; - cd-gpios = <&gpg 8 GPIO_ACTIVE_LOW>; - wp-gpios = <&gph 8 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 6b89238f0565..64df6919abaf 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -34,6 +34,8 @@ properties: - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 - items: - enum: + - qcom,ipq5332-sdhci + - qcom,ipq9574-sdhci - qcom,qcs404-sdhci - qcom,sc7180-sdhci - qcom,sc7280-sdhci @@ -125,11 +127,13 @@ properties: phandle to apps_smmu node with sid mask. interconnects: + minItems: 1 items: - description: data path, sdhc to ddr - description: config path, cpu to sdhc interconnect-names: + minItems: 1 items: - const: sdhc-ddr - const: cpu-sdhc diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index 3d46c2525787..09455f9fa8de 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell PXA SDHCI v2/v3 +title: Marvell PXA SDHCI v1/v2/v3 maintainers: - Ulf Hansson <ulf.hansson@linaro.org> @@ -34,6 +34,7 @@ allOf: properties: compatible: enum: + - mrvl,pxav1-mmc - mrvl,pxav2-mmc - mrvl,pxav3-mmc - marvell,armada-380-sdhci @@ -61,6 +62,22 @@ properties: - const: io - const: core + pinctrl-names: + description: + Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between + SDIO CMD and GPIO mode. + items: + - const: default + - const: state_cmd_gpio + + pinctrl-0: + description: + Should contain default pinctrl. + + pinctrl-1: + description: + Should switch CMD pin to GPIO mode as a high output. + mrvl,clk-delay-cycles: description: Specify a number of cycles to delay for tuning. $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml index a586fad0a46b..c71424aeaccd 100644 --- a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml @@ -55,6 +55,16 @@ properties: minItems: 1 maxItems: 3 + socionext,syscon-uhs-mode: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to syscon that configures UHS mode + - description: ID of SD instance + description: + A phandle to syscon with one argument that configures UHS mode. + The argument is the ID of SD instance. + allOf: - $ref: mmc-controller.yaml diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml new file mode 100644 index 000000000000..51e1b04e799f --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive Designware Mobile Storage Host Controller + +description: + StarFive uses the Synopsys designware mobile storage host controller + to interface a SoC with storage medium such as eMMC or SD/MMC cards. + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + +maintainers: + - William Qiu <william.qiu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-mmc + + reg: + maxItems: 1 + + clocks: + items: + - description: biu clock + - description: ciu clock + + clock-names: + items: + - const: biu + - const: ciu + + interrupts: + maxItems: 1 + + starfive,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller syscon node + - description: offset of SYS_SYSCONSAIF__SYSCFG register for MMC controller + - description: shift of SYS_SYSCONSAIF__SYSCFG register for MMC controller + - description: mask of SYS_SYSCONSAIF__SYSCFG register for MMC controller + description: + Should be four parameters, the phandle to System Register Controller + syscon node and the offset/shift/mask of SYS_SYSCONSAIF__SYSCFG register + for MMC controller. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - starfive,sysreg + +unevaluatedProperties: false + +examples: + - | + mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x16010000 0x10000>; + clocks = <&syscrg 91>, + <&syscrg 93>; + clock-names = "biu","ciu"; + resets = <&syscrg 64>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; + }; diff --git a/Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml b/Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml index 23aa8e6b2d70..611687166735 100644 --- a/Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml @@ -12,7 +12,7 @@ maintainers: - Li-hao Kuo <lhjeff911@gmail.com> allOf: - - $ref: "mmc-controller.yaml" + - $ref: mmc-controller.yaml properties: compatible: diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml index 8dfad89c78a7..6f11b2adf103 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Common Properties allOf: - - $ref: "mmc-controller.yaml#" + - $ref: mmc-controller.yaml# maintainers: - Ulf Hansson <ulf.hansson@linaro.org> diff --git a/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml b/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml new file mode 100644 index 000000000000..a6e7f123eda7 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC) + +maintainers: + - Xiangsheng Hou <xiangsheng.hou@mediatek.com> + +properties: + compatible: + enum: + - mediatek,mt2701-nfc + - mediatek,mt2712-nfc + - mediatek,mt7622-nfc + + reg: + items: + - description: Base physical address and size of NFI. + + interrupts: + items: + - description: NFI interrupt + + clocks: + items: + - description: clock used for the controller + - description: clock used for the pad + + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + ecc-engine: + description: device-tree node of the required ECC engine. + $ref: /schemas/types.yaml#/definitions/phandle + +patternProperties: + "^nand@[a-f0-9]$": + $ref: nand-chip.yaml# + unevaluatedProperties: false + properties: + reg: + maximum: 1 + nand-on-flash-bbt: true + nand-ecc-mode: + const: hw + +allOf: + - $ref: nand-controller.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt2701-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-step-size: + enum: [ 512, 1024 ] + nand-ecc-strength: + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, + 40, 44, 48, 52, 56, 60] + + - if: + properties: + compatible: + contains: + const: mediatek,mt2712-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-step-size: + enum: [ 512, 1024 ] + nand-ecc-strength: + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, + 40, 44, 48, 52, 56, 60, 68, 72, 80] + + - if: + properties: + compatible: + contains: + const: mediatek,mt7622-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-step-size: + const: 512 + nand-ecc-strength: + enum: [4, 6, 8, 10, 12] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ecc-engine + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt2701-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + nand-controller@1100d000 { + compatible = "mediatek,mt2701-nfc"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names = "nfi_clk", "pad_clk"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + preloader@0 { + label = "pl"; + read-only; + reg = <0x0 0x400000>; + }; + android@400000 { + label = "android"; + reg = <0x400000 0x12c00000>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml new file mode 100644 index 000000000000..505baf1e8830 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs NAND ECC engine + +maintainers: + - Xiangsheng Hou <xiangsheng.hou@mediatek.com> + +description: | + MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. + +properties: + compatible: + enum: + - mediatek,mt2701-ecc + - mediatek,mt2712-ecc + - mediatek,mt7622-ecc + - mediatek,mt7986-ecc + + reg: + items: + - description: Base physical address and size of ECC. + + interrupts: + items: + - description: ECC interrupt + + clocks: + maxItems: 1 + + clock-names: + const: nfiecc_clk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt2701-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + bch: ecc@1100e000 { + compatible = "mediatek,mt2701-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI_ECC>; + clock-names = "nfiecc_clk"; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml index 5df94953c34e..44cd4476d1d3 100644 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml @@ -15,6 +15,7 @@ description: | allOf: - $ref: "mtd.yaml#" + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt deleted file mode 100644 index 839ea2f93d04..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt +++ /dev/null @@ -1,176 +0,0 @@ -MTK SoCs NAND FLASH controller (NFC) DT binding - -This file documents the device tree bindings for MTK SoCs NAND controllers. -The functional split of the controller requires two drivers to operate: -the nand controller interface driver and the ECC engine driver. - -The hardware description for both devices must be captured as device -tree nodes. - -1) NFC NAND Controller Interface (NFI): -======================================= - -The first part of NFC is NAND Controller Interface (NFI) HW. -Required NFI properties: -- compatible: Should be one of - "mediatek,mt2701-nfc", - "mediatek,mt2712-nfc", - "mediatek,mt7622-nfc". -- reg: Base physical address and size of NFI. -- interrupts: Interrupts of NFI. -- clocks: NFI required clocks. -- clock-names: NFI clocks internal name. -- ecc-engine: Required ECC Engine node. -- #address-cells: NAND chip index, should be 1. -- #size-cells: Should be 0. - -Example: - - nandc: nfi@1100d000 { - compatible = "mediatek,mt2701-nfc"; - reg = <0 0x1100d000 0 0x1000>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names = "nfi_clk", "pad_clk"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - }; - -Platform related properties, should be set in {platform_name}.dts: -- children nodes: NAND chips. - -Children nodes properties: -- reg: Chip Select Signal, default 0. - Set as reg = <0>, <1> when need 2 CS. -Optional: -- nand-on-flash-bbt: Store BBT on NAND Flash. -- nand-ecc-mode: the NAND ecc mode (check driver for supported modes) -- nand-ecc-step-size: Number of data bytes covered by a single ECC step. - valid values: - 512 and 1024 on mt2701 and mt2712. - 512 only on mt7622. - 1024 is recommended for large page NANDs. -- nand-ecc-strength: Number of bits to correct per ECC step. - The valid values that each controller supports: - mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60. - mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80. - mt7622: 4, 6, 8, 10, 12, 14, 16. - The strength should be calculated as follows: - E = (S - F) * 8 / B - S = O / (P / Q) - E : nand-ecc-strength. - S : spare size per sector. - F : FDM size, should be in the range [1,8]. - It is used to store free oob data. - O : oob size. - P : page size. - Q : nand-ecc-step-size. - B : number of parity bits needed to correct - 1 bitflip. - According to MTK NAND controller design, - this number depends on max ecc step size - that MTK NAND controller supports. - If max ecc step size supported is 1024, - then it should be always 14. And if max - ecc step size is 512, then it should be - always 13. - If the result does not match any one of the listed - choices above, please select the smaller valid value from - the list. - (otherwise the driver will do the adjustment at runtime) -- pinctrl-names: Default NAND pin GPIO setting name. -- pinctrl-0: GPIO setting node. - -Example: - &pio { - nand_pins_default: nanddefault { - pins_dat { - pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>, - <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>, - <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>, - <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>, - <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>, - <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>, - <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>, - <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>, - <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>; - input-enable; - drive-strength = <MTK_DRIVE_8mA>; - bias-pull-up; - }; - - pins_we { - pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>; - drive-strength = <MTK_DRIVE_8mA>; - bias-pull-up = <MTK_PUPD_SET_R1R0_10>; - }; - - pins_ale { - pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>; - drive-strength = <MTK_DRIVE_8mA>; - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; - }; - }; - }; - - &nandc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_default>; - nand@0 { - reg = <0>; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - }; - }; - -NAND chip optional subnodes: -- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml - -Example: - nand@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - preloader@0 { - label = "pl"; - read-only; - reg = <0x00000000 0x00400000>; - }; - android@00400000 { - label = "android"; - reg = <0x00400000 0x12c00000>; - }; - }; - }; - -2) ECC Engine: -============== - -Required BCH properties: -- compatible: Should be one of - "mediatek,mt2701-ecc", - "mediatek,mt2712-ecc", - "mediatek,mt7622-ecc". -- reg: Base physical address and size of ECC. -- interrupts: Interrupts of ECC. -- clocks: ECC required clocks. -- clock-names: ECC clocks internal name. - -Example: - - bch: ecc@1100e000 { - compatible = "mediatek,mt2701-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_NFI_ECC>; - clock-names = "nfiecc_clk"; - }; diff --git a/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml index 9aca4e6c6047..2edc65e0e361 100644 --- a/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml +++ b/Documentation/devicetree/bindings/mtd/partitions/partitions.yaml @@ -32,7 +32,7 @@ properties: enum: [1, 2] patternProperties: - "partition(-.+|@[0-9a-f]+)": + "^partition(-.+|@[0-9a-f]+)$": $ref: partition.yaml required: diff --git a/Documentation/devicetree/bindings/net/amlogic,g12a-mdio-mux.yaml b/Documentation/devicetree/bindings/net/amlogic,g12a-mdio-mux.yaml new file mode 100644 index 000000000000..ec5c038ce6a0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/amlogic,g12a-mdio-mux.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MDIO bus multiplexer/glue of Amlogic G12a SoC family + +description: + This is a special case of a MDIO bus multiplexer. It allows to choose between + the internal mdio bus leading to the embedded 10/100 PHY or the external + MDIO bus. + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: mdio-mux.yaml# + +properties: + compatible: + const: amlogic,g12a-mdio-mux + + reg: + maxItems: 1 + + clocks: + items: + - description: peripheral clock + - description: platform crytal + - description: SoC 50MHz MPLL + + clock-names: + items: + - const: pclk + - const: clkin0 + - const: clkin1 + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + mdio-multiplexer@4c000 { + compatible = "amlogic,g12a-mdio-mux"; + reg = <0x4c000 0xa4>; + clocks = <&clkc_eth_phy>, <&xtal>, <&clkc_mpll>; + clock-names = "pclk", "clkin0", "clkin1"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@8 { + compatible = "ethernet-phy-id0180.3301", + "ethernet-phy-ieee802.3-c22"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <8>; + max-speed = <100>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/amlogic,gxl-mdio-mux.yaml b/Documentation/devicetree/bindings/net/amlogic,gxl-mdio-mux.yaml new file mode 100644 index 000000000000..27ae004dbea0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/amlogic,gxl-mdio-mux.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic GXL MDIO bus multiplexer + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +description: + This is a special case of a MDIO bus multiplexer. It allows to choose between + the internal mdio bus leading to the embedded 10/100 PHY or the external + MDIO bus on the Amlogic GXL SoC family. + +allOf: + - $ref: mdio-mux.yaml# + +properties: + compatible: + const: amlogic,gxl-mdio-mux + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + eth_phy_mux: mdio@558 { + compatible = "amlogic,gxl-mdio-mux"; + reg = <0x558 0xc>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&refclk>; + clock-names = "ref"; + mdio-parent-bus = <&mdio0>; + + external_mdio: mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + internal_mdio: mdio@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/asix,ax88796c.yaml b/Documentation/devicetree/bindings/net/asix,ax88796c.yaml index 699ebf452479..164d1ff9e83c 100644 --- a/Documentation/devicetree/bindings/net/asix,ax88796c.yaml +++ b/Documentation/devicetree/bindings/net/asix,ax88796c.yaml @@ -19,6 +19,7 @@ description: | allOf: - $ref: ethernet-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml properties: compatible: @@ -39,8 +40,8 @@ properties: it should be marked GPIO_ACTIVE_LOW. maxItems: 1 + controller-data: true local-mac-address: true - mac-address: true required: diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml index 1eb98c9a1a26..d3f45d29fa0a 100644 --- a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml +++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml @@ -30,13 +30,17 @@ properties: - items: - enum: + - renesas,r8a779a0-canfd # R-Car V3U + - renesas,r8a779g0-canfd # R-Car V4H + - const: renesas,rcar-gen4-canfd # R-Car Gen4 + + - items: + - enum: - renesas,r9a07g043-canfd # RZ/G2UL and RZ/Five - renesas,r9a07g044-canfd # RZ/G2{L,LC} - renesas,r9a07g054-canfd # RZ/V2L - const: renesas,rzg2l-canfd # RZ/G2L family - - const: renesas,r8a779a0-canfd # R-Car V3U - reg: maxItems: 1 @@ -60,7 +64,7 @@ properties: $ref: /schemas/types.yaml#/definitions/flag description: The controller can operate in either CAN FD only mode (default) or - Classical CAN only mode. The mode is global to both the channels. + Classical CAN only mode. The mode is global to all channels. Specify this property to put the controller in Classical CAN only mode. assigned-clocks: @@ -80,6 +84,10 @@ patternProperties: The controller supports multiple channels and each is represented as a child node. Each channel can be enabled/disabled individually. + properties: + phys: + maxItems: 1 + additionalProperties: false required: @@ -159,7 +167,7 @@ allOf: properties: compatible: contains: - const: renesas,r8a779a0-canfd + const: renesas,rcar-gen4-canfd then: patternProperties: "^channel[2-7]$": false diff --git a/Documentation/devicetree/bindings/net/dsa/arrow,xrs700x.yaml b/Documentation/devicetree/bindings/net/dsa/arrow,xrs700x.yaml index 2a6d126606ca..9565a7402146 100644 --- a/Documentation/devicetree/bindings/net/dsa/arrow,xrs700x.yaml +++ b/Documentation/devicetree/bindings/net/dsa/arrow,xrs700x.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Arrow SpeedChips XRS7000 Series Switch allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports maintainers: - George McCollister <george.mccollister@gmail.com> diff --git a/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml b/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml index 1219b830b1a4..5bef4128d175 100644 --- a/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml +++ b/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml @@ -66,7 +66,7 @@ required: - reg allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml b/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml index d159ac78cec1..eed16e216fb6 100644 --- a/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml +++ b/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml @@ -85,11 +85,16 @@ properties: ports: type: object - properties: - brcm,use-bcm-hdr: - description: if present, indicates that the switch port has Broadcom - tags enabled (per-packet metadata) - type: boolean + patternProperties: + '^port@[0-9a-f]$': + $ref: dsa-port.yaml# + unevaluatedProperties: false + + properties: + brcm,use-bcm-hdr: + description: if present, indicates that the switch port has Broadcom + tags enabled (per-packet metadata) + type: boolean required: - reg diff --git a/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml b/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml index b173fceb8998..480120469953 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ethernet Switch port +title: Generic DSA Switch Port maintainers: - Andrew Lunn <andrew@lunn.ch> - Florian Fainelli <f.fainelli@gmail.com> - - Vivien Didelot <vivien.didelot@gmail.com> + - Vladimir Oltean <olteanv@gmail.com> description: - Ethernet switch port Description + A DSA switch port is a component of a switch that manages one MAC, and can + pass Ethernet frames. It can act as a stanadard Ethernet switch port, or have + DSA-specific functionality. -allOf: - - $ref: /schemas/net/ethernet-controller.yaml# +$ref: /schemas/net/ethernet-switch-port.yaml# properties: reg: @@ -58,25 +59,6 @@ properties: - rtl8_4t - seville - phy-handle: true - - phy-mode: true - - fixed-link: true - - mac-address: true - - sfp: true - - managed: true - - rx-internal-delay-ps: true - - tx-internal-delay-ps: true - -required: - - reg - # CPU and DSA ports must have phylink-compatible link descriptions if: oneOf: diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index 5469ae8a4389..8d971813bab6 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -9,7 +9,7 @@ title: Ethernet Switch maintainers: - Andrew Lunn <andrew@lunn.ch> - Florian Fainelli <f.fainelli@gmail.com> - - Vivien Didelot <vivien.didelot@gmail.com> + - Vladimir Oltean <olteanv@gmail.com> description: This binding represents Ethernet Switches which have a dedicated CPU @@ -18,10 +18,9 @@ description: select: false -properties: - $nodename: - pattern: "^(ethernet-)?switch(@.*)?$" +$ref: /schemas/net/ethernet-switch.yaml# +properties: dsa,member: minItems: 2 maxItems: 2 @@ -32,30 +31,28 @@ properties: (single device hanging off a CPU port) must not specify this property $ref: /schemas/types.yaml#/definitions/uint32-array -patternProperties: - "^(ethernet-)?ports$": - type: object - properties: - '#address-cells': - const: 1 - '#size-cells': - const: 0 +additionalProperties: true + +$defs: + ethernet-ports: + description: A DSA switch without any extra port properties + $ref: '#/' patternProperties: - "^(ethernet-)?port@[0-9]+$": + "^(ethernet-)?ports$": type: object - description: Ethernet switch ports - - $ref: dsa-port.yaml# - - unevaluatedProperties: false - -oneOf: - - required: - - ports - - required: - - ethernet-ports - -additionalProperties: true + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^(ethernet-)?port@[0-9]+$": + description: Ethernet switch ports + $ref: dsa-port.yaml# + unevaluatedProperties: false ... diff --git a/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml b/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml index 447589b01e8e..4021b054f684 100644 --- a/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml +++ b/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Hirschmann Hellcreek TSN Switch allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports maintainers: - Andrew Lunn <andrew@lunn.ch> diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index f2e9ff3f580b..449ee0735012 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -24,56 +24,46 @@ description: | There is only the standalone version of MT7531. - Port 5 on MT7530 has got various ways of configuration. - - For standalone MT7530: + Port 5 on MT7530 has got various ways of configuration: - Port 5 can be used as a CPU port. - - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC - which port 5 is wired to. Usually used for connecting the wan port - directly to the CPU to achieve 2 Gbps routing in total. + - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, + the gmac of the SoC which is wired to port 5 can connect to the PHY. + This is usually used for connecting the wan port directly to the CPU to + achieve 2 Gbps routing in total. - The driver looks up the reg on the ethernet-phy node which the phy-handle - property refers to on the gmac node to mux the specified phy. + The driver looks up the reg on the ethernet-phy node, which the phy-handle + property on the gmac node refers to, to mux the specified phy. The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the - compatible string and the reg must be 1. So, for now, only gmac1 of an + compatible string and the reg must be 1. So, for now, only gmac1 of a MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. - Check out example 5 for a similar configuration. - - - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. - Check out example 7 for a similar configuration. - - For multi-chip module MT7530: - - - Port 5 can be used as a CPU port. - - - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. - Usually used for connecting the wan port directly to the CPU to achieve 2 - Gbps routing in total. - - The driver looks up the reg on the ethernet-phy node which the phy-handle - property refers to on the gmac node to mux the specified phy. For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 5. - - In case of an external phy wired to gmac1 of the SoC, port 5 must not be - enabled. + - For the multi-chip module MT7530, in case of an external phy wired to + gmac1 of the SoC, port 5 must not be enabled. In case of muxing PHY 0 or 4, the external phy must not be enabled. For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 6. - - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. - The external phy must be wired TX to TX to gmac1 of the SoC for this to - work. Ubiquiti EdgeRouter X SFP is wired this way. + - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. - Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. + For the multi-chip module MT7530, the external phy must be wired TX to TX + to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired + this way. + + For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the + external phy is connected TX to TX. For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. + Check out example 7. properties: @@ -157,9 +147,6 @@ patternProperties: patternProperties: "^(ethernet-)?port@[0-9]+$": type: object - description: Ethernet switch ports - - unevaluatedProperties: false properties: reg: @@ -168,7 +155,6 @@ patternProperties: for user ports. allOf: - - $ref: dsa-port.yaml# - if: required: [ ethernet ] then: @@ -238,7 +224,7 @@ $defs: - sgmii allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports - if: required: - mediatek,mcm @@ -605,7 +591,7 @@ examples: label = "lan4"; }; - /* Commented out, phy4 is muxed to gmac1. + /* Commented out, phy4 is connected to gmac1. port@4 { reg = <4>; label = "wan"; diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index 4da75b1f9533..a4b53434c85c 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -11,7 +11,7 @@ maintainers: - Woojung Huh <Woojung.Huh@microchip.com> allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml index b34de303966b..8d7e878b84dc 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml @@ -10,7 +10,7 @@ maintainers: - UNGLinuxDriver@microchip.com allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports properties: compatible: diff --git a/Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml b/Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml index 347a0e1b3d3f..fe02d05196e4 100644 --- a/Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml @@ -78,7 +78,7 @@ required: - reg allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml index df98a16e4e75..9a64ed658745 100644 --- a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml +++ b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml @@ -13,7 +13,7 @@ description: depends on the SPI bus master driver. allOf: - - $ref: "dsa.yaml#" + - $ref: dsa.yaml#/$defs/ethernet-ports - $ref: /schemas/spi/spi-peripheral-props.yaml# maintainers: diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.yaml b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml index 978162df51f7..389892592aac 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.yaml +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml @@ -66,15 +66,11 @@ properties: With the legacy mapping the reg corresponding to the internal mdio is the switch reg with an offset of -1. +$ref: "dsa.yaml#" + patternProperties: "^(ethernet-)?ports$": type: object - properties: - '#address-cells': - const: 1 - '#size-cells': - const: 0 - patternProperties: "^(ethernet-)?port@[0-6]$": type: object @@ -116,7 +112,7 @@ required: - compatible - reg -additionalProperties: true +unevaluatedProperties: false examples: - | @@ -148,8 +144,6 @@ examples: switch@10 { compatible = "qca,qca8337"; - #address-cells = <1>; - #size-cells = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; reg = <0x10>; @@ -209,8 +203,6 @@ examples: switch@10 { compatible = "qca,qca8337"; - #address-cells = <1>; - #size-cells = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; reg = <0x10>; diff --git a/Documentation/devicetree/bindings/net/dsa/realtek.yaml b/Documentation/devicetree/bindings/net/dsa/realtek.yaml index 1a7d45a8ad66..cfd69c2604ea 100644 --- a/Documentation/devicetree/bindings/net/dsa/realtek.yaml +++ b/Documentation/devicetree/bindings/net/dsa/realtek.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Realtek switches for unmanaged switches allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml index 0a0d62b6c00e..833d2f68daa1 100644 --- a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml @@ -14,7 +14,7 @@ description: | handles 4 ports + 1 CPU management port. allOf: - - $ref: dsa.yaml# + - $ref: dsa.yaml#/$defs/ethernet-ports properties: compatible: diff --git a/Documentation/devicetree/bindings/net/ethernet-switch-port.yaml b/Documentation/devicetree/bindings/net/ethernet-switch-port.yaml new file mode 100644 index 000000000000..d5cf7e40e3c3 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet-switch-port.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-switch-port.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Ethernet Switch Port + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Florian Fainelli <f.fainelli@gmail.com> + - Vladimir Oltean <olteanv@gmail.com> + +description: + An Ethernet switch port is a component of a switch that manages one MAC, and + can pass Ethernet frames. + +$ref: ethernet-controller.yaml# + +properties: + reg: + description: Port number + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/net/ethernet-switch.yaml b/Documentation/devicetree/bindings/net/ethernet-switch.yaml new file mode 100644 index 000000000000..a04f8ef744aa --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet-switch.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Ethernet Switch + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Florian Fainelli <f.fainelli@gmail.com> + - Vladimir Oltean <olteanv@gmail.com> + +description: + Ethernet switches are multi-port Ethernet controllers. Each port has + its own number and is represented as its own Ethernet controller. + The minimum required functionality is to pass packets to software. + They may or may not be able to forward packets automonously between + ports. + +select: false + +properties: + $nodename: + pattern: "^(ethernet-)?switch(@.*)?$" + +patternProperties: + "^(ethernet-)?ports$": + type: object + unevaluatedProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^(ethernet-)?port@[0-9]+$": + type: object + description: Ethernet switch ports + +oneOf: + - required: + - ports + - required: + - ethernet-ports + +additionalProperties: true + +$defs: + base: + description: An ethernet switch without any extra port properties + $ref: '#/' + + patternProperties: + "^(ethernet-)?port@[0-9]+$": + description: Ethernet switch ports + $ref: ethernet-switch-port.yaml# + unevaluatedProperties: false + +... diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml index 77e5f32cb62f..e6f2045f05de 100644 --- a/Documentation/devicetree/bindings/net/fsl,fec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml @@ -51,6 +51,7 @@ properties: - fsl,imx8mm-fec - fsl,imx8mn-fec - fsl,imx8mp-fec + - fsl,imx93-fec - const: fsl,imx8mq-fec - const: fsl,imx6sx-fec - items: diff --git a/Documentation/devicetree/bindings/net/maxlinear,gpy2xx.yaml b/Documentation/devicetree/bindings/net/maxlinear,gpy2xx.yaml new file mode 100644 index 000000000000..d71fa9de2b64 --- /dev/null +++ b/Documentation/devicetree/bindings/net/maxlinear,gpy2xx.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/maxlinear,gpy2xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MaxLinear GPY2xx PHY + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Michael Walle <michael@walle.cc> + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + maxlinear,use-broken-interrupts: + description: | + Interrupts are broken on some GPY2xx PHYs in that they keep the + interrupt line asserted even after the interrupt status register is + cleared. Thus it is blocking the interrupt line which is usually bad + for shared lines. By default interrupts are disabled for this PHY and + polling mode is used. If one can live with the consequences, this + property can be used to enable interrupt handling. + + Affected PHYs (as far as known) are GPY215B and GPY215C. + type: boolean + +dependencies: + maxlinear,use-broken-interrupts: [ interrupts ] + +unevaluatedProperties: false + +examples: + - | + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&intc 0>; + maxlinear,use-broken-interrupts; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/mdio-mux-meson-g12a.txt b/Documentation/devicetree/bindings/net/mdio-mux-meson-g12a.txt deleted file mode 100644 index 3a96cbed9294..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-meson-g12a.txt +++ /dev/null @@ -1,48 +0,0 @@ -Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family. - -This is a special case of a MDIO bus multiplexer. It allows to choose between -the internal mdio bus leading to the embedded 10/100 PHY or the external -MDIO bus. - -Required properties in addition to the generic multiplexer properties: -- compatible : amlogic,g12a-mdio-mux -- reg: physical address and length of the multiplexer/glue registers -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "pclk" : peripheral clock. - * "clkin0" : platform crytal - * "clkin1" : SoC 50MHz MPLL - -Example : - -mdio_mux: mdio-multiplexer@4c000 { - compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x4c000 0x0 0xa4>; - clocks = <&clkc CLKID_ETH_PHY>, - <&xtal>, - <&clkc CLKID_MPLL_5OM>; - clock-names = "pclk", "clkin0", "clkin1"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - - ext_mdio: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - int_mdio: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_ephy: ethernet-phy@8 { - compatible = "ethernet-phy-id0180.3301", - "ethernet-phy-ieee802.3-c22"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <8>; - max-speed = <100>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt index df9e844dd6bc..2681168777a1 100644 --- a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt +++ b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt @@ -158,6 +158,7 @@ KSZ9031: no link will be established. KSZ9131: +LAN8841: All skew control options are specified in picoseconds. The increment step is 100ps. Unlike KSZ9031, the values represent picoseccond delays. diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml new file mode 100644 index 000000000000..157e3bbcaf6f --- /dev/null +++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MotorComm yt8xxx Ethernet PHY + +maintainers: + - Frank Sae <frank.sae@motor-comm.com> + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + enum: + - ethernet-phy-id4f51.e91a + - ethernet-phy-id4f51.e91b + + rx-internal-delay-ps: + description: | + RGMII RX Clock Delay used only when PHY operates in RGMII mode with + internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, + 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800, + 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ] + default: 1950 + + tx-internal-delay-ps: + description: | + RGMII TX Clock Delay used only when PHY operates in RGMII mode with + internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800, + 1950, 2100, 2250 ] + default: 1950 + + motorcomm,clk-out-frequency-hz: + description: clock output on clock output pin. + enum: [0, 25000000, 125000000] + default: 0 + + motorcomm,keep-pll-enabled: + description: | + If set, keep the PLL enabled even if there is no link. Useful if you + want to use the clock output without an ethernet link. + type: boolean + + motorcomm,auto-sleep-disabled: + description: | + If set, PHY will not enter sleep mode and close AFE after unplug cable + for a timer. + type: boolean + + motorcomm,tx-clk-adj-enabled: + description: | + This configuration is mainly to adapt to VF2 with JH7110 SoC. + Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk. + type: boolean + + motorcomm,tx-clk-10-inverted: + description: | + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII + Transmit PHY Clock delay train configuration when speed is 10Mbps. + type: boolean + + motorcomm,tx-clk-100-inverted: + description: | + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII + Transmit PHY Clock delay train configuration when speed is 100Mbps. + type: boolean + + motorcomm,tx-clk-1000-inverted: + description: | + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII + Transmit PHY Clock delay train configuration when speed is 1000Mbps. + type: boolean + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy-mode = "rgmii-id"; + ethernet-phy@4 { + /* Only needed to make DT lint tools work. Do not copy/paste + * into real DTS files. + */ + compatible = "ethernet-phy-id4f51.e91a"; + + reg = <4>; + rx-internal-delay-ps = <2100>; + tx-internal-delay-ps = <150>; + motorcomm,clk-out-frequency-hz = <0>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + }; + }; + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy-mode = "rgmii"; + ethernet-phy@5 { + /* Only needed to make DT lint tools work. Do not copy/paste + * into real DTS files. + */ + compatible = "ethernet-phy-id4f51.e91a"; + + reg = <5>; + motorcomm,clk-out-frequency-hz = <125000000>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + }; + }; diff --git a/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml b/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml index ee0a504bdb24..8ee2c7d7ff42 100644 --- a/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml +++ b/Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml @@ -18,14 +18,52 @@ description: | packets using CPU. Additionally, PTP is supported as well as FDMA for faster packet extraction/injection. -properties: - $nodename: - pattern: "^switch@[0-9a-f]+$" +allOf: + - if: + properties: + compatible: + const: mscc,vsc7514-switch + then: + $ref: ethernet-switch.yaml# + required: + - interrupts + - interrupt-names + properties: + reg: + minItems: 21 + reg-names: + minItems: 21 + ethernet-ports: + patternProperties: + "^port@[0-9a-f]+$": + $ref: ethernet-switch-port.yaml# + unevaluatedProperties: false + + - if: + properties: + compatible: + const: mscc,vsc7512-switch + then: + $ref: /schemas/net/dsa/dsa.yaml# + properties: + reg: + maxItems: 20 + reg-names: + maxItems: 20 + ethernet-ports: + patternProperties: + "^port@[0-9a-f]+$": + $ref: /schemas/net/dsa/dsa-port.yaml# + unevaluatedProperties: false +properties: compatible: - const: mscc,vsc7514-switch + enum: + - mscc,vsc7512-switch + - mscc,vsc7514-switch reg: + minItems: 20 items: - description: system target - description: rewriter target @@ -50,6 +88,7 @@ properties: - description: fdma target reg-names: + minItems: 20 items: - const: sys - const: rew @@ -87,59 +126,16 @@ properties: - const: xtr - const: fdma - ethernet-ports: - type: object - - properties: - '#address-cells': - const: 1 - '#size-cells': - const: 0 - - additionalProperties: false - - patternProperties: - "^port@[0-9a-f]+$": - type: object - description: Ethernet ports handled by the switch - - $ref: ethernet-controller.yaml# - - unevaluatedProperties: false - - properties: - reg: - description: Switch port number - - phy-handle: true - - phy-mode: true - - fixed-link: true - - mac-address: true - - required: - - reg - - phy-mode - - oneOf: - - required: - - phy-handle - - required: - - fixed-link - required: - compatible - reg - reg-names - - interrupts - - interrupt-names - ethernet-ports -additionalProperties: false +unevaluatedProperties: false examples: + # VSC7514 (Switchdev) - | switch@1010000 { compatible = "mscc,vsc7514-switch"; @@ -187,5 +183,51 @@ examples: }; }; }; + # VSC7512 (DSA) + - | + ethernet-switch@1{ + compatible = "mscc,vsc7512-switch"; + reg = <0x71010000 0x10000>, + <0x71030000 0x10000>, + <0x71080000 0x100>, + <0x710e0000 0x10000>, + <0x711e0000 0x100>, + <0x711f0000 0x100>, + <0x71200000 0x100>, + <0x71210000 0x100>, + <0x71220000 0x100>, + <0x71230000 0x100>, + <0x71240000 0x100>, + <0x71250000 0x100>, + <0x71260000 0x100>, + <0x71270000 0x100>, + <0x71280000 0x100>, + <0x71800000 0x80000>, + <0x71880000 0x10000>, + <0x71040000 0x10000>, + <0x71050000 0x10000>, + <0x71060000 0x10000>; + reg-names = "sys", "rew", "qs", "ptp", "port0", "port1", + "port2", "port3", "port4", "port5", "port6", + "port7", "port8", "port9", "port10", "qsys", + "ana", "s0", "s1", "s2"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ethernet = <&mac_sw>; + phy-handle = <&phy0>; + phy-mode = "internal"; + }; + port@1 { + reg = <1>; + phy-handle = <&phy1>; + phy-mode = "internal"; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml index 04df496af7e6..63409cbff5ad 100644 --- a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NXP i.MX8 DWMAC glue layer +title: NXP i.MX8/9 DWMAC glue layer maintainers: - Clark Wang <xiaoning.wang@nxp.com> @@ -19,6 +19,7 @@ select: enum: - nxp,imx8mp-dwmac-eqos - nxp,imx8dxl-dwmac-eqos + - nxp,imx93-dwmac-eqos required: - compatible @@ -32,6 +33,7 @@ properties: - enum: - nxp,imx8mp-dwmac-eqos - nxp,imx8dxl-dwmac-eqos + - nxp,imx93-dwmac-eqos - const: snps,dwmac-5.10a clocks: diff --git a/Documentation/devicetree/bindings/net/rfkill-gpio.yaml b/Documentation/devicetree/bindings/net/rfkill-gpio.yaml new file mode 100644 index 000000000000..9630c8466fac --- /dev/null +++ b/Documentation/devicetree/bindings/net/rfkill-gpio.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/rfkill-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO controlled rfkill switch + +maintainers: + - Johannes Berg <johannes@sipsolutions.net> + - Philipp Zabel <p.zabel@pengutronix.de> + +properties: + compatible: + const: rfkill-gpio + + label: + description: rfkill switch name, defaults to node name + + radio-type: + description: rfkill radio type + enum: + - bluetooth + - fm + - gps + - nfc + - ultrawideband + - wimax + - wlan + - wwan + + shutdown-gpios: + maxItems: 1 + +required: + - compatible + - radio-type + - shutdown-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml index 42fb72b6909d..04936632fcbb 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -49,11 +49,11 @@ properties: - rockchip,rk3368-gmac - rockchip,rk3399-gmac - rockchip,rv1108-gmac - - rockchip,rv1126-gmac - items: - enum: - rockchip,rk3568-gmac - rockchip,rk3588-gmac + - rockchip,rv1126-gmac - const: snps,dwmac-4.20a clocks: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index e88a86623fce..16b7d2904696 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -552,7 +552,7 @@ required: dependencies: snps,reset-active-low: ["snps,reset-gpio"] - snps,reset-delay-us: ["snps,reset-gpio"] + snps,reset-delays-us: ["snps,reset-gpio"] allOf: - $ref: "ethernet-controller.yaml#" diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index 821974815dec..900063411a20 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -57,6 +57,7 @@ properties: - ti,am654-cpsw-nuss - ti,j7200-cpswxg-nuss - ti,j721e-cpsw-nuss + - ti,j721e-cpswxg-nuss - ti,am642-cpsw-nuss reg: @@ -111,7 +112,7 @@ properties: const: 0 patternProperties: - "^port@[1-4]$": + "^port@[1-8]$": type: object description: CPSWxG NUSS external ports @@ -121,7 +122,7 @@ properties: properties: reg: minimum: 1 - maximum: 4 + maximum: 8 description: CPSW port number phys: @@ -186,12 +187,36 @@ allOf: properties: compatible: contains: - const: ti,j7200-cpswxg-nuss + const: ti,j721e-cpswxg-nuss then: properties: ethernet-ports: patternProperties: - "^port@[3-4]$": false + "^port@[5-8]$": false + "^port@[1-4]$": + properties: + reg: + minimum: 1 + maximum: 4 + + - if: + not: + properties: + compatible: + contains: + enum: + - ti,j721e-cpswxg-nuss + - ti,j7200-cpswxg-nuss + then: + properties: + ethernet-ports: + patternProperties: + "^port@[3-8]$": false + "^port@[1-2]$": + properties: + reg: + minimum: 1 + maximum: 2 additionalProperties: false diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml index 6230f576134b..3e910d3b24a0 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml @@ -93,6 +93,14 @@ properties: description: Number of timestamp Generator function outputs (TS_GENFx) + ti,pps: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + description: | + The pair of HWx_TS_PUSH input and TS_GENFy output indexes used for + PPS events generation. Platform/board specific. + refclk-mux: type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml b/Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml index 5557676e9d4b..0ea84d6fe73e 100644 --- a/Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml +++ b/Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml @@ -29,15 +29,15 @@ additionalProperties: false examples: - | - mmc { - #address-cells = <1>; - #size-cells = <0>; - - wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; - }; + mmc { + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml b/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml index e68ed9423150..d89f7a3f88a7 100644 --- a/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml +++ b/Documentation/devicetree/bindings/net/wireless/ieee80211.yaml @@ -1,6 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - %YAML 1.2 --- $id: http://devicetree.org/schemas/net/wireless/ieee80211.yaml# diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt index 9bf9bbac16e2..cdc303caf5f4 100644 --- a/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt +++ b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt @@ -1,4 +1,4 @@ -Marvell 8787/8897/8997 (sd8787/sd8897/sd8997/pcie8997) SDIO/PCIE devices +Marvell 8787/8897/8978/8997 (sd8787/sd8897/sd8978/sd8997/pcie8997) SDIO/PCIE devices ------ This node provides properties for controlling the Marvell SDIO/PCIE wireless device. @@ -10,7 +10,9 @@ Required properties: - compatible : should be one of the following: * "marvell,sd8787" * "marvell,sd8897" + * "marvell,sd8978" * "marvell,sd8997" + * "nxp,iw416" * "pci11ab,2b42" * "pci1b4b,2b42" diff --git a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml index f0c78f994491..7d526ff53fb7 100644 --- a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml +++ b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml @@ -1,6 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - %YAML 1.2 --- $id: http://devicetree.org/schemas/net/wireless/mediatek,mt76.yaml# diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml index 556eb523606a..7d5f982a3d09 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml @@ -1,6 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - %YAML 1.2 --- $id: http://devicetree.org/schemas/net/wireless/qcom,ath11k.yaml# @@ -21,6 +20,7 @@ properties: - qcom,ipq8074-wifi - qcom,ipq6018-wifi - qcom,wcn6750-wifi + - qcom,ipq5018-wifi reg: maxItems: 1 @@ -262,10 +262,10 @@ allOf: examples: - | - q6v5_wcss: q6v5_wcss@CD00000 { + q6v5_wcss: remoteproc@cd00000 { compatible = "qcom,ipq8074-wcss-pil"; - reg = <0xCD00000 0x4040>, - <0x4AB000 0x20>; + reg = <0xcd00000 0x4040>, + <0x4ab000 0x20>; reg-names = "qdsp6", "rmb"; }; @@ -386,7 +386,7 @@ examples: #address-cells = <2>; #size-cells = <2>; - qcn9074_0: qcn9074_0@51100000 { + qcn9074_0: wifi@51100000 { no-map; reg = <0x0 0x51100000 0x0 0x03500000>; }; @@ -463,6 +463,6 @@ examples: qcom,smem-states = <&wlan_smp2p_out 0>; qcom,smem-state-names = "wlan-smp2p-out"; wifi-firmware { - iommus = <&apps_smmu 0x1c02 0x1>; + iommus = <&apps_smmu 0x1c02 0x1>; }; }; diff --git a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml index 583db5d42226..84e5659e50ef 100644 --- a/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml @@ -2,7 +2,6 @@ # Copyright (c) 2020, Silicon Laboratories, Inc. %YAML 1.2 --- - $id: http://devicetree.org/schemas/net/wireless/silabs,wfx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml index e31456730e9f..f799a1e52173 100644 --- a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml +++ b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml @@ -90,47 +90,47 @@ examples: // For wl12xx family: spi1 { - #address-cells = <1>; - #size-cells = <0>; - - wlcore1: wlcore@1 { - compatible = "ti,wl1271"; - reg = <1>; - spi-max-frequency = <48000000>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - vwlan-supply = <&vwlan_fixed>; - clock-xtal; - ref-clock-frequency = <38400000>; - }; + #address-cells = <1>; + #size-cells = <0>; + + wlcore1: wlcore@1 { + compatible = "ti,wl1271"; + reg = <1>; + spi-max-frequency = <48000000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + vwlan-supply = <&vwlan_fixed>; + clock-xtal; + ref-clock-frequency = <38400000>; + }; }; // For wl18xx family: spi2 { - #address-cells = <1>; - #size-cells = <0>; - - wlcore2: wlcore@0 { - compatible = "ti,wl1835"; - reg = <0>; - spi-max-frequency = <48000000>; - interrupts = <27 IRQ_TYPE_EDGE_RISING>; - vwlan-supply = <&vwlan_fixed>; - }; + #address-cells = <1>; + #size-cells = <0>; + + wlcore2: wlcore@0 { + compatible = "ti,wl1835"; + reg = <0>; + spi-max-frequency = <48000000>; + interrupts = <27 IRQ_TYPE_EDGE_RISING>; + vwlan-supply = <&vwlan_fixed>; + }; }; // SDIO example: mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - - wlcore3: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - }; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + + wlcore3: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; }; diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 8e89b15b535f..2173fe82317d 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -19,16 +19,21 @@ properties: - qcom,apq8064-qfprom - qcom,apq8084-qfprom - qcom,ipq8064-qfprom - - qcom,msm8974-qfprom + - qcom,ipq8074-qfprom - qcom,msm8916-qfprom + - qcom,msm8974-qfprom + - qcom,msm8976-qfprom - qcom,msm8996-qfprom - qcom,msm8998-qfprom - qcom,qcs404-qfprom - qcom,sc7180-qfprom - qcom,sc7280-qfprom - qcom,sdm630-qfprom + - qcom,sdm670-qfprom - qcom,sdm845-qfprom - qcom,sm6115-qfprom + - qcom,sm8150-qfprom + - qcom,sm8250-qfprom - const: qcom,qfprom reg: diff --git a/Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml b/Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml index 73a0c658dbfd..dc790d2cd9f0 100644 --- a/Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml @@ -31,65 +31,56 @@ unevaluatedProperties: false examples: - | - // The UniPhier eFuse should be a subnode of a "soc-glue" node. + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; - soc-glue@5f900000 { - compatible = "simple-mfd"; + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x68>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x5f900000 0x2000>; - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; + /* Data cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - usb_rterm0: trim@54,4 { - reg = <0x54 1>; - bits = <4 2>; - }; - usb_rterm1: trim@55,4 { - reg = <0x55 1>; - bits = <4 2>; - }; - usb_rterm2: trim@58,4 { - reg = <0x58 1>; - bits = <4 2>; - }; - usb_rterm3: trim@59,4 { - reg = <0x59 1>; - bits = <4 2>; - }; - usb_sel_t0: trim@54,0 { - reg = <0x54 1>; - bits = <0 4>; - }; - usb_sel_t1: trim@55,0 { - reg = <0x55 1>; - bits = <0 4>; - }; - usb_sel_t2: trim@58,0 { - reg = <0x58 1>; - bits = <0 4>; - }; - usb_sel_t3: trim@59,0 { - reg = <0x59 1>; - bits = <0 4>; - }; - usb_hs_i0: trim@56,0 { - reg = <0x56 1>; - bits = <0 4>; - }; - usb_hs_i2: trim@5a,0 { - reg = <0x5a 1>; - bits = <0 4>; - }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; }; }; diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index 60cf3cbde4c5..bbbad31ae4ca 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -50,12 +50,22 @@ patternProperties: opp-supported-hw: description: | A single 32 bit bitmap value, representing compatible HW. - Bitmap: + Bitmap for MSM8996 format: 0: MSM8996, speedbin 0 1: MSM8996, speedbin 1 2: MSM8996, speedbin 2 - 3-31: unused - maximum: 0x7 + 3: MSM8996, speedbin 3 + 4-31: unused + + Bitmap for MSM8996SG format (speedbin shifted of 4 left): + 0-3: unused + 4: MSM8996SG, speedbin 0 + 5: MSM8996SG, speedbin 1 + 6: MSM8996SG, speedbin 2 + 7-31: unused + enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, + 0x9, 0xd, 0xe, 0xf, + 0x10, 0x20, 0x30, 0x70] clock-latency-ns: true @@ -106,6 +116,7 @@ examples: L2_0: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -140,6 +151,7 @@ examples: L2_1: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml index b9ce2e099ce9..a30ef93213c0 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml @@ -30,7 +30,9 @@ patternProperties: this OPP node. Sometimes several corners/levels shares a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, min uV, and max uV. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 required: - opp-level diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index bad980902f66..f13f87fddb3d 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -24,6 +24,9 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie + - fsl,imx8mm-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep reg: items: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 8d7eb51edcb4..89cfdee4b89f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -47,8 +47,10 @@ properties: enable registers $ref: "/schemas/types.yaml#/definitions/phandle-array" items: - minItems: 3 - maxItems: 3 + - items: + - description: Syscon to TCSR system registers + - description: Perst enable offset + - description: Perst separation enable offset interrupts: items: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a5859bb3dc28..fb32c43dd12d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -16,25 +16,31 @@ description: | properties: compatible: - enum: - - qcom,pcie-ipq8064 - - qcom,pcie-ipq8064-v2 - - qcom,pcie-apq8064 - - qcom,pcie-apq8084 - - qcom,pcie-msm8996 - - qcom,pcie-ipq4019 - - qcom,pcie-ipq8074 - - qcom,pcie-qcs404 - - qcom,pcie-sa8540p - - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - - qcom,pcie-sdm845 - - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - - qcom,pcie-ipq6018 + oneOf: + - enum: + - qcom,pcie-apq8064 + - qcom,pcie-apq8084 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq6018 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064-v2 + - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 + - qcom,pcie-msm8996 + - qcom,pcie-qcs404 + - qcom,pcie-sa8540p + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sc8280xp + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8350 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + - items: + - const: qcom,pcie-msm8998 + - const: qcom,pcie-msm8996 reg: minItems: 4 @@ -153,6 +159,7 @@ allOf: contains: enum: - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 then: properties: reg: @@ -195,6 +202,7 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 then: @@ -312,27 +320,17 @@ allOf: enum: - qcom,pcie-msm8996 then: - oneOf: - - properties: - clock-names: - items: - - const: pipe # Pipe Clock driving internal logic - - const: aux # Auxiliary (AUX) clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - properties: - clock-names: - items: - - const: pipe # Pipe Clock driving internal logic - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: cfg # Configuration clock - - const: aux # Auxiliary (AUX) clock properties: clocks: minItems: 5 maxItems: 5 + clock-names: + items: + - const: pipe # Pipe Clock driving internal logic + - const: aux # Auxiliary (AUX) clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock resets: false reset-names: false @@ -373,6 +371,7 @@ allOf: contains: enum: - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 then: properties: clocks: @@ -555,6 +554,35 @@ allOf: compatible: contains: enum: + - qcom,pcie-sm8350 + then: + properties: + clocks: + minItems: 8 + maxItems: 9 + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: - qcom,pcie-sm8450-pcie0 then: properties: @@ -664,6 +692,7 @@ allOf: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 then: required: @@ -692,6 +721,7 @@ allOf: - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 + - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 then: @@ -746,6 +776,7 @@ allOf: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - qcom,pcie-sa8540p then: diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml new file mode 100644 index 000000000000..a8574f8a84a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip AXI PCIe Bridge Common Properties + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + +properties: + reg: + maxItems: 2 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aclk + - const: aclk-perf + - const: hclk + - const: pm + + num-lanes: + maximum: 4 + + phys: + oneOf: + - maxItems: 1 + - maxItems: 4 + + phy-names: + oneOf: + - const: pcie-phy + - items: + - const: pcie-phy-0 + - const: pcie-phy-1 + - const: pcie-phy-2 + - const: pcie-phy-3 + + resets: + maxItems: 7 + + reset-names: + items: + - const: core + - const: mgmt + - const: mgmt-sticky + - const: pipe + - const: pm + - const: pclk + - const: aclk + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - phys + - phy-names + - resets + - reset-names + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml new file mode 100644 index 000000000000..88386a6d7011 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip AXI PCIe Endpoint + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + +allOf: + - $ref: /schemas/pci/pci-ep.yaml# + - $ref: rockchip,rk3399-pcie-common.yaml# + +properties: + compatible: + const: rockchip,rk3399-pcie-ep + + reg: true + + reg-names: + items: + - const: apb-base + - const: mem-base + + rockchip,max-outbound-regions: + description: Maximum number of outbound regions + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 32 + default: 32 + +required: + - rockchip,max-outbound-regions + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/rk3399-cru.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie-ep@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; + reg-names = "apb-base", "mem-base"; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; + rockchip,max-outbound-regions = <16>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml new file mode 100644 index 000000000000..531008f0b6ac --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip AXI PCIe Root Port Bridge Host + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: rockchip,rk3399-pcie-common.yaml# + +properties: + compatible: + const: rockchip,rk3399-pcie + + reg: true + + reg-names: + items: + - const: axi-base + - const: apb-base + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: sys + - const: legacy + - const: client + + aspm-no-l0s: + description: This property is needed if using 24MHz OSC for RC's PHY. + + ep-gpios: + description: pre-reset GPIO + + vpcie12v-supply: + description: The 12v regulator to use for PCIe. + + vpcie3v3-supply: + description: The 3.3v regulator to use for PCIe. + + vpcie1v8-supply: + description: The 1.8v regulator to use for PCIe. + + vpcie0v9-supply: + description: The 0.9v regulator to use for PCIe. + + interrupt-controller: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + +required: + - ranges + - "#interrupt-cells" + - interrupts + - interrupt-controller + - interrupt-map + - interrupt-map-mask + - msi-map + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/rk3399-cru.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@f8000000 { + compatible = "rockchip,rk3399-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "legacy", "client"; + ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 + 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; + num-lanes = <4>; + msi-map = <0x0 &its 0x0 0x1000>; + reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>; + reg-names = "axi-base", "apb-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + /* deprecated legacy PHY model */ + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt deleted file mode 100644 index 778467307a93..000000000000 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Rockchip AXI PCIe Endpoint Controller DT description - -Required properties: -- compatible: Should contain "rockchip,rk3399-pcie-ep" -- reg: Two register ranges as listed in the reg-names property -- reg-names: Must include the following names - - "apb-base" - - "mem-base" -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "aclk" - - "aclk-perf" - - "hclk" - - "pm" -- resets: Must contain seven entries for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following names - - "core" - - "mgmt" - - "mgmt-sticky" - - "pipe" - - "pm" - - "aclk" - - "pclk" -- pinctrl-names : The pin control state names -- pinctrl-0: The "default" pinctrl state -- phys: Must contain an phandle to a PHY for each entry in phy-names. -- phy-names: Must include 4 entries for all 4 lanes even if some of - them won't be used for your cases. Entries are of the form "pcie-phy-N": - where N ranges from 0 to 3. - (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt - for changing the #phy-cells of phy node to support it) -- rockchip,max-outbound-regions: Maximum number of outbound regions - -Optional Property: -- num-lanes: number of lanes to use -- max-functions: Maximum number of functions that can be configured (default 1). - -pcie0-ep: pcie@f8000000 { - compatible = "rockchip,rk3399-pcie-ep"; - #address-cells = <3>; - #size-cells = <2>; - rockchip,max-outbound-regions = <16>; - clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; - clock-names = "aclk", "aclk-perf", - "hclk", "pm"; - max-functions = /bits/ 8 <8>; - num-lanes = <4>; - reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; - reg-names = "apb-base", "mem-base"; - resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, - <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , - <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; - reset-names = "core", "mgmt", "mgmt-sticky", "pipe", - "pm", "pclk", "aclk"; - phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; - phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreq>; -}; diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt deleted file mode 100644 index af34c65773fd..000000000000 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt +++ /dev/null @@ -1,135 +0,0 @@ -* Rockchip AXI PCIe Root Port Bridge DT description - -Required properties: -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- compatible: Should contain "rockchip,rk3399-pcie" -- reg: Two register ranges as listed in the reg-names property -- reg-names: Must include the following names - - "axi-base" - - "apb-base" -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "aclk" - - "aclk-perf" - - "hclk" - - "pm" -- msi-map: Maps a Requester ID to an MSI controller and associated - msi-specifier data. See ./pci-msi.txt -- interrupts: Three interrupt entries must be specified. -- interrupt-names: Must include the following names - - "sys" - - "legacy" - - "client" -- resets: Must contain seven entries for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following names - - "core" - - "mgmt" - - "mgmt-sticky" - - "pipe" - - "pm" - - "aclk" - - "pclk" -- pinctrl-names : The pin control state names -- pinctrl-0: The "default" pinctrl state -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- interrupt-map-mask and interrupt-map: standard PCI properties - -Required properties for legacy PHY model (deprecated): -- phys: From PHY bindings: Phandle for the Generic PHY for PCIe. -- phy-names: MUST be "pcie-phy". - -Required properties for per-lane PHY model (preferred): -- phys: Must contain an phandle to a PHY for each entry in phy-names. -- phy-names: Must include 4 entries for all 4 lanes even if some of - them won't be used for your cases. Entries are of the form "pcie-phy-N": - where N ranges from 0 to 3. - (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt - for changing the #phy-cells of phy node to support it) - -Optional Property: -- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if - using 24MHz OSC for RC's PHY. -- ep-gpios: contain the entry for pre-reset GPIO -- num-lanes: number of lanes to use -- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe. -- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. -- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. -- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe. - -*Interrupt controller child node* -The core controller provides a single interrupt for legacy INTx. The PCIe node -should contain an interrupt controller node as a target for the PCI -'interrupt-map' property. This node represents the domain at which the four -INTx interrupts are decoded and routed. - - -Required properties for Interrupt controller child node: -- interrupt-controller: identifies the node as an interrupt controller -- #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - -Example: - -pcie0: pcie@f8000000 { - compatible = "rockchip,rk3399-pcie"; - #address-cells = <3>; - #size-cells = <2>; - clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; - clock-names = "aclk", "aclk-perf", - "hclk", "pm"; - bus-range = <0x0 0x1>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "legacy", "client"; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 - 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; - num-lanes = <4>; - msi-map = <0x0 &its 0x0 0x1000>; - reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>; - reg-names = "axi-base", "apb-base"; - resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, - <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , - <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; - reset-names = "core", "mgmt", "mgmt-sticky", "pipe", - "pm", "pclk", "aclk"; - /* deprecated legacy PHY model */ - phys = <&pcie_phy>; - phy-names = "pcie-phy"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreq>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - pcie0_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; -}; - -pcie0: pcie@f8000000 { - ... - - /* preferred per-lane PHY model */ - phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; - phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; - - ... -}; diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml index 437e61618d06..f0d8e486a07d 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -15,9 +15,6 @@ description: | maintainers: - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> -allOf: - - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# - properties: compatible: enum: @@ -29,40 +26,25 @@ properties: maxItems: 5 reg-names: - oneOf: - - items: - - const: dbi - - const: dbi2 - - const: link - - const: addr_space - - items: - - const: dbi - - const: dbi2 - - const: link - - const: addr_space - - const: atu + minItems: 4 + items: + - const: dbi + - const: dbi2 + - const: link + - const: addr_space + - const: atu clocks: minItems: 1 maxItems: 2 - clock-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - const: link # for NX1 + clock-names: true resets: minItems: 1 maxItems: 2 - reset-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - const: link # for NX1 + reset-names: true num-ib-windows: const: 16 @@ -78,6 +60,46 @@ properties: phy-names: const: pcie-phy +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pro5-pcie-ep + then: + properties: + reg: + maxItems: 4 + reg-names: + maxItems: 4 + clocks: + minItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + reset-names: + items: + - const: gio + - const: link + else: + properties: + reg: + minItems: 5 + reg-names: + minItems: 5 + clocks: + maxItems: 1 + clock-names: + const: link + resets: + maxItems: 1 + reset-names: + const: link + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index b0513b197d08..3d7aee97353a 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -66,15 +66,11 @@ properties: const: 0x104c device-id: - oneOf: - - items: - - const: 0xb00d - - items: - - const: 0xb00f - - items: - - const: 0xb010 - - items: - - const: 0xb013 + enum: + - 0xb00d + - 0xb00f + - 0xb010 + - 0xb013 msi-map: true diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml new file mode 100644 index 000000000000..a55a4d047d3f --- /dev/null +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V SBI PMU events + +maintainers: + - Atish Patra <atishp@rivosinc.com> + +description: | + The SBI PMU extension allows supervisor software to configure, start and + stop any performance counter at anytime. Thus, a user can leverage all + capabilities of performance analysis tools, such as perf, if the SBI PMU + extension is enabled. The following constraints apply: + + The platform must provide information about PMU event to counter mappings + either via device tree or another way, specific to the platform. + Without the event to counter mappings, the SBI PMU extension cannot be used. + + Platforms should provide information about the PMU event selector values + that should be encoded in the expected value of MHPMEVENTx while configuring + MHPMCOUNTERx for that specific event. The can either be done via device tree + or another way, specific to the platform. + The exact value to be written to MHPMEVENTx is completely dependent on the + platform. + + For information on the SBI specification see the section "Performance + Monitoring Unit Extension" of: + https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc + +properties: + compatible: + const: riscv,pmu + + riscv,event-to-mhpmevent: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-ONE mapping between a PMU event and the event + selector value that the platform expects to be written to the MHPMEVENTx + CSR for that event. + The mapping is encoded in an matrix format where each element represents + an event. + This property shouldn't encode any raw hardware event. + items: + items: + - description: event_idx, a 20-bit wide encoding of the event type and + code. Refer to the SBI specification for a complete description of + the event types and codes. + - description: upper 32 bits of the event selector value for MHPMEVENTx + - description: lower 32 bits of the event selector value for MHPMEVENTx + + riscv,event-to-mhpmcounters: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents a MANY-to-MANY mapping between a range of events and all the + MHPMCOUNTERx in a bitmap format that can be used to monitor these range + of events. The information is encoded in an matrix format where each + element represents a certain range of events and corresponding counters. + This property shouldn't encode any raw event. + items: + items: + - description: first event_idx of the range of events + - description: last event_idx of the range of events + - description: bitmap of MHPMCOUNTERx for this event + + riscv,raw-event-to-mhpmcounters: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s) + and all the MHPMCOUNTERx in a bitmap format that can be used to monitor + that raw event. + The encoding of the raw events are platform specific. The information is + encoded in a matrix format where each element represents the specific raw + event(s). + If a platform directly encodes each raw PMU event as a unique ID, the + value of variant must be 0xffffffff_ffffffff. + items: + items: + - description: + upper 32 invariant bits for the range of events + - description: + lower 32 invariant bits for the range of events + - description: + upper 32 bits of the variant bit mask for the range of events + - description: + lower 32 bits of the variant bit mask for the range of events + - description: + bitmap of all MHPMCOUNTERx that can monitor the range of events + +dependencies: + "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ] + "riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ] + +required: + - compatible + +additionalProperties: false + +examples: + - | + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>; + riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>, + <0x00002 0x00002 0x00000004>, + <0x00003 0x0000A 0x00000ff8>, + <0x10000 0x10033 0x000ff000>; + riscv,raw-event-to-mhpmcounters = + /* For event ID 0x0002 */ + <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>, + /* For event ID 0-4 */ + <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>, + /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */ + <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>; + }; + + - | + /* + * For HiFive Unmatched board the encodings can be found here + * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf + * + * This example also binds standard SBI PMU hardware IDs to U74 PMU event + * codes, U74 uses a bitfield for events encoding, so several U74 events + * can be bound to a single perf ID. + * See SBI PMU hardware IDs in arch/riscv/include/asm/sbi.h + */ + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */ + <0x00003 0x00000000 0x1801>, + /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */ + <0x00004 0x00000000 0x0302>, + /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */ + <0x00005 0x00000000 0x4000>, + /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */ + <0x00006 0x00000000 0x6001>, + /* L1D_READ_MISS -> Data cache miss or MMIO access */ + <0x10001 0x00000000 0x0202>, + /* L1D_WRITE_ACCESS -> Data cache write-back */ + <0x10002 0x00000000 0x0402>, + /* L1I_READ_ACCESS -> Instruction cache miss */ + <0x10009 0x00000000 0x0102>, + /* LL_READ_MISS -> UTLB miss */ + <0x10011 0x00000000 0x2002>, + /* DTLB_READ_MISS -> Data TLB miss */ + <0x10019 0x00000000 0x1002>, + /* ITLB_READ_MISS-> Instruction TLB miss */ + <0x10021 0x00000000 0x0802>; + riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>, + <0x10001 0x10002 0x18>, + <0x10009 0x10009 0x18>, + <0x10011 0x10011 0x18>, + <0x10019 0x10019 0x18>, + <0x10021 0x10021 0x18>; + riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>, + <0x0 0x1 0xffffffff 0xfff800ff 0x18>, + <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; + }; diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml new file mode 100644 index 000000000000..948839499235 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner F1C100s USB PHY + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,suniv-f1c100s-usb-phy + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy_ctrl + + clocks: + maxItems: 1 + description: USB OTG PHY bus clock + + clock-names: + const: usb0_phy + + resets: + maxItems: 1 + description: USB OTG reset + + reset-names: + const: usb0_reset + + usb0_id_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/suniv-ccu-f1c100s.h> + #include <dt-bindings/reset/suniv-ccu-f1c100s.h> + + phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml index f3a5fbabbbb5..bb01c6b34dab 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml @@ -2,7 +2,7 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb2-phy.yaml#" +$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb2-phy.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Amlogic G12A USB2 PHY @@ -13,8 +13,8 @@ maintainers: properties: compatible: enum: - - amlogic,meson-g12a-usb2-phy - - amlogic,meson-a1-usb2-phy + - amlogic,g12a-usb2-phy + - amlogic,a1-usb2-phy reg: maxItems: 1 @@ -68,7 +68,7 @@ additionalProperties: false examples: - | phy@36000 { - compatible = "amlogic,meson-g12a-usb2-phy"; + compatible = "amlogic,g12a-usb2-phy"; reg = <0x36000 0x2000>; clocks = <&xtal>; clock-names = "xtal"; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml index 868b4e6fde71..3314711292d6 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml @@ -2,7 +2,7 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#" +$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Amlogic G12A USB3 + PCIE Combo PHY @@ -13,7 +13,7 @@ maintainers: properties: compatible: enum: - - amlogic,meson-g12a-usb3-pcie-phy + - amlogic,g12a-usb3-pcie-phy reg: maxItems: 1 @@ -35,6 +35,11 @@ properties: "#phy-cells": const: 1 + phy-supply: + description: + Phandle to a regulator that provides power to the PHY. This + regulator will be managed during the PHY power on/off sequence. + required: - compatible - reg @@ -49,7 +54,7 @@ additionalProperties: false examples: - | phy@46000 { - compatible = "amlogic,meson-g12a-usb3-pcie-phy"; + compatible = "amlogic,g12a-usb3-pcie-phy"; reg = <0x46000 0x2000>; clocks = <&ref_clk>; clock-names = "ref_clk"; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml new file mode 100644 index 000000000000..c2f5c9d2fce6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/amlogic,meson-gxl-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson GXL USB2 PHY + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + const: amlogic,meson-gxl-usb2-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: phy + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + "#phy-cells": + const: 0 + + phy-supply: true + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@78000 { + compatible = "amlogic,meson-gxl-usb2-phy"; + reg = <0x78000 0x20>; + clocks = <&xtal>; + clock-names = "phy"; + resets = <&phy_reset>; + reset-names = "phy"; + #phy-cells = <0>; + phy-supply = <&usb2_supply>; + }; diff --git a/Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml b/Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml index 20b79e2e8b82..b11d9873854a 100644 --- a/Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml +++ b/Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml @@ -27,7 +27,8 @@ properties: description: phandle of syscon used to control usb tcxo. hisilicon,eye-diagram-param: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 description: Eye diagram for phy. required: diff --git a/Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml b/Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml index 1cb00dbcd4c5..3c69aca6c7eb 100644 --- a/Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml +++ b/Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml @@ -32,7 +32,8 @@ properties: description: phandle of syscon used to control phy deep sleep. hisilicon,eye-diagram-param: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 description: Eye diagram for phy. hisilicon,tx-vboost-lvl: diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 5613cc5106e3..230a17f24966 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -79,6 +79,7 @@ properties: - enum: - mediatek,mt2712-tphy - mediatek,mt7629-tphy + - mediatek,mt7986-tphy - mediatek,mt8183-tphy - mediatek,mt8186-tphy - mediatek,mt8192-tphy diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt deleted file mode 100644 index b84a02ebffdf..000000000000 --- a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Amlogic Meson GXL and GXM USB2 PHY binding - -Required properties: -- compatible: Should be "amlogic,meson-gxl-usb2-phy" -- reg: The base address and length of the registers -- #phys-cells: must be 0 (see phy-bindings.txt in this directory) - -Optional properties: -- clocks: a phandle to the clock of this PHY -- clock-names: must be "phy" -- resets: a phandle to the reset line of this PHY -- reset-names: must be "phy" -- phy-supply: see phy-bindings.txt in this directory - - -Example: - usb2_phy0: phy@78000 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78000 0x0 0x20>; - }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt deleted file mode 100644 index b62397d2bb0c..000000000000 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ /dev/null @@ -1,779 +0,0 @@ -Device tree binding for NVIDIA Tegra XUSB pad controller -======================================================== - -The Tegra XUSB pad controller manages a set of I/O lanes (with differential -signals) which connect directly to pins/pads on the SoC package. Each lane -is controlled by a HW block referred to as a "pad" in the Tegra hardware -documentation. Each such "pad" may control either one or multiple lanes, -and thus contains any logic common to all its lanes. Each lane can be -separately configured and powered up. - -Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or -super-speed USB. Other lanes are for various types of low-speed, full-speed -or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller -contains a software-configurable mux that sits between the I/O controller -ports (e.g. PCIe) and the lanes. - -In addition to per-lane configuration, USB 3.0 ports may require additional -settings on a per-board basis. - -Pads will be represented as children of the top-level XUSB pad controller -device tree node. Each lane exposed by the pad will be represented by its -own subnode and can be referenced by users of the lane using the standard -PHY bindings, as described by the phy-bindings.txt file in this directory. - -The Tegra hardware documentation refers to the connection between the XUSB -pad controller and the XUSB controller as "ports". This is confusing since -"port" is typically used to denote the physical USB receptacle. The device -tree binding in this document uses the term "port" to refer to the logical -abstraction of the signals that are routed to a USB receptacle (i.e. a PHY -for the USB signal, the VBUS power supply, the USB 2.0 companion port for -USB 3.0 receptacles, ...). - -Required properties: --------------------- -- compatible: Must be: - - Tegra124: "nvidia,tegra124-xusb-padctl" - - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - - Tegra210: "nvidia,tegra210-xusb-padctl" - - Tegra186: "nvidia,tegra186-xusb-padctl" - - Tegra194: "nvidia,tegra194-xusb-padctl" -- reg: Physical base address and length of the controller's registers. -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must include the following entries: - - "padctl" - -For Tegra124: -- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V. -- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. -- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. -- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V. - -For Tegra210: -- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V. -- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. -- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. -- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. -- nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node. - -For Tegra186: -- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY - power supply. Must supply 1.8 V. -- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply - 3.3 V. -- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. -- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. - -For Tegra194: -- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply - 3.3 V. -- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - -Pad nodes: -========== - -A required child node named "pads" contains a list of subnodes, one for each -of the pads exposed by the XUSB pad controller. Each pad may need additional -resources that can be referenced in its pad node. - -The "status" property is used to enable or disable the use of a pad. If set -to "disabled", the pad will not be used on the given board. In order to use -the pad and any of its lanes, this property must be set to "okay". - -For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie -and sata. No extra resources are required for operation of these pads. - -For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is -a description of the properties of each pad. - -UTMI pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "trk": phandle and specifier referring to the USB2 tracking clock - -HSIC pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "trk": phandle and specifier referring to the HSIC tracking clock - -PCIe pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "pll": phandle and specifier referring to the PLLE -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must contain the following entries: - - "phy": reset for the PCIe UPHY block - -SATA pad: ---------- - -Required properties: -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must contain the following entries: - - "phy": reset for the SATA UPHY block - - -PHY nodes: -========== - -Each pad node has a child named "lanes" that contains one or more children of -its own, each representing one of the lanes controlled by the pad. - -Required properties: --------------------- -- status: Defines the operation status of the PHY. Valid values are: - - "disabled": the PHY is disabled - - "okay": the PHY is enabled -- #phy-cells: Should be 0. Since each lane represents a single PHY, there is - no need for an additional specifier. -- nvidia,function: The output function of the PHY. See below for a list of - valid functions per SoC generation. - -For Tegra124 and Tegra132, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2 - - functions: "snps", "xusb", "uart" -- ulpi: ulpi-0 - - functions: "snps", "xusb" -- hsic: hsic-0, hsic-1 - - functions: "snps", "xusb" -- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4 - - functions: "pcie", "usb3-ss" -- sata: sata-0 - - functions: "usb3-ss", "sata" - -For Tegra210, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2, usb2-3 - - functions: "snps", "xusb", "uart" -- hsic: hsic-0, hsic-1 - - functions: "snps", "xusb" -- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6 - - functions: "pcie-x1", "usb3-ss", "pcie-x4" -- sata: sata-0 - - functions: "usb3-ss", "sata" - -For Tegra194, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2, usb2-3 - - functions: "xusb" -- usb3: usb3-0, usb3-1, usb3-2, usb3-3 - - functions: "xusb" - -Port nodes: -=========== - -A required child node named "ports" contains a list of all the ports exposed -by the XUSB pad controller. Per-port configuration is only required for USB. - -USB2 ports: ------------ - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- mode: A string that determines the mode in which to run the port. Valid - values are: - - "host": for USB host mode - - "device": for USB device mode - - "otg": for USB OTG mode - -Required properties for OTG/Peripheral capable USB2 ports: -- usb-role-switch: Boolean property to indicate that the port support OTG or - peripheral mode. If present, the port supports switching between USB host - and peripheral roles. Connector should be added as subnode. - See usb/usb-conn-gpio.txt. - -Optional properties: -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -ULPI ports: ------------ - -Optional properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -HSIC ports: ------------ - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled - -Optional properties: -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -Super-speed USB ports: ----------------------- - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- nvidia,usb2-companion: A single cell that specifies the physical port number - to map this super-speed USB port to. The range of valid port numbers varies - with the SoC generation: - - 0-2: for Tegra124 and Tegra132 - - 0-3: for Tegra210 - -Optional properties: -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. - -- maximum-speed: Only for Tegra194. A string property that specifies maximum - supported speed of a usb3 port. Valid values are: - - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed. - - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only. - -For Tegra124 and Tegra132, the XUSB pad controller exposes the following -ports: -- 3x USB2: usb2-0, usb2-1, usb2-2 -- 1x ULPI: ulpi-0 -- 2x HSIC: hsic-0, hsic-1 -- 2x super-speed USB: usb3-0, usb3-1 - -For Tegra210, the XUSB pad controller exposes the following ports: -- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 -- 2x HSIC: hsic-0, hsic-1 -- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 - -For Tegra194, the XUSB pad controller exposes the following ports: -- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 -- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 - -Examples: -========= - -Tegra124 and Tegra132: ----------------------- - -SoC include: - - padctl@7009f000 { - /* for Tegra124 */ - compatible = "nvidia,tegra124-xusb-padctl"; - /* for Tegra132 */ - compatible = "nvidia,tegra132-xusb-padctl", - "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - pads { - usb2 { - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - ulpi { - status = "disabled"; - - lanes { - ulpi-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - ulpi-0 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - }; - }; - -Board file: - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* Micro A/B */ - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - /* Mini PCIe */ - usb2-1 { - status = "okay"; - mode = "host"; - }; - - /* USB3 */ - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,port = <2>; - status = "okay"; - }; - }; - }; - -Tegra210: ---------- - -SoC include: - - padctl@7009f000 { - compatible = "nvidia,tegra210-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-3 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 205>; - reset-names = "phy"; - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-5 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-6 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 204>; - reset-names = "phy"; - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - usb2-3 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - - usb3-3 { - status = "disabled"; - }; - }; - }; - -Board file: - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-3 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "pcie-x1"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-5 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - usb2-1 { - status = "okay"; - vbus-supply = <&vdd_5v0_rtl>; - mode = "host"; - }; - - usb2-2 { - status = "okay"; - vbus-supply = <&vdd_usb_vbus>; - mode = "host"; - }; - - usb2-3 { - status = "okay"; - mode = "host"; - }; - - usb3-0 { - status = "okay"; - nvidia,lanes = "pcie-6"; - nvidia,port = <1>; - }; - - usb3-1 { - status = "okay"; - nvidia,lanes = "pcie-5"; - nvidia,port = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml new file mode 100644 index 000000000000..33b41b6b2fd5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml @@ -0,0 +1,654 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra124 XUSB pad controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra124-xusb-padctl + + - items: + - const: nvidia,tegra132-xusb-padctl + - const: nvidia,tegra124-xusb-padctl + + reg: + maxItems: 1 + + interrupts: + items: + - description: XUSB pad controller interrupt + + resets: + items: + - description: pad controller reset + + reset-names: + items: + - const: padctl + + avdd-pll-utmip-supply: + description: UTMI PLL power supply. Must supply 1.8 V. + + avdd-pll-erefe-supply: + description: PLLE reference PLL power supply. Must supply 1.05 V. + + avdd-pex-pll-supply: + description: PCIe/USB3 PLL power supply. Must supply 1.05 V. + + hvdd-pex-pll-e-supply: + description: High-voltage PLLE power supply. Must supply 3.3 V. + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or be absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + ulpi: + type: object + additionalProperties: false + properties: + lanes: + type: object + additionalProperties: false + properties: + ulpi-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + hsic: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: HSIC tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + hsic-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + hsic-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + pcie: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: PLLE clock + + clock-names: + items: + - const: pll + + resets: + items: + - description: reset for the PCIe UPHY block + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + pcie-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-4: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + sata: + type: object + additionalProperties: false + properties: + resets: + items: + - description: reset for the SATA UPHY block + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + sata-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ sata, usb3-ss ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + ulpi-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + hsic-0: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + hsic-1: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - compatible + - reg + - resets + - reset-names + - avdd-pll-utmip-supply + - avdd-pll-erefe-supply + - avdd-pex-pll-supply + - hvdd-pex-pll-e-supply + +examples: + # Tegra124 and Tegra132 + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + padctl@7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x7009f000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + + pads { + usb2 { + lanes { + usb2-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + ulpi { + lanes { + ulpi-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + hsic-1 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + pcie { + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + #phy-cells = <0>; + }; + + pcie-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-2 { + nvidia,function = "pcie"; + #phy-cells = <0>; + }; + + pcie-3 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-4 { + nvidia,function = "pcie"; + #phy-cells = <0>; + }; + }; + }; + + sata { + lanes { + sata-0 { + nvidia,function = "sata"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + /* Micro A/B */ + usb2-0 { + mode = "otg"; + }; + + /* Mini PCIe */ + usb2-1 { + mode = "host"; + }; + + /* USB3 */ + usb2-2 { + vbus-supply = <&vdd_usb3_vbus>; + mode = "host"; + }; + + ulpi-0 { + status = "disabled"; + }; + + hsic-0 { + status = "disabled"; + }; + + hsic-1 { + status = "disabled"; + }; + + usb3-0 { + nvidia,usb2-companion = <2>; + }; + + usb3-1 { + status = "disabled"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml new file mode 100644 index 000000000000..8b1d5a8529e3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml @@ -0,0 +1,544 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 XUSB pad controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + const: nvidia,tegra186-xusb-padctl + + reg: + items: + - description: pad controller registers + - description: AO registers + + interrupts: + items: + - description: XUSB pad controller interrupt + + reg-names: + items: + - const: padctl + - const: ao + + resets: + items: + - description: pad controller reset + + reset-names: + items: + - const: padctl + + avdd-pll-erefeut-supply: + description: UPHY brick and reference clock as well as UTMI PHY + power supply. Must supply 1.8 V. + + avdd-usb-supply: + description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must + supply 3.3 V. + + vclamp-usb-supply: + description: Bias rail for USB pad. Must supply 1.8 V. + + vddio-hsic-supply: + description: HSIC PHY power supply. Must supply 1.2 V. + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or be absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + hsic: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: HSIC tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + hsic-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3: + type: object + additionalProperties: false + properties: + lanes: + type: object + additionalProperties: false + properties: + usb3-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + hsic-0: + type: object + additionalProperties: false + + usb3-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-2: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - compatible + - reg + - resets + - reset-names + - avdd-pll-erefeut-supply + - avdd-usb-supply + - vclamp-usb-supply + - vddio-hsic-supply + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/gpio/tegra186-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/tegra186-reset.h> + + padctl@3520000 { + compatible = "nvidia,tegra186-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + + resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + avdd-pll-erefeut-supply = <&vdd_1v8_pll>; + avdd-usb-supply = <&vdd_3v3_sys>; + vclamp-usb-supply = <&vdd_1v8>; + vddio-hsic-supply = <&gnd>; + + pads { + usb2 { + clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; + clock-names = "trk"; + status = "disabled"; + + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "otg"; + vbus-supply = <&vdd_usb0>; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(X, 7) GPIO_ACTIVE_LOW>; + id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + }; + + usb2-1 { + vbus-supply = <&vdd_usb1>; + mode = "host"; + }; + + usb2-2 { + status = "disabled"; + }; + + hsic-0 { + status = "disabled"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml new file mode 100644 index 000000000000..6e3398399628 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml @@ -0,0 +1,632 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra194 XUSB pad controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + enum: + - nvidia,tegra194-xusb-padctl + - nvidia,tegra234-xusb-padctl + + reg: + items: + - description: pad controller registers + - description: AO registers + + reg-names: + items: + - const: padctl + - const: ao + + interrupts: + items: + - description: XUSB pad controller interrupt + + resets: + items: + - description: pad controller reset + + reset-names: + items: + - const: padctl + + avdd-usb-supply: + description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must + supply 3.3 V. + + vclamp-usb-supply: + description: Bias rail for USB pad. Must supply 1.8 V. + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3: + type: object + additionalProperties: false + properties: + lanes: + type: object + additionalProperties: false + properties: + usb3-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-3: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb3-0: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-2: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-3: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - compatible + - reg + - resets + - reset-names + - avdd-usb-supply + - vclamp-usb-supply + +examples: + - | + #include <dt-bindings/clock/tegra194-clock.h> + #include <dt-bindings/gpio/tegra194-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/tegra194-reset.h> + + padctl@3520000 { + compatible = "nvidia,tegra194-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + + resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + avdd-usb-supply = <&vdd_usb_3v3>; + vclamp-usb-supply = <&vdd_1v8ao>; + + pads { + usb2 { + clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + mode = "host"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + vbus-supply = <&vdd_5v_sata>; + mode = "host"; + }; + + usb3-0 { + vbus-supply = <&vdd_5v0_sys>; + nvidia,usb2-companion = <1>; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + maximum-speed = "super-speed"; + vbus-supply = <&vdd_5v0_sys>; + nvidia,usb2-companion = <3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml new file mode 100644 index 000000000000..d16bd6e47f90 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml @@ -0,0 +1,786 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra210 XUSB pad controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + const: nvidia,tegra210-xusb-padctl + + reg: + maxItems: 1 + + resets: + items: + - description: pad controller reset + + interrupts: + items: + - description: XUSB pad controller interrupt + + reset-names: + items: + - const: padctl + + avdd-pll-utmip-supply: + description: UTMI PLL power supply. Must supply 1.8 V. + + avdd-pll-uerefe-supply: + description: PLLE reference PLL power supply. Must supply 1.05 V. + + dvdd-pex-pll-supply: + description: PCIe/USB3 PLL power supply. Must supply 1.05 V. + + hvdd-pex-pll-e-supply: + description: High-voltage PLLE power supply. Must supply 1.8 V. + + nvidia,pmc: + description: phandle to the Tegra Power Management Controller (PMC) node + $ref: /schemas/types.yaml#/definitions/phandle + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or be absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + hsic: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: HSIC tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + hsic-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + hsic-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + pcie: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: PCIe PLL clock source + + clock-names: + items: + - const: pll + + resets: + items: + - description: PCIe PHY reset + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + pcie-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-4: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-5: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-6: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + sata: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: SATA PLL clock source + + clock-names: + items: + - const: pll + + resets: + items: + - description: SATA PHY reset + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + sata-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ usb3-ss, sata ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-3: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + hsic-0: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + hsic-1: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-2: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-3: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - avdd-pll-utmip-supply + - avdd-pll-uerefe-supply + - dvdd-pex-pll-supply + - hvdd-pex-pll-e-supply + +examples: + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/gpio/tegra-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + padctl@7009f000 { + compatible = "nvidia,tegra210-xusb-padctl"; + reg = <0x7009f000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + avdd-pll-utmip-supply = <&vdd_1v8>; + avdd-pll-uerefe-supply = <&vdd_pex_1v05>; + dvdd-pex-pll-supply = <&vdd_pex_1v05>; + hvdd-pex-pll-e-supply = <&vdd_1v8>; + + pads { + usb2 { + clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; + clock-names = "trk"; + status = "disabled"; + + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + hsic-1 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + pcie { + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; + clock-names = "pll"; + resets = <&tegra_car 205>; + reset-names = "phy"; + + lanes { + pcie-0 { + nvidia,function = "pcie-x1"; + #phy-cells = <0>; + }; + + pcie-1 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-2 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-3 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-4 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-5 { + nvidia,function = "usb3-ss"; + #phy-cells = <0>; + }; + + pcie-6 { + nvidia,function = "usb3-ss"; + #phy-cells = <0>; + }; + }; + }; + + sata { + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; + clock-names = "pll"; + resets = <&tegra_car 204>; + reset-names = "phy"; + + lanes { + sata-0 { + nvidia,function = "sata"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "peripheral"; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_LOW>; + }; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_rtl>; + mode = "host"; + }; + + usb2-2 { + vbus-supply = <&vdd_usb_vbus>; + mode = "host"; + }; + + usb2-3 { + mode = "host"; + }; + + hsic-0 { + status = "disabled"; + }; + + hsic-1 { + status = "disabled"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + }; + + usb3-1 { + nvidia,usb2-companion = <2>; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml index fdb277edebeb..0c8f03b78608 100644 --- a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml @@ -43,6 +43,9 @@ properties: vddio-supply: description: phandle to VDD I/O supply regulator + '#clock-cells': + const: 0 + '#phy-cells': const: 0 @@ -53,7 +56,6 @@ allOf: contains: enum: - qcom,hdmi-phy-8660 - - qcom,hdmi-phy-8960 then: properties: clocks: @@ -68,6 +70,24 @@ allOf: compatible: contains: enum: + - qcom,hdmi-phy-8960 + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: slave_iface + - const: pxo + vddio-supply: false + + - if: + properties: + compatible: + contains: + enum: - qcom,hdmi-phy-8084 - qcom,hdmi-phy-8974 then: @@ -96,9 +116,10 @@ examples: "hdmi_pll"; reg = <0x4a00400 0x60>, <0x4a00500 0x100>; + #clock-cells = <0>; #phy-cells = <0>; power-domains = <&mmcc 1>; - clock-names = "slave_iface"; - clocks = <&clk 21>; + clock-names = "slave_iface", "pxo"; + clocks = <&clk 21>, <&pxo_board>; core-vdda-supply = <&pm8921_hdmi_mvs>; }; diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml index be41acbd3b6c..80a5348dbfde 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml @@ -75,6 +75,9 @@ patternProperties: minItems: 3 maxItems: 6 + "#clock-cells": + const: 1 + "#phy-cells": const: 0 diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml index 0c6b3ba7346b..e81a38281f8c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml @@ -30,6 +30,7 @@ properties: - qcom,sdm845-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sm6115-qmp-usb3-phy - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-phy @@ -253,6 +254,7 @@ allOf: contains: enum: - qcom,qcm2290-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy then: properties: clocks: @@ -321,6 +323,7 @@ allOf: - qcom,sc8180x-qmp-usb3-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sm6115-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-phy then: diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml new file mode 100644 index 000000000000..dbc4a4c71f05 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe2 PHY controller + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm + platforms. + +properties: + compatible: + items: + - const: qcom,qcs404-pcie2-phy + - const: qcom,pcie2-phy + + reg: + items: + - description: PHY register set + + clocks: + items: + - description: a clock-specifier pair for the "pipe" clock + + clock-output-names: + maxItems: 1 + + "#clock-cells": + const: 0 + + "#phy-cells": + const: 0 + + vdda-vp-supply: + description: low voltage regulator + + vdda-vph-supply: + description: high voltage regulator + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: pipe + +required: + - compatible + - reg + - clocks + - clock-output-names + - "#clock-cells" + - "#phy-cells" + - vdda-vp-supply + - vdda-vph-supply + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcs404.h> + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 636ea430fbff..7f403e77f320 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -82,81 +82,74 @@ properties: Phandle to TCSR syscon register region. $ref: /schemas/types.yaml#/definitions/phandle -if: - properties: - compatible: - contains: - const: qcom,qusb2-v2-phy -then: - properties: - qcom,imp-res-offset-value: - description: - It is a 6 bit value that specifies offset to be - added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY - tuning parameter that may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 63 - default: 0 - - qcom,bias-ctrl-value: - description: - It is a 6 bit value that specifies bias-ctrl-value. It is a PHY - tuning parameter that may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 63 - default: 32 - - qcom,charge-ctrl-value: - description: - It is a 2 bit value that specifies charge-ctrl-value. It is a PHY - tuning parameter that may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 3 - default: 0 - - qcom,hstx-trim-value: - description: - It is a 4 bit value that specifies tuning for HSTX - output current. - Possible range is - 15mA to 24mA (stepsize of 600 uA). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 15 - default: 3 - - qcom,preemphasis-level: - description: - It is a 2 bit value that specifies pre-emphasis level. - Possible range is 0 to 15% (stepsize of 5%). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 3 - default: 2 - - qcom,preemphasis-width: - description: - It is a 1 bit value that specifies how long the HSTX - pre-emphasis (specified using qcom,preemphasis-level) must be in - effect. Duration could be half-bit of full-bit. - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 1 - default: 0 - - qcom,hsdisc-trim-value: - description: - It is a 2 bit value tuning parameter that control disconnect - threshold and may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 3 - default: 0 + qcom,imp-res-offset-value: + description: + It is a 6 bit value that specifies offset to be + added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY + tuning parameter that may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 0 + + qcom,bias-ctrl-value: + description: + It is a 6 bit value that specifies bias-ctrl-value. It is a PHY + tuning parameter that may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 32 + + qcom,charge-ctrl-value: + description: + It is a 2 bit value that specifies charge-ctrl-value. It is a PHY + tuning parameter that may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + + qcom,hstx-trim-value: + description: + It is a 4 bit value that specifies tuning for HSTX + output current. + Possible range is - 15mA to 24mA (stepsize of 600 uA). + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + default: 3 + + qcom,preemphasis-level: + description: + It is a 2 bit value that specifies pre-emphasis level. + Possible range is 0 to 15% (stepsize of 5%). + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 2 + + qcom,preemphasis-width: + description: + It is a 1 bit value that specifies how long the HSTX + pre-emphasis (specified using qcom,preemphasis-level) must be in + effect. Duration could be half-bit of full-bit. + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1 + default: 0 + + qcom,hsdisc-trim-value: + description: + It is a 2 bit value tuning parameter that control disconnect + threshold and may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 required: - compatible @@ -169,6 +162,23 @@ required: - vdda-phy-dpdm-supply - resets +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,qusb2-v2-phy + then: + properties: + qcom,imp-res-offset-value: false + qcom,bias-ctrl-value: false + qcom,charge-ctrl-value: false + qcom,hstx-trim-value: false + qcom,preemphasis-level: false + qcom,preemphasis-width: false + qcom,hsdisc-trim-value: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml index d9d0ab90edb1..2e19a434c669 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml @@ -19,12 +19,17 @@ maintainers: properties: compatible: - enum: - - qcom,sc7180-qmp-usb3-dp-phy - - qcom,sc7280-qmp-usb3-dp-phy - - qcom,sc8180x-qmp-usb3-dp-phy - - qcom,sdm845-qmp-usb3-dp-phy - - qcom,sm8250-qmp-usb3-dp-phy + oneOf: + - enum: + - qcom,sc7180-qmp-usb3-dp-phy + - qcom,sc8180x-qmp-usb3-dp-phy + - qcom,sdm845-qmp-usb3-dp-phy + - qcom,sm8250-qmp-usb3-dp-phy + - items: + - enum: + - qcom,sc7280-qmp-usb3-dp-phy + - const: qcom,sm8250-qmp-usb3-dp-phy + reg: items: - description: Address and length of PHY's USB serdes block. @@ -46,18 +51,12 @@ properties: ranges: true clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - - description: 19.2 MHz ref clk. - - description: Phy common block aux clock. + minItems: 3 + maxItems: 4 clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - - const: com_aux + minItems: 3 + maxItems: 4 power-domains: maxItems: 1 @@ -166,6 +165,64 @@ required: - vdda-phy-supply - vdda-pll-supply +allOf: + - if: + properties: + compatible: + enum: + - qcom,sc7180-qmp-usb3-dp-phy + - qcom,sdm845-qmp-usb3-dp-phy + then: + properties: + clocks: + items: + - description: Phy aux clock + - description: Phy config clock + - description: 19.2 MHz ref clk + - description: Phy common block aux clock + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + + - if: + properties: + compatible: + enum: + - qcom,sc8180x-qmp-usb3-dp-phy + then: + properties: + clocks: + items: + - description: Phy aux clock + - description: 19.2 MHz ref clk + - description: Phy common block aux clock + clock-names: + items: + - const: aux + - const: ref + - const: com_aux + + - if: + properties: + compatible: + enum: + - qcom,sm8250-qmp-usb3-dp-phy + then: + properties: + clocks: + items: + - description: Phy aux clock + - description: Board XO source + - description: Phy common block aux clock + clock-names: + items: + - const: aux + - const: ref_clk_src + - const: com_aux + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 80aa8d2507fb..ef49efbd0a20 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -19,15 +19,20 @@ properties: - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy reg: minItems: 1 maxItems: 2 clocks: + minItems: 5 maxItems: 6 clock-names: + minItems: 5 items: - const: aux - const: cfg_ahb @@ -40,16 +45,21 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: + minItems: 1 items: - const: phy + - const: phy_nocsr vdda-phy-supply: true vdda-pll-supply: true + vdda-qref-supply: true + qcom,4ln-config-sel: description: PCIe 4-lane configuration $ref: /schemas/types.yaml#/definitions/phandle-array @@ -104,6 +114,46 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy + then: + properties: + clocks: + maxItems: 5 + clock-names: + maxItems: 5 + else: + properties: + clocks: + minItems: 6 + clock-names: + minItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-qmp-gen4x2-pcie-phy + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + examples: - | #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index dde86a19f792..64ed331880f6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -17,6 +17,8 @@ properties: compatible: enum: - qcom,sc8280xp-qmp-ufs-phy + - qcom,sm6125-qmp-ufs-phy + - qcom,sm8550-qmp-ufs-phy reg: maxItems: 1 @@ -43,6 +45,9 @@ properties: vdda-pll-supply: true + "#clock-cells": + const: 1 + "#phy-cells": const: 0 diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 6f31693d9868..3cd5fc3e8fab 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -17,6 +17,10 @@ properties: compatible: enum: - qcom,sc8280xp-qmp-usb43dp-phy + - qcom,sm6350-qmp-usb3-dp-phy + - qcom,sm8350-qmp-usb3-dp-phy + - qcom,sm8450-qmp-usb3-dp-phy + - qcom,sm8550-qmp-usb3-dp-phy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml new file mode 100644 index 000000000000..c53bab107b6d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SNPS eUSB2 phy controller + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + +description: + eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + +properties: + compatible: + const: qcom,sm8550-snps-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: ref + + clock-names: + items: + - const: ref + + resets: + maxItems: 1 + + phys: + maxItems: 1 + description: + Phandle to eUSB2 to USB 2.0 repeater + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda12-supply + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,sm8550-tcsr.h> + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x88e3000 0x154>; + #phy-cells = <0>; + + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml new file mode 100644 index 000000000000..083fda530b48 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Synopsis eUSB2 to USB 2.0 repeater + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + +description: + eUSB2 repeater converts between eUSB2 and USB 2.0 signaling levels and + allows a eUSB2 PHY to connect to legacy USB 2.0 products + +properties: + compatible: + const: qcom,pm8550b-eusb2-repeater + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + vdd18-supply: true + + vdd3-supply: true + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/spmi/spmi.h> + + pmic@7 { + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550b_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml index abcc4373f39e..ca6a0836b53c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml @@ -16,7 +16,6 @@ properties: compatible: enum: - qcom,usb-hs-28nm-femtophy - - qcom,usb-hs-28nm-mdm9607 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt deleted file mode 100644 index 3c7cb2be4b12..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt +++ /dev/null @@ -1,65 +0,0 @@ -Qualcomm's USB HSIC PHY - -PROPERTIES - -- compatible: - Usage: required - Value type: <string> - Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the - following: - - "qcom,usb-hsic-phy-mdm9615" - "qcom,usb-hsic-phy-msm8974" - -- #phy-cells: - Usage: required - Value type: <u32> - Definition: Should contain 0 - -- clocks: - Usage: required - Value type: <prop-encoded-array> - Definition: Should contain clock specifier for phy, calibration and - a calibration sleep clock - -- clock-names: - Usage: required - Value type: <stringlist> - Definition: Should contain "phy, "cal" and "cal_sleep" - -- pinctrl-names: - Usage: required - Value type: <stringlist> - Definition: Should contain "init" and "default" in that order - -- pinctrl-0: - Usage: required - Value type: <prop-encoded-array> - Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch - free state - -- pinctrl-1: - Usage: required - Value type: <prop-encoded-array> - Definition: List of pinctrl settings to apply to mux out the HSIC pins - -EXAMPLE - -usb-controller { - ulpi { - phy { - compatible = "qcom,usb-hsic-phy-msm8974", - "qcom,usb-hsic-phy"; - #phy-cells = <0>; - pinctrl-names = "init", "default"; - pinctrl-0 = <&hsic_sleep>; - pinctrl-1 = <&hsic_default>; - clocks = <&gcc GCC_USB_HSIC_CLK>, - <&gcc GCC_USB_HSIC_IO_CAL_CLK>, - <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>; - clock-names = "phy", "cal", "cal_sleep"; - assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>; - assigned-clock-rates = <960000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml new file mode 100644 index 000000000000..077e13a94448 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm USB HSIC PHY Controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Vinod Koul <vkoul@kernel.org> + +properties: + compatible: + items: + - enum: + - qcom,usb-hsic-phy-mdm9615 + - qcom,usb-hsic-phy-msm8974 + - const: qcom,usb-hsic-phy + + clocks: + maxItems: 3 + + clock-names: + items: + - const: phy + - const: cal + - const: cal_sleep + + "#phy-cells": + const: 0 + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + items: + - const: init + - const: default + +required: + - compatible + - clocks + - clock-names + - "#phy-cells" + - pinctrl-0 + - pinctrl-1 + - pinctrl-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8974.h> + + phy { + compatible = "qcom,usb-hsic-phy-msm8974", + "qcom,usb-hsic-phy"; + clocks = <&gcc GCC_USB_HSIC_CLK>, + <&gcc GCC_USB_HSIC_IO_CAL_CLK>, + <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>; + clock-names = "phy", "cal", "cal_sleep"; + #phy-cells = <0>; + pinctrl-names = "init", "default"; + pinctrl-0 = <&hsic_sleep>; + pinctrl-1 = <&hsic_default>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml index 68e70961beb2..85d405e028b9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -14,18 +14,25 @@ description: | properties: compatible: - enum: - - qcom,usb-snps-hs-5nm-phy - - qcom,usb-snps-hs-7nm-phy - - qcom,sc7280-usb-hs-phy - - qcom,sc8180x-usb-hs-phy - - qcom,sc8280xp-usb-hs-phy - - qcom,sm6375-usb-hs-phy - - qcom,sm8150-usb-hs-phy - - qcom,sm8250-usb-hs-phy - - qcom,sm8350-usb-hs-phy - - qcom,sm8450-usb-hs-phy - - qcom,usb-snps-femto-v2-phy + oneOf: + - enum: + - qcom,sc8180x-usb-hs-phy + - qcom,usb-snps-femto-v2-phy + - items: + - enum: + - qcom,sc8280xp-usb-hs-phy + - const: qcom,usb-snps-hs-5nm-phy + - items: + - enum: + - qcom,sc7280-usb-hs-phy + - qcom,sdx55-usb-hs-phy + - qcom,sdx65-usb-hs-phy + - qcom,sm6375-usb-hs-phy + - qcom,sm8150-usb-hs-phy + - qcom,sm8250-usb-hs-phy + - qcom,sm8350-usb-hs-phy + - qcom,sm8450-usb-hs-phy + - const: qcom,usb-snps-hs-7nm-phy reg: maxItems: 1 @@ -160,7 +167,7 @@ examples: #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,gcc-sm8150.h> phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy"; + compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0x088e2000 0x400>; #phy-cells = <0>; diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt deleted file mode 100644 index 30064253f290..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt +++ /dev/null @@ -1,42 +0,0 @@ -Qualcomm PCIe2 PHY controller -============================= - -The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm -platforms. - -Required properties: - - compatible: compatible list, should be: - "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a clock-specifier pair for the "pipe" clock - - - vdda-vp-supply: phandle to low voltage regulator - - vdda-vph-supply: phandle to high voltage regulator - - - resets: reset-specifier pairs for the "phy" and "pipe" resets - - reset-names: list of resets, should contain: - "phy" and "pipe" - - - clock-output-names: name of the outgoing clock signal from the PHY PLL - - #clock-cells: must be 0 - -Example: - phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc GCC_PCIE_0_PIPE_ARES>; - reset-names = "phy", "pipe"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index f71920082fa3..0d6b8c28be07 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml# +$id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip USB2.0 phy with inno IP block diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml new file mode 100644 index 000000000000..2538235c5ac6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip specific extensions to the Analogix Display Port PHY + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + const: rockchip,rk3288-dp-phy + + clocks: + maxItems: 1 + + clock-names: + const: 24m + + "#phy-cells": + const: 0 + +required: + - compatible + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt deleted file mode 100644 index e3b4809fbe82..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +++ /dev/null @@ -1,26 +0,0 @@ -Rockchip specific extensions to the Analogix Display Port PHY ------------------------------------- - -Required properties: -- compatible : should be one of the following supported values: - - "rockchip.rk3288-dp-phy" -- clocks: from common clock binding: handle to dp clock. - of memory mapped region. -- clock-names: from common clock binding: - Required elements: "24m" -- #phy-cells : from the generic PHY bindings, must be 0; - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - -... - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml index b03b2f00cc5b..3bee3f8733f7 100644 --- a/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml @@ -22,13 +22,13 @@ properties: samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true description: - Phandle to PMU system controller interface. + Phandle to PMU system controller interface (if not a child of PMU). required: - compatible - "#phy-cells" - - samsung,pmu-syscon additionalProperties: false @@ -36,6 +36,5 @@ examples: - | phy { compatible = "samsung,exynos5420-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml index 415440aaad89..b2250e4a6b1b 100644 --- a/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml @@ -35,15 +35,18 @@ properties: syscon: $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true description: Phandle to PMU system controller interface, valid only for - samsung,s5pv210-mipi-video-phy and samsung,exynos5420-mipi-video-phy. + samsung,s5pv210-mipi-video-phy and samsung,exynos5420-mipi-video-phy (if + not a child of PMU). samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true description: Phandle to PMU system controller interface, valid for - samsung,exynos5433-mipi-video-phy. + samsung,exynos5433-mipi-video-phy (if not a child of PMU). samsung,disp-sysreg: $ref: /schemas/types.yaml#/definitions/phandle @@ -81,13 +84,10 @@ allOf: samsung,disp-sysreg: false samsung,cam0-sysreg: false samsung,cam1-sysreg: false - required: - - syscon else: properties: syscon: false required: - - samsung,pmu-syscon - samsung,disp-sysreg - samsung,cam0-sysreg - samsung,cam1-sysreg @@ -99,7 +99,6 @@ examples: phy { compatible = "samsung,exynos5433-mipi-video-phy"; #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; samsung,cam0-sysreg = <&syscon_cam0>; samsung,cam1-sysreg = <&syscon_cam1>; samsung,disp-sysreg = <&syscon_disp>; diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml index a3cd45acea28..de3cffc850bc 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -117,20 +117,12 @@ additionalProperties: false examples: - | - ahci-glue@65700000 { - compatible = "socionext,uniphier-pxs3-ahci-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65700000 0x100>; - - ahci_phy: phy@10 { - compatible = "socionext,uniphier-pxs3-ahci-phy"; - reg = <0x10 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 28>, <&sys_clk 30>; - reset-names = "link", "phy"; - resets = <&sys_rst 28>, <&sys_rst 30>; - }; + ahci_phy: phy@10 { + compatible = "socionext,uniphier-pxs3-ahci-phy"; + reg = <0x10 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 28>, <&sys_clk 30>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; }; diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml index 63dab914a48d..19522c54f448 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml @@ -61,28 +61,23 @@ examples: - | // The UniPhier usb2-phy should be a subnode of a "syscon" compatible node. - soc-glue@5f800000 { - compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - usb-controller { - compatible = "socionext,uniphier-ld11-usb2-phy"; - #address-cells = <1>; - #size-cells = <0>; - - usb_phy0: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - usb_phy1: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - - usb_phy2: phy@2 { - reg = <2>; - #phy-cells = <0>; - }; + usb-hub { + compatible = "socionext,uniphier-ld11-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml index 21e4414eea60..2107d98ace15 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml @@ -146,22 +146,15 @@ additionalProperties: false examples: - | - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; - }; + usb_hsphy0: phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; }; diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml index 4c26d2d2303d..8f5aa6238bf3 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml @@ -131,21 +131,13 @@ additionalProperties: false examples: - | - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-ld20-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus0>; - }; + usb_ssphy0: phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; }; diff --git a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml index 02b76f15e717..237295b2b5a8 100644 --- a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml +++ b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml @@ -15,6 +15,7 @@ properties: compatible: enum: + - nxp,tjr1443 - ti,tcan1042 - ti,tcan1043 diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml index 6717f163390b..7ae084397258 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml @@ -1,13 +1,13 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale IMX8MM IOMUX Controller +title: Freescale IMX8M IOMUX Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Peng Fan <peng.fan@nxp.com> description: Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory @@ -15,7 +15,11 @@ description: properties: compatible: - const: fsl,imx8mm-iomuxc + enum: + - fsl,imx8mm-iomuxc + - fsl,imx8mn-iomuxc + - fsl,imx8mp-iomuxc + - fsl,imx8mq-iomuxc reg: maxItems: 1 @@ -34,9 +38,10 @@ patternProperties: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val input_val> are specified using a PIN_FUNC_ID macro, which can - be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Mini Reference Manual for detailed CONFIG settings. + be found in <arch/arm64/boot/dts/freescale/imx8m[m,n,p,q]-pinfunc.h>. + The last integer CONFIG is the pad setting value like pull-up on this + pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for + detailed CONFIG settings. $ref: /schemas/types.yaml#/definitions/uint32-matrix items: items: @@ -51,7 +56,8 @@ patternProperties: - description: | "input_val" indicates the select input value to be applied. - description: | - "pad_setting" indicates the pad configuration value to be applied. + "pad_setting" indicates the pad configuration value to be + applied. required: - fsl,pins diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml deleted file mode 100644 index b1cdbb56d4e4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml +++ /dev/null @@ -1,84 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Freescale IMX8MN IOMUX Controller - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory - for common binding part and usage. - -properties: - compatible: - const: fsl,imx8mn-iomuxc - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - 'grp$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - fsl,pins: - description: - each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg - mux_val input_val> are specified using a PIN_FUNC_ID macro, which can - be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Nano Reference Manual for detailed CONFIG settings. - $ref: /schemas/types.yaml#/definitions/uint32-matrix - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. - - required: - - fsl,pins - - additionalProperties: false - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mn-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_uart2: uart2grp { - fsl,pins = - <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, - <0x240 0x4A8 0x000 0x0 0x0 0x140>; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml deleted file mode 100644 index 4eed3a4e153a..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml +++ /dev/null @@ -1,84 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Freescale IMX8MP IOMUX Controller - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory - for common binding part and usage. - -properties: - compatible: - const: fsl,imx8mp-iomuxc - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - 'grp$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - fsl,pins: - description: - each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg - mux_val input_val> are specified using a PIN_FUNC_ID macro, which can - be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. - $ref: /schemas/types.yaml#/definitions/uint32-matrix - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. - - required: - - fsl,pins - - additionalProperties: false - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mp-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_uart2: uart2grp { - fsl,pins = - <0x228 0x488 0x5F0 0x0 0x6 0x49>, - <0x228 0x488 0x000 0x0 0x0 0x49>; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml deleted file mode 100644 index d4a8ea5551a5..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml +++ /dev/null @@ -1,84 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Freescale IMX8MQ IOMUX Controller - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory - for common binding part and usage. - -properties: - compatible: - const: fsl,imx8mq-iomuxc - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - 'grp$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - fsl,pins: - description: - each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg - mux_val input_val> are specified using a PIN_FUNC_ID macro, which can - be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Quad Reference Manual for detailed CONFIG settings. - $ref: /schemas/types.yaml#/definitions/uint32-matrix - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. - - required: - - fsl,pins - - additionalProperties: false - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_uart1: uart1grp { - fsl,pins = - <0x234 0x49C 0x4F4 0x0 0x0 0x49>, - <0x238 0x4A0 0x4F4 0x0 0x0 0x49>; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 1b44335b1e94..a55c8e4ff26e 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -70,11 +70,11 @@ allOf: - $ref: "pinctrl.yaml#" patternProperties: - '-[0-9]+$': + 'pins$': type: object additionalProperties: false patternProperties: - 'pins': + '(^pins|pins?$)': type: object additionalProperties: false description: | @@ -158,7 +158,7 @@ examples: <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - i2c0_pins_a: i2c0-0 { + i2c0_pins_a: i2c0-pins { pins1 { pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, <MT8135_PIN_101_SCL0__FUNC_SCL0>; @@ -166,7 +166,7 @@ examples: }; }; - i2c1_pins_a: i2c1-0 { + i2c1_pins_a: i2c1-pins { pins { pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, <MT8135_PIN_196_SCL1__FUNC_SCL1>; @@ -174,7 +174,7 @@ examples: }; }; - i2c2_pins_a: i2c2-0 { + i2c2_pins_a: i2c2-pins { pins1 { pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; bias-pull-down; @@ -186,7 +186,7 @@ examples: }; }; - i2c3_pins_a: i2c3-0 { + i2c3_pins_a: i2c3-pins { pins1 { pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>, <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index c9ea0cad489b..ac93eb8f01a6 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -61,11 +61,11 @@ then: - "#interrupt-cells" patternProperties: - '-[0-9]+$': + '-pins(-[a-z]+)?$': type: object additionalProperties: false patternProperties: - 'mux': + '^mux(-|$)': type: object additionalProperties: false description: | @@ -244,7 +244,7 @@ patternProperties: groups: enum: [wf0_2g, wf0_5g] - 'conf': + '^conf(-|$)': type: object additionalProperties: false description: | @@ -348,7 +348,7 @@ examples: gpio-controller; #gpio-cells = <2>; - pinctrl_eth_default: eth-0 { + pinctrl_eth_default: eth-pins { mux-mdio { groups = "mdc_mdio"; function = "eth"; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml new file mode 100644 index 000000000000..74c66fbcb2ae --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -0,0 +1,475 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT7981 Pin Controller + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +description: + The MediaTek's MT7981 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7981-pinctrl + + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: gpio + - const: iocfg_rt + - const: iocfg_rm + - const: iocfg_rb + - const: iocfg_lb + - const: iocfg_bl + - const: iocfg_tm + - const: iocfg_tl + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: > + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^.*mux.*$': + type: object + additionalProperties: false + description: | + pinmux configuration nodes. + + The following table shows the effective values of "group", "function" + properties and chip pinout pins + + groups function pins (in pin#) + --------------------------------------------------------------------- + "wa_aice1" "wa_aice" 0, 1 + "wa_aice2" "wa_aice" 0, 1 + "wm_uart_0" "uart" 0, 1 + "dfd" "dfd" 0, 1, 4, 5 + "watchdog" "watchdog" 2 + "pcie_pereset" "pcie" 3 + "jtag" "jtag" 4, 5, 6, 7, 8 + "wm_jtag_0" "jtag" 4, 5, 6, 7, 8 + "wo0_jtag_0" "jtag" 9, 10, 11, 12, 13 + "uart2_0" "uart" 4, 5, 6, 7 + "gbe_led0" "led" 8 + "pta_ext_0" "pta" 4, 5, 6 + "pwm2" "pwm" 7 + "net_wo0_uart_txd_0" "uart" 8 + "spi1_0" "spi" 4, 5, 6, 7 + "i2c0_0" "i2c" 6, 7 + "dfd_ntrst" "dfd" 8 + "wm_aice1" "wa_aice" 9, 10 + "pwm0_0" "pwm" 13 + "pwm0_1" "pwm" 15 + "pwm1_0" "pwm" 14 + "pwm1_1" "pwm" 15 + "net_wo0_uart_txd_1" "uart" 14 + "net_wo0_uart_txd_2" "uart" 15 + "gbe_led1" "led" 13 + "pcm" "pcm" 9, 10, 11, 12, 13, 25 + "watchdog1" "watchdog" 13 + "udi" "udi" 9, 10, 11, 12, 13 + "drv_vbus" "usb" 14 + "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 + "snfi" "flash" 16, 17, 18, 19, 20, 21 + "spi0" "spi" 16, 17, 18, 19 + "spi0_wp_hold" "spi" 20, 21 + "spi1_1" "spi" 22, 23, 24, 25 + "spi2" "spi" 26, 27, 28, 29 + "spi2_wp_hold" "spi" 30, 31 + "uart1_0" "uart" 16, 17, 18, 19 + "uart1_1" "uart" 26, 27, 28, 29 + "uart2_1" "uart" 22, 23, 24, 25 + "pta_ext_1" "pta" 22, 23, 24 + "wm_aurt_1" "uart" 20, 21 + "wm_aurt_2" "uart" 30, 31 + "wm_jtag_1" "jtag" 20, 21, 22, 23, 24 + "wo0_jtag_1" "jtag" 25, 26, 27, 28, 29 + "wa_aice3" "wa_aice" 28, 20 + "wm_aice2" "wa_aice" 30, 31 + "i2c0_1" "i2c" 30, 31 + "u2_phy_i2c" "i2c" 30, 31 + "uart0" "uart" 32, 33 + "sgmii1_phy_i2c" "i2c" 32, 33 + "u3_phy_i2c" "i2c" 32, 33 + "sgmii0_phy_i2c" "i2c" 32, 33 + "pcie_clk" "pcie" 34 + "pcie_wake" "pcie" 35 + "i2c0_2" "i2c" 36, 37 + "smi_mdc_mdio" "eth" 36, 37 + "gbe_ext_mdc_mdio" "eth" 36, 37 + "wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56 + + "wf0_mode3" "eth" 45, 46, 47, 48, 49, 51 + "wf2g_led0" "led" 30 + "wf2g_led1" "led" 34 + "wf5g_led0" "led" 31 + "wf5g_led1" "led" 35 + "mt7531_int" "eth" 38 + "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22 + 23, 24, 25, 34, 35 + + $ref: /schemas/pinctrl/pinmux-node.yaml + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led, + pwm, spi, uart, watchdog, flash, pcie] + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: wa_aice + then: + properties: + groups: + enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2] + - if: + properties: + function: + const: dfd + then: + properties: + groups: + enum: [dfd, dfd_ntrst] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1] + - if: + properties: + function: + const: pta + then: + properties: + groups: + enum: [pta_ext_0, pta_ext_1] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm] + - if: + properties: + function: + const: udi + then: + properties: + groups: + enum: [udi] + - if: + properties: + function: + const: usb + then: + properties: + groups: + enum: [drv_vbus] + - if: + properties: + function: + const: ant + then: + properties: + groups: + enum: [ant_sel] + - if: + properties: + function: + const: eth + then: + properties: + groups: + enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3, + mt7531_int] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c, + sgmii0_phy_i2c, i2c0_2] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, wf5g_led1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + items: + enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1] + maxItems: 3 + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_wp_hold] + maxItems: 4 + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0, + net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0, + uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0] + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + enum: [watchdog] + - if: + properties: + function: + const: flash + then: + properties: + groups: + items: + enum: [emmc_45, snfi] + maxItems: 1 + - if: + properties: + function: + const: pcie + then: + properties: + groups: + items: + enum: [pcie_clk, pcie_wake, pcie_pereset] + maxItems: 3 + + '^.*conf.*$': + type: object + additionalProperties: false + description: pinconf configuration nodes. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N, + JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N, + WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK, + WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, + SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, + SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_REQ, + PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET, + WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK, + WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0, + WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_HB10] + maxItems: 57 + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: > + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: > + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,pull-up-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull up setings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull down setings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", + "iocfg_rb", "iocfg_lb", "iocfg_bl", + "iocfg_tm", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 56>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mdio_pins: mdio-pins { + mux { + function = "eth"; + groups = "smi_mdc_mdio"; + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 0d2484056a0f..c30cd0d010dd 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -67,11 +67,11 @@ required: - gpio-ranges patternProperties: - '-[0-9]+$': + '-pins(-[a-z]+)?$': type: object additionalProperties: false patternProperties: - 'pins': + '^pins': type: object additionalProperties: false description: | @@ -210,7 +210,7 @@ examples: interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; - i2c0_pins_a: i2c-0 { + i2c0_pins_a: i2c0-pins { pins1 { pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; @@ -219,7 +219,7 @@ examples: }; }; - i2c1_pins_a: i2c-1 { + i2c1_pins_a: i2c1-pins { pins { pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 000000000000..4b96884a1afc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao <zhiyong.tao@mediatek.com> + - Bernhard Rosenkränzer <bero@baylibre.com> + +description: | + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in <soc>-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pull up + settings for 2 pull resistors, R0 and R1. User can configure those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt8365-pinfunc.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + + pio-pins { + pins { + pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, <MT8365_PIN_60_SCL1__FUNC_SCL1_0>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml new file mode 100644 index 000000000000..300747252a7b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5332 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5332-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 53 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5332-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5332-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5332-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0, + blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, + blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, + blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0, + cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, + gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1, + mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, + pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3, + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0, + rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd, + wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ] + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <0x2>; + + serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml index 93f231c7a3b4..28f1b6a07b70 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml index 5687acaf19bf..3137db927fc0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml index a0a12171b6d0..96b598bf9a76 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml index a4f6e4c588f4..c7c94d742ed2 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true '#interrupt-cells': true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml index 3b79f5be860b..6cb667fa8665 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -20,7 +20,9 @@ properties: description: Specifies the base address and size of the TLMM register space maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -54,7 +56,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 @@ -66,8 +68,8 @@ $defs: enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2, - blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3, - wlan ] + blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, + gp0_clk, gp1_clk, sdc3, wlan ] bias-pull-down: true bias-pull-up: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml index ad0cad4694c0..348d84c3cd21 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml index cc6d0c9c5100..85082adc1811 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -61,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, qdsd_data3 ] @@ -125,7 +127,7 @@ examples: interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 117>; + gpio-ranges = <&tlmm 0 0 113>; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml index 5495f58905af..633c9e5ed49e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index c9a4a79e8d01..ce219827ccc8 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -51,7 +53,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, qdsd_data3 ] diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml index 33d07d531273..cf386f644ccb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml index 9287cbbff711..afe4a80f0b79 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml index 858f45710fe2..5dfcc3eadbb0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml index 55d5439c6c24..0c4936fc35ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -32,10 +34,10 @@ properties: gpio-reserved-ranges: minItems: 1 - maxItems: 75 + maxItems: 73 gpio-line-names: - maxItems: 150 + maxItems: 146 patternProperties: "-state$": @@ -61,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ] minItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml index 8e1cd4ba1116..047b4584e3c0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml index 21ba32cc204a..c07ee9868046 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 29dd503f9522..db505fdeac86 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -40,6 +40,10 @@ properties: - qcom,pm8350b-gpio - qcom,pm8350c-gpio - qcom,pm8450-gpio + - qcom,pm8550-gpio + - qcom,pm8550b-gpio + - qcom,pm8550ve-gpio + - qcom,pm8550vs-gpio - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio @@ -52,10 +56,12 @@ properties: - qcom,pmi8994-gpio - qcom,pmi8998-gpio - qcom,pmk8350-gpio + - qcom,pmk8550-gpio - qcom,pmm8155au-gpio - qcom,pmp8074-gpio - qcom,pmr735a-gpio - qcom,pmr735b-gpio + - qcom,pmr735d-gpio - qcom,pms405-gpio - qcom,pmx55-gpio - qcom,pmx65-gpio @@ -111,6 +117,7 @@ allOf: enum: - qcom,pm8008-gpio - qcom,pmi8950-gpio + - qcom,pmr735d-gpio then: properties: gpio-line-names: @@ -146,6 +153,8 @@ allOf: enum: - qcom,pm8018-gpio - qcom,pm8019-gpio + - qcom,pm8550vs-gpio + - qcom,pmk8550-gpio then: properties: gpio-line-names: @@ -162,6 +171,7 @@ allOf: enum: - qcom,pm8226-gpio - qcom,pm8350b-gpio + - qcom,pm8550ve-gpio - qcom,pm8950-gpio then: properties: @@ -236,6 +246,8 @@ allOf: - qcom,pm8038-gpio - qcom,pm8150b-gpio - qcom,pm8150l-gpio + - qcom,pm8550-gpio + - qcom,pm8550b-gpio - qcom,pmc8180c-gpio - qcom,pmp8074-gpio - qcom,pms405-gpio @@ -411,6 +423,10 @@ $defs: - gpio1-gpio8 for pm8350b - gpio1-gpio9 for pm8350c - gpio1-gpio4 for pm8450 + - gpio1-gpio12 for pm8550 + - gpio1-gpio12 for pm8550b + - gpio1-gpio8 for pm8550ve + - gpio1-gpio6 for pm8550vs - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 - gpio1-gpio36 for pm8941 @@ -421,10 +437,12 @@ $defs: - gpio1-gpio2 for pmi8950 - gpio1-gpio10 for pmi8994 - gpio1-gpio4 for pmk8350 + - gpio1-gpio6 for pmk8550 - gpio1-gpio10 for pmm8155au - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12) - gpio1-gpio4 for pmr735a - gpio1-gpio4 for pmr735b + - gpio1-gpio2 for pmr735d - gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 72cce38bc1ce..9412b9362328 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -74,7 +74,7 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-pmic-mpp-state" - patternProperties: - "mpp": + '-pins$': $ref: "#/$defs/qcom-pmic-mpp-state" additionalProperties: false @@ -179,7 +179,7 @@ examples: }; default-state { - gpio-mpp { + gpio-pins { pins = "mpp1", "mpp2", "mpp3", "mpp4"; function = "digital"; input-enable; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml index adf64bfaa4ed..6271fd15e0b6 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml index 29d50c4a0034..20bc967a17b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml @@ -26,7 +26,9 @@ properties: - const: north - const: east - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml new file mode 100644 index 000000000000..7e5fb9a6e7d3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block + +maintainers: + - Melody Olvera <quic_molvera@quicinc.com> + +description: | + Top Level Mode Multiplexer pin controller found in the QDU1000 and + QRU1000 SoCs. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qdu1000-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 76 + + gpio-line-names: + maxItems: 151 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qdu1000-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qdu1000-tlmm-state" + additionalProperties: false + +$defs: + qcom-qdu1000-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng, + dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, + ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in, + intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist, + pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, + qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, + qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, + qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable, + qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request, + qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss, + qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs, + qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04, + qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14, + qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert, + smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2, + usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1, + vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + uart0-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup00"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml new file mode 100644 index 000000000000..70d9106ad83d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA8775P TLMM block + +maintainers: + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sa8775p-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 74 + + gpio-line-names: + maxItems: 148 + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sa8775p-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sa8775p-tlmm-state" + additionalProperties: false + +$defs: + qcom-sa8775p-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, + edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, + edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, + emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, + emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, + emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_gp4, gcc_gp5, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, + jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3, + mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, + mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, + mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, + mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, + mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1, + pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, + qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, + qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0, + sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1, + tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2, + tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f000000 { + compatible = "qcom,sa8775p-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 148>; + + qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml index b40f6dc6adae..f33792a1af6c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml @@ -26,7 +26,9 @@ properties: - const: north - const: south - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml index f7ec8a4f664f..e51feb4c0700 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -59,7 +59,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" + - pattern: "^gpio([0-9]|1[0-4])$" minItems: 1 maxItems: 15 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml index 24191d5f64ac..0ace55c9868e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml @@ -28,7 +28,9 @@ properties: - const: east - const: south - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true '#interrupt-cells': true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml index 7d2589387e1a..200b3b6ccd87 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml @@ -65,7 +65,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: - pattern: "^gpio([0-1]|1[0-8])$" + pattern: "^gpio([0-9]|1[0-8])$" function: enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, @@ -94,14 +94,12 @@ $defs: 2: Lower Slew rate (slower edges) 3: Reserved (No adjustments) + bias-bus-hold: true bias-pull-down: true - bias-pull-up: true - bias-disable: true - + input-enable: true output-high: true - output-low: true required: @@ -136,7 +134,7 @@ examples: clock-names = "core", "audio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&lpi_tlmm 0 0 18>; + gpio-ranges = <&lpi_tlmm 0 0 19>; dmic01-state { dmic01-clk-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml index 4efde29c36a2..97b27d6835e9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml index bd4fd8404aa4..ea6bd0b44f56 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml @@ -31,7 +31,9 @@ properties: - const: center - const: north - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml index 7585117c0f06..f586b3aa138e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml index c9627777ceb3..23d7c030fec0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -23,7 +23,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -48,6 +50,10 @@ patternProperties: $ref: "#/$defs/qcom-sdm845-tlmm-state" additionalProperties: false + "-hog(-[0-9]+)?$": + required: + - gpio-hog + $defs: qcom-sdm845-tlmm-state: type: object @@ -117,6 +123,7 @@ additionalProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> pinctrl@3400000 { @@ -130,6 +137,12 @@ examples: gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc_intc>; + ap-suspend-l-hog { + gpio-hog; + gpios = <126 GPIO_ACTIVE_LOW>; + output-low; + }; + cci0-default-state { pins = "gpio17", "gpio18"; function = "cci_i2c"; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml index a76117e41d93..a40175258495 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -20,7 +20,9 @@ properties: description: Specifies the base address and size of the TLMM register space maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -53,7 +55,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml index 2f53905260e6..89c5562583d1 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml index 164f24db8b2b..29325483cd2b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml @@ -26,7 +26,9 @@ properties: - const: south - const: east - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml index e1dd54a160d5..c9bc4893e8e8 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml @@ -27,7 +27,9 @@ properties: - const: south - const: east - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml index 41e3e0afc9a8..d95935fcc8b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml @@ -22,11 +22,21 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + minItems: 9 + maxItems: 9 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true - gpio-reserved-ranges: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 78 + + gpio-line-names: + maxItems: 156 + "#gpio-cells": true gpio-ranges: true wakeup-parent: true @@ -61,7 +71,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 @@ -118,7 +128,16 @@ examples: pinctrl@f100000 { compatible = "qcom,sm6350-tlmm"; reg = <0x0f100000 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml index d54ebb2bd5a8..66cef48ed59b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -61,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 @@ -132,7 +134,7 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 157>; + gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */ gpio-wo-subnode-state { pins = "gpio1"; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml index 85adddbdee56..4376a9bd4d70 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml @@ -27,7 +27,9 @@ properties: - const: north - const: south - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml index bd45faa3f078..de9d8854c690 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -64,7 +64,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" + - pattern: "^gpio([0-9]|1[0-3])$" minItems: 1 maxItems: 14 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index c80f3847ac08..cf561dff8893 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -25,7 +25,9 @@ properties: - const: south - const: north - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -129,6 +131,6 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 180>; + gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */ wakeup-parent = <&pdc>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index 0b1e4aa5819e..797242f68b1c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -22,11 +22,20 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true - gpio-reserved-ranges: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 102 + + gpio-line-names: + maxItems: 203 + "#gpio-cells": true gpio-ranges: true wakeup-parent: true @@ -61,7 +70,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 @@ -100,6 +109,7 @@ $defs: bias-pull-down: true bias-pull-up: true drive-strength: true + input-disable: true input-enable: true output-high: true output-low: true @@ -120,7 +130,7 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 203>; + gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */ gpio-wo-subnode-state { pins = "gpio1"; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index 01a0a4a40ba5..8bf51df0b231 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -65,7 +65,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: - pattern: "^gpio([0-9]|[1-2][0-9])$" + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" function: enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, @@ -96,14 +96,12 @@ $defs: 2: Lower Slew rate (slower edges) 3: Reserved (No adjustments) + bias-bus-hold: true bias-pull-down: true - bias-pull-up: true - bias-disable: true - + input-enable: true output-high: true - output-low: true required: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml index 4a1d10d6c5e7..56c8046f1be0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -32,7 +34,7 @@ properties: maxItems: 105 gpio-line-names: - maxItems: 209 + maxItems: 210 "#gpio-cells": true gpio-ranges: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..5e90051ed314 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC. + +properties: + compatible: + const: qcom,sm8550-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI pins SLEW registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + "#gpio-cells": + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8550-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8550-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8550-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk, + i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,sm8550-lpass-lpi-pinctrl"; + reg = <0x06e80000 0x20000>, + <0x0725a000 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml new file mode 100644 index 000000000000..a457425ba112 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8550 TLMM block + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8550-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 105 + + gpio-line-names: + maxItems: 210 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8550-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8550-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8550-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aon_cci, aoss_cti, atest_char, atest_usb, + audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, + cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl, + cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx, + coex_uart1_tx, coex_uart2_rx, coex_uart2_tx, + cri_trng, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, + i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, + i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, + ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, + pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, + qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, + qlink2_enable, qlink2_request, qlink2_wmss, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup1_se7, qup2_se0, + qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira, + qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb, + qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, + qup2_se7, sd_write_protect, sdc40, sdc41, sdc42, + sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, + tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, + tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, + uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, + usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8550-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup2_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup2_se7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index e1354f0c64f8..cb5ba1bd6f8d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -16,8 +16,9 @@ description: properties: interrupts: description: - Specifies the TLMM summary IRQ - maxItems: 1 + TLMM summary IRQ and dirconn interrupts. + minItems: 1 + maxItems: 9 interrupt-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml index 6f17f3991640..1e63ea34146a 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -29,47 +29,609 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [ - # common - i2c, spi, wdt, - - # For MT7620 SoC - ephy, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi refclk, - uartf, uartlite, wled, - - # For MT7628 and MT7688 SoCs - gpio, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, - p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0, - pwm1, refclk, sdmode, spi cs1, spis, uart0, uart1, uart2, - wled_an, wled_kn, - ] - function: - description: The mux function to select. - enum: [ - # common - gpio, i2c, refclk, spi, - - # For MT7620 SoC - ephy, gpio i2s, gpio uartf, i2s uartf, mdio, nand, pa, - pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, - rgmii1, rgmii2, sd, spi refclk, uartf, uartlite, wdt refclk, - wdt rst, wled, - - # For MT7628 and MT7688 SoCs - antenna, debug, i2s, jtag, p0led_an, p0led_kn, - p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, - p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, - rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi cs1, - spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -, - ] + description: + A string containing the name of the function to mux to the group. + anyOf: + - description: For MT7620 SoC + enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa, + pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk, + rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk, + wdt rst, wled] + + - description: For MT7628 and MT7688 SoCs + enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, + refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1, + spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 required: - groups - function + allOf: + - if: + properties: + function: + const: antenna + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: debug + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: ephy + then: + properties: + groups: + enum: [ephy] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + anyOf: + - description: For MT7620 SoC + enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, + spi, spi refclk, uartf, uartlite, wdt, wled] + + - description: For MT7628 and MT7688 SoCs + enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, + p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, perst, pwm0, pwm1, refclk, + sdmode, spi, spi cs1, spis, uart0, uart1, uart2, + wdt, wled_an, wled_kn] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, + sdmode] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: nand + then: + properties: + groups: + enum: [nd_sd] + + - if: + properties: + function: + const: p0led_an + then: + properties: + groups: + enum: [p0led_an] + + - if: + properties: + function: + const: p0led_kn + then: + properties: + groups: + enum: [p0led_kn] + + - if: + properties: + function: + const: p1led_an + then: + properties: + groups: + enum: [p1led_an] + + - if: + properties: + function: + const: p1led_kn + then: + properties: + groups: + enum: [p1led_kn] + + - if: + properties: + function: + const: p2led_an + then: + properties: + groups: + enum: [p2led_an] + + - if: + properties: + function: + const: p2led_kn + then: + properties: + groups: + enum: [p2led_kn] + + - if: + properties: + function: + const: p3led_an + then: + properties: + groups: + enum: [p3led_an] + + - if: + properties: + function: + const: p3led_kn + then: + properties: + groups: + enum: [p3led_kn] + + - if: + properties: + function: + const: p4led_an + then: + properties: + groups: + enum: [p4led_an] + + - if: + properties: + function: + const: p4led_kn + then: + properties: + groups: + enum: [p4led_kn] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [gpio] + + - if: + properties: + function: + const: pcie refclk + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcie rst + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: perst + then: + properties: + groups: + enum: [perst] + + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [uart1, uart2] + + - if: + properties: + function: + const: pwm0 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: pwm1 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: pwm_uart2 + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + anyOf: + - description: For MT7620 SoC + enum: [mdio] + + - description: For MT7628 and MT7688 SoCs + enum: [gpio, refclk, spi cs1] + + - if: + properties: + function: + const: rgmii1 + then: + properties: + groups: + enum: [rgmii1] + + - if: + properties: + function: + const: rgmii2 + then: + properties: + groups: + enum: [rgmii2] + + - if: + properties: + function: + const: rsvd + then: + properties: + groups: + enum: [p0led_an, p0led_kn, wled_an, wled_kn] + + - if: + properties: + function: + const: sd + then: + properties: + groups: + enum: [nd_sd] + + - if: + properties: + function: + const: sdxc + then: + properties: + groups: + enum: [sdmode] + + - if: + properties: + function: + const: sdxc d5 d4 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: sdxc d6 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: sdxc d7 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi cs1 + then: + properties: + groups: + enum: [spi cs1] + + - if: + properties: + function: + const: spi refclk + then: + properties: + groups: + enum: [spi refclk] + + - if: + properties: + function: + const: spis + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: sw_r + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart0 + then: + properties: + groups: + enum: [uart0] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: utif + then: + properties: + groups: + enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, + p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis] + + - if: + properties: + function: + const: wdt + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt refclk + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt rst + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled + then: + properties: + groups: + enum: [wled] + + - if: + properties: + function: + const: wled_an + then: + properties: + groups: + enum: [wled_an] + + - if: + properties: + function: + const: wled_kn + then: + properties: + groups: + enum: [wled_kn] + + - if: + properties: + function: + const: "-" + then: + properties: + groups: + enum: [i2c, spi cs1, uart0] + additionalProperties: false additionalProperties: false @@ -83,7 +645,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,mt7620-pinctrl"; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml index 61e5c847e8c8..1b1d37b981d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -29,21 +29,213 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1, - uart2, uart3, wdt] - function: - description: The mux function to select. + description: + A string containing the name of the function to mux to the group. enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi, uart1, uart2, uart3, wdt refclk, wdt rst] + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + required: - groups - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, + uart1, uart2, uart3, wdt] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: nand1 + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: nand2 + then: + properties: + groups: + enum: [sdhci] + + - if: + properties: + function: + const: pcie refclk + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcie rst + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: rgmii1 + then: + properties: + groups: + enum: [rgmii1] + + - if: + properties: + function: + const: rgmii2 + then: + properties: + groups: + enum: [rgmii2] + + - if: + properties: + function: + const: sdhci + then: + properties: + groups: + enum: [sdhci] + + - if: + properties: + function: + const: spdif2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: spdif3 + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: uart3 + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: wdt refclk + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt rst + then: + properties: + groups: + enum: [wdt] + additionalProperties: false additionalProperties: false @@ -57,7 +249,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,mt7621-pinctrl"; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml index 56e5becabcfd..7fd0df880a76 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -29,18 +29,93 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci] - function: - description: The mux function to select. + description: + A string containing the name of the function to mux to the group. enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci] + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + required: - groups - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: sdram + then: + properties: + groups: + enum: [sdram] + + - if: + properties: + function: + const: pci + then: + properties: + groups: + enum: [pci] + additionalProperties: false additionalProperties: false @@ -54,7 +129,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,rt2880-pinctrl"; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index f602a5d6e13a..4d66ca752a30 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -30,38 +30,225 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [ - # common - i2c, jtag, led, mdio, rgmii, spi, spi_cs1, uartf, uartlite, - - # For RT3050, RT3052 and RT3350 SoCs - sdram, - - # For RT3352 SoC - lna, pa - ] - function: - description: The mux function to select. - enum: [ - # common - gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, mdio, - pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf, - uartlite, wdg_cs1, + description: + A string containing the name of the function to mux to the group. + anyOf: + - description: For RT3050, RT3052 and RT3350 SoCs + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, + pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, + uartlite] - # For RT3050, RT3052 and RT3350 SoCs - sdram, + - description: For RT3352 SoC + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + lna, mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, + spi_cs1, uartf, uartlite, wdg_cs1] - # For RT3352 SoC - lna, pa - ] + - description: For RT5350 SoC + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, + uartlite, wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 required: - groups - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + anyOf: + - description: For RT3050, RT3052 and RT3350 SoCs + enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, + uartlite] + + - description: For RT3352 SoC + enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, + uartf, uartlite] + + - description: For RT5350 SoC + enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: lna + then: + properties: + groups: + enum: [lna] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: sdram + then: + properties: + groups: + enum: [sdram] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + additionalProperties: false additionalProperties: false @@ -75,7 +262,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,rt305x-pinctrl"; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml index feb6e66dcb61..008d93181aea 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -29,21 +29,213 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf, - uartlite] - function: - description: The mux function to select. + description: + A string containing the name of the function to mux to the group. enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2, pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite] + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + required: - groups - function + allOf: + - if: + properties: + function: + const: ge1 + then: + properties: + groups: + enum: [ge1] + + - if: + properties: + function: + const: ge2 + then: + properties: + groups: + enum: [ge2] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: lna a + then: + properties: + groups: + enum: [lna a] + + - if: + properties: + function: + const: lna g + then: + properties: + groups: + enum: [lna g] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pci-dev + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-fnc + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-host1 + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-host2 + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + additionalProperties: false additionalProperties: false @@ -57,7 +249,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,rt3883-pinctrl"; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml new file mode 100644 index 000000000000..ab2d456c93e4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Port Output Enable for GPT (POEG) + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be + disabled by using the port output enabling function for the GPT (POEG). + Specifically, either of the following ways can be used. + * Input level detection of the GTETRGA to GTETRGD pins. + * Output-disable request from the GPT. + * SSF bit setting(ie, by setting POEGGn.SSF to 1) + + The state of the GTIOCxA and the GTIOCxB pins when the output is disabled, + are controlled by the GPT module. + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-poeg # RZ/G2{L,LC} + - renesas,r9a07g054-poeg # RZ/V2L + - const: renesas,rzg2l-poeg + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + renesas,gpt: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to gpt instance that serves the pwm operation. + + renesas,poeg-id: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + POEG group index. Valid values are: + <0> : POEG group A + <1> : POEG group B + <2> : POEG group C + <3> : POEG group D + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + - renesas,poeg-id + - renesas,gpt + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + poeggd: poeg@10049400 { + compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg"; + reg = <0x10049400 0x400>; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_POEG_D_RST>; + renesas,poeg-id = <3>; + renesas,gpt = <&gpt>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index d6539723f354..45b767986a87 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -76,15 +76,13 @@ allOf: required: - compatible - rockchip,grf - - "#address-cells" - - "#size-cells" - - ranges patternProperties: "gpio@[0-9a-f]+$": type: object $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#" + deprecated: true unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml index 14a8c0215cc6..bc34e2c872bc 100644 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml# @@ -69,11 +70,17 @@ examples: - | // The UniPhier pinctrl should be a subnode of a "syscon" compatible node. - soc-glue@5f800000 { - compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; + pinctrl { + compatible = "socionext,uniphier-ld20-pinctrl"; + + pinctrl_ether_rgmii: ether-rgmii { + groups = "ether_rgmii"; + function = "ether_rgmii"; - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; + tx { + pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1", + "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL"; + drive-strength = <9>; + }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml new file mode 100644 index 000000000000..b470901f5f56 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 AON Pin Controller + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + + Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3 + can be multiplexed and have configurable bias, drive strength, + schmitt trigger etc. + Some peripherals such as PWM have their I/O go through the 4 "GPIOs". + +maintainers: + - Jianlong Huang <jianlong.huang@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-aon-pinctrl + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX macro. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x17020000 0x10000>; + resets = <&aoncrg 2>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + pwm-0 { + pwm-pins { + pinmux = <0xff030802>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file mode 100644 index 000000000000..222b9e240f8a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SYS Pin Controller + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63 + can be multiplexed and have configurable bias, drive strength, + schmitt trigger etc. + Some peripherals have their I/O go through the 64 "GPIOs". This also + includes a number of other UARTs, I2Cs, SPIs, PWMs etc. + All these peripherals are connected to all 64 GPIOs such that + any GPIO can be set up to be controlled by any of the peripherals. + +maintainers: + - Jianlong Huang <jianlong.huang@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-sys-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX or PINMUX + macros. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x13040000 0x10000>; + clocks = <&syscrg 112>; + resets = <&syscrg 2>; + interrupts = <86>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + uart0-0 { + tx-pins { + pinmux = <0xff140005>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = <0x0E000406>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml new file mode 100644 index 000000000000..46e2647a5d72 --- /dev/null +++ b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SoCs PPU power domain controller + +maintainers: + - Samuel Holland <samuel@sholland.org> + +description: + D1 and related SoCs contain a power domain controller for the CPUs, GPU, and + video-related hardware. + +properties: + compatible: + enum: + - allwinner,sun20i-d1-ppu + + reg: + maxItems: 1 + + clocks: + description: Bus Clock + maxItems: 1 + + resets: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - resets + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun20i-d1-r-ccu.h> + #include <dt-bindings/reset/sun20i-d1-r-ccu.h> + + ppu: power-controller@7001000 { + compatible = "allwinner,sun20i-d1-ppu"; + reg = <0x7001000 0x1000>; + clocks = <&r_ccu CLK_BUS_R_PPU>; + resets = <&r_ccu RST_BUS_R_PPU>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt index 99b5b10cda31..ba5865ae6bfe 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt +++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt @@ -1,5 +1,5 @@ -Amlogic Meson Power Controller -============================== +Amlogic Meson Power Controller (deprecated) +=========================================== The Amlogic Meson SoCs embeds an internal Power domain controller. diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml index 777e1d852ddd..c21a66422d4f 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml @@ -23,11 +23,16 @@ description: | properties: compatible: - enum: - - fsl,imx6q-gpc - - fsl,imx6qp-gpc - - fsl,imx6sl-gpc - - fsl,imx6sx-gpc + oneOf: + - enum: + - fsl,imx6q-gpc + - items: + - enum: + - fsl,imx6qp-gpc + - fsl,imx6sl-gpc + - fsl,imx6sx-gpc + - fsl,imx6ul-gpc + - const: fsl,imx6q-gpc reg: maxItems: 1 @@ -35,6 +40,10 @@ properties: interrupts: maxItems: 1 + interrupt-controller: true + '#interrupt-cells': + const: 3 + clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 605ec7ab5f63..c9acef80f452 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller - mediatek,mt8186-power-controller + - mediatek,mt8188-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller @@ -84,6 +85,7 @@ $defs: "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. + "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. maxItems: 1 diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml b/Documentation/devicetree/bindings/power/power-domain.yaml index 889091b9814f..d1235e562041 100644 --- a/Documentation/devicetree/bindings/power/power-domain.yaml +++ b/Documentation/devicetree/bindings/power/power-domain.yaml @@ -43,9 +43,6 @@ properties: domain would be considered as capable of being powered-on or powered-off. operating-points-v2: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - maxItems: 1 description: Phandles to the OPP tables of power domains provided by a power domain provider. If the provider provides a single power domain only or all diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 633d49884019..afad3135ed67 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -30,6 +30,7 @@ properties: - qcom,qcs404-rpmpd - qcom,qdu1000-rpmhpd - qcom,sa8540p-rpmhpd + - qcom,sa8775p-rpmhpd - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sc7280-rpmhpd @@ -39,7 +40,6 @@ properties: - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd - - qcom,sm4250-rpmpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml index da2509724812..75061124d9a8 100644 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml @@ -42,6 +42,9 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: The reset value written to the reboot register (32 bit access). + priority: + default: 192 + required: - compatible - offset @@ -49,6 +52,7 @@ required: additionalProperties: false allOf: + - $ref: restart-handler.yaml# - if: not: required: diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml new file mode 100644 index 000000000000..98eb8b4110e7 --- /dev/null +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/starfive,jh7110-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Power Management Unit + +maintainers: + - Walker Chen <walker.chen@starfivetech.com> + +description: | + StarFive JH7110 SoC includes support for multiple power domains which can be + powered on/off by software based on different application scenes to save power. + +properties: + compatible: + enum: + - starfive,jh7110-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#power-domain-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x17030000 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-coincell.yaml b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-coincell.yaml index 0450f4dd4e51..1d2405bea109 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-coincell.yaml +++ b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-coincell.yaml @@ -16,18 +16,30 @@ maintainers: properties: compatible: - const: qcom,pm8941-coincell + oneOf: + - items: + - enum: + - qcom,pm8998-coincell + - const: qcom,pm8941-coincell + + - const: qcom,pm8941-coincell reg: maxItems: 1 qcom,rset-ohms: - description: resistance (in ohms) for current-limiting resistor + description: | + Resistance (in ohms) for current-limiting resistor. If unspecified, + inherit the previous configuration (e.g. from bootloader or hardware + default value). enum: [ 800, 1200, 1700, 2100 ] qcom,vset-millivolts: $ref: /schemas/types.yaml#/definitions/uint32 - description: voltage (in millivolts) to apply for charging + description: | + Voltage (in millivolts) to apply for charging. If unspecified, inherit + the previous configuration (e.g. from bootloader or hardware default + value). enum: [ 2500, 3000, 3100, 3200 ] qcom,charger-disable: @@ -37,8 +49,6 @@ properties: required: - compatible - reg - - qcom,rset-ohms - - qcom,vset-millivolts additionalProperties: false diff --git a/Documentation/devicetree/bindings/power/supply/richtek,rt9467.yaml b/Documentation/devicetree/bindings/power/supply/richtek,rt9467.yaml new file mode 100644 index 000000000000..3723717dc1f6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/richtek,rt9467.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/richtek,rt9467.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9467 Switching Battery Charger with Power Path Management + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + - ChiaEn Wu <chiaen_wu@richtek.com> + +description: | + RT9467 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for + portable applications. It integrates a synchronous PWM controller, power + MOSFETs, input current sensing and regulation, high-accuracy voltage + regulation, and charge termination. The charge current is regulated through + integrated sensing resistors. + + The RT9467 also features USB On-The-Go (OTG) support. It also integrates + D+/D- pin for USB host/charging port detection. + + Datasheet is available at + https://www.richtek.com/assets/product_file/RT9467/DS9467-01.pdf + +properties: + compatible: + const: richtek,rt9467 + + reg: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + + charge-enable-gpios: + description: GPIO is used to turn on and off charging. + maxItems: 1 + + usb-otg-vbus-regulator: + type: object + description: OTG boost regulator. + unevaluatedProperties: false + $ref: /schemas/regulator/regulator.yaml# + + properties: + enable-gpios: true + +required: + - compatible + - reg + - wakeup-source + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@5b { + compatible = "richtek,rt9467"; + reg = <0x5b>; + wakeup-source; + interrupts-extended = <&gpio_intc 32 IRQ_TYPE_LEVEL_LOW>; + charge-enable-gpios = <&gpio26 1 GPIO_ACTIVE_LOW>; + + rt9467_otg_vbus: usb-otg-vbus-regulator { + regulator-name = "rt9467-usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/power/supply/richtek,rt9471.yaml b/Documentation/devicetree/bindings/power/supply/richtek,rt9471.yaml new file mode 100644 index 000000000000..fbb54cfeca08 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/richtek,rt9471.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/richtek,rt9471.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9471 3A Single Cell Switching Battery charger + +maintainers: + - Alina Yu <alina_yu@richtek.com> + - ChiYuan Huang <cy_huang@richtek.com> + +description: | + RT9471 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for + portable applications. It supports USB BC1.2 port detection, current and + voltage regulations in both charging and boost mode. + + Datasheet is available at + https://www.richtek.com/assets/product_file/RT9471=RT9471D/DS9471D-02.pdf + +properties: + compatible: + const: richtek,rt9471 + + reg: + maxItems: 1 + + charge-enable-gpios: + description: GPIO used to turn on and off charging. + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + + usb-otg-vbus-regulator: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - wakeup-source + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@53 { + compatible = "richtek,rt9471"; + reg = <0x53>; + charge-enable-gpios = <&gpio26 1 GPIO_ACTIVE_LOW>; + wakeup-source; + interrupts-extended = <&gpio_intc 32 IRQ_TYPE_EDGE_FALLING>; + + usb-otg-vbus-regulator { + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4850000>; + regulator-max-microvolt = <5300000>; + regulator-min-microamp = <500000>; + regulator-max-microamp = <1200000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt index c4d78f28d23c..3ff6ebbb4998 100644 --- a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt +++ b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt @@ -97,16 +97,6 @@ Nintendo Wii device tree - reg : should contain the EXI registers location and length - interrupts : should contain the EXI interrupt -1.g) The Open Host Controller Interface (OHCI) nodes - - Represent the USB 1.x Open Host Controller Interfaces. - - Required properties: - - - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci" - - reg : should contain the OHCI registers location and length - - interrupts : should contain the OHCI interrupt - 1.h) The Enhanced Host Controller Interface (EHCI) node Represents the USB 2.0 Enhanced Host Controller Interface. diff --git a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml new file mode 100644 index 000000000000..dbc974bff9e9 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PWM Controller + +maintainers: + - John Crispin <john@phrozen.org> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2712-pwm + - mediatek,mt6795-pwm + - mediatek,mt7622-pwm + - mediatek,mt7623-pwm + - mediatek,mt7628-pwm + - mediatek,mt7629-pwm + - mediatek,mt8183-pwm + - mediatek,mt8365-pwm + - mediatek,mt8516-pwm + - items: + - enum: + - mediatek,mt8195-pwm + - const: mediatek,mt8183-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 10 + + clock-names: + description: + This controller needs two input clocks for its core and one + clock for each PWM output. + minItems: 2 + items: + - const: top + - const: main + - const: pwm1 + - const: pwm2 + - const: pwm3 + - const: pwm4 + - const: pwm5 + - const: pwm6 + - const: pwm7 + - const: pwm8 + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt2712-clk.h> + #include <dt-bindings/interrupt-controller/irq.h> + + pwm0: pwm@11006000 { + compatible = "mediatek,mt2712-pwm"; + reg = <0x11006000 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM0>, <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>, + <&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>; + clock-names = "top", "main", + "pwm1", "pwm2", + "pwm3", "pwm4", + "pwm5", "pwm6", + "pwm7", "pwm8"; + }; diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml index 739d3155dd32..41cea4979132 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml @@ -63,8 +63,7 @@ properties: pinctrl-1: description: configuration for the sleep state - operating-points-v2: - $ref: /schemas/types.yaml#/definitions/phandle + operating-points-v2: true power-domains: items: diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt deleted file mode 100644 index 554c96b6d0c3..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ /dev/null @@ -1,52 +0,0 @@ -MediaTek PWM controller - -Required properties: - - compatible: should be "mediatek,<name>-pwm": - - "mediatek,mt2712-pwm": found on mt2712 SoC. - - "mediatek,mt6795-pwm": found on mt6795 SoC. - - "mediatek,mt7622-pwm": found on mt7622 SoC. - - "mediatek,mt7623-pwm": found on mt7623 SoC. - - "mediatek,mt7628-pwm": found on mt7628 SoC. - - "mediatek,mt7629-pwm": found on mt7629 SoC. - - "mediatek,mt8183-pwm": found on mt8183 SoC. - - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC. - - "mediatek,mt8365-pwm": found on mt8365 SoC. - - "mediatek,mt8516-pwm": found on mt8516 SoC. - - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of - the cell format. - - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following, except for MT7628 which - has no clocks - - "top": the top clock generator - - "main": clock used by the PWM core - - "pwm1-3": the three per PWM clocks for mt8365 - - "pwm1-8": the eight per PWM clocks for mt2712 - - "pwm1-6": the six per PWM clocks for mt7622 - - "pwm1-5": the five per PWM clocks for mt7623 - - "pwm1" : the PWM1 clock for mt7629 - - pinctrl-names: Must contain a "default" entry. - - pinctrl-0: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. - -Optional properties: -- assigned-clocks: Reference to the PWM clock entries. -- assigned-clock-parents: The phandle of the parent clock of PWM clock. - -Example: - pwm0: pwm@11006000 { - compatible = "mediatek,mt7623-pwm"; - reg = <0 0x11006000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM>, - <&pericfg CLK_PERI_PWM1>, - <&pericfg CLK_PERI_PWM2>, - <&pericfg CLK_PERI_PWM3>, - <&pericfg CLK_PERI_PWM4>, - <&pericfg CLK_PERI_PWM5>; - clock-names = "top", "main", "pwm1", "pwm2", - "pwm3", "pwm4", "pwm5"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml index 605c1766dba8..bae993128981 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml @@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive PWM controller maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> description: diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..9aabdb373afa --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks <ben.dooks@sifive.com> + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + pwm: pwm@180000 { + compatible = "snps,dw-apb-timers-pwm2"; + reg = <0x180000 0x200>; + #pwm-cells = <3>; + clocks = <&bus>, <&timer>; + clock-names = "bus", "timer"; + }; diff --git a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt deleted file mode 100644 index b9f58e480349..000000000000 --- a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt +++ /dev/null @@ -1,117 +0,0 @@ -ACT88xx regulators -------------------- - -Required properties: -- compatible: "active-semi,act8846" or "active-semi,act8865" or "active-semi,act8600" -- reg: I2C slave address - -Optional properties: -- system-power-controller: Telling whether or not this pmic is controlling - the system power. See Documentation/devicetree/bindings/power/power-controller.txt . -- active-semi,vsel-high: Indicates the VSEL pin is high. - If this property is missing, assume the VSEL pin is low(0). - -Optional input supply properties: -- for act8600: - - vp1-supply: The input supply for DCDC_REG1 - - vp2-supply: The input supply for DCDC_REG2 - - vp3-supply: The input supply for DCDC_REG3 - - inl-supply: The input supply for LDO_REG5, LDO_REG6, LDO_REG7 and LDO_REG8 - SUDCDC_REG4, LDO_REG9 and LDO_REG10 do not have separate supplies. -- for act8846: - - vp1-supply: The input supply for REG1 - - vp2-supply: The input supply for REG2 - - vp3-supply: The input supply for REG3 - - vp4-supply: The input supply for REG4 - - inl1-supply: The input supply for REG5, REG6 and REG7 - - inl2-supply: The input supply for REG8 and LDO_REG9 - - inl3-supply: The input supply for REG10, REG11 and REG12 -- for act8865: - - vp1-supply: The input supply for DCDC_REG1 - - vp2-supply: The input supply for DCDC_REG2 - - vp3-supply: The input supply for DCDC_REG3 - - inl45-supply: The input supply for LDO_REG1 and LDO_REG2 - - inl67-supply: The input supply for LDO_REG3 and LDO_REG4 - -Any standard regulator properties can be used to configure the single regulator. -regulator-initial-mode, regulator-allowed-modes and regulator-mode could be specified -for act8865 using mode values from dt-bindings/regulator/active-semi,8865-regulator.h -file. - -The valid names for regulators are: - - for act8846: - REG1, REG2, REG3, REG4, REG5, REG6, REG7, REG8, REG9, REG10, REG11, REG12 - - for act8865: - DCDC_REG1, DCDC_REG2, DCDC_REG3, LDO_REG1, LDO_REG2, LDO_REG3, LDO_REG4. - - for act8600: - DCDC_REG1, DCDC_REG2, DCDC_REG3, SUDCDC_REG4, LDO_REG5, LDO_REG6, LDO_REG7, - LDO_REG8, LDO_REG9, LDO_REG10, - -Example: --------- - -#include <dt-bindings/regulator/active-semi,8865-regulator.h> - - i2c1: i2c@f0018000 { - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - active-semi,vsel-high; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - - regulator-allowed-modes = <ACT8865_REGULATOR_MODE_FIXED>, - <ACT8865_REGULATOR_MODE_LOWPOWER>; - regulator-initial-mode = <ACT8865_REGULATOR_MODE_FIXED>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <1150000>; - regulator-suspend-max-microvolt = <1150000>; - regulator-changeable-in-suspend; - regulator-mode = <ACT8865_REGULATOR_MODE_LOWPOWER>; - }; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddana_reg: LDO_REG1 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-allowed-modes = <ACT8865_REGULATOR_MODE_NORMAL>, - <ACT8865_REGULATOR_MODE_LOWPOWER>; - regulator-initial-mode = <ACT8865_REGULATOR_MODE_NORMAL>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vddfuse_reg: LDO_REG2 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt b/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt deleted file mode 100644 index 4017527619ab..000000000000 --- a/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt +++ /dev/null @@ -1,113 +0,0 @@ -Device-Tree bindings for regulators of Active-semi ACT8945A Multi-Function Device - -Required properties: - - compatible: "active-semi,act8945a", please refer to ../mfd/act8945a.txt. - -Optional properties: -- active-semi,vsel-high: Indicates if the VSEL pin is set to logic-high. - If this property is missing, assume the VSEL pin is set to logic-low. - -Optional input supply properties: - - vp1-supply: The input supply for REG_DCDC1 - - vp2-supply: The input supply for REG_DCDC2 - - vp3-supply: The input supply for REG_DCDC3 - - inl45-supply: The input supply for REG_LDO1 and REG_LDO2 - - inl67-supply: The input supply for REG_LDO3 and REG_LDO4 - -Any standard regulator properties can be used to configure the single regulator. -regulator-initial-mode, regulator-allowed-modes and regulator-mode could be -specified using mode values from dt-bindings/regulator/active-semi,8945a-regulator.h -file. - -The valid names for regulators are: - REG_DCDC1, REG_DCDC2, REG_DCDC3, REG_LDO1, REG_LDO2, REG_LDO3, REG_LDO4. - -Example: - -#include <dt-bindings/regulator/active-semi,8945a-regulator.h> - - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - - active-semi,vsel-high; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - - regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, - <ACT8945A_REGULATOR_MODE_LOWPOWER>; - regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt=<1400000>; - regulator-suspend-max-microvolt=<1400000>; - regulator-changeable-in-suspend; - regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>; - }; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - - regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, - <ACT8945A_REGULATOR_MODE_LOWPOWER>; - regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - - regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, - <ACT8945A_REGULATOR_MODE_LOWPOWER>; - regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/active-semi,act8600.yaml b/Documentation/devicetree/bindings/regulator/active-semi,act8600.yaml new file mode 100644 index 000000000000..b8ca967bc83d --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/active-semi,act8600.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/active-semi,act8600.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Active-semi ACT8600 regulator + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + compatible: + const: active-semi,act8600 + + reg: + maxItems: 1 + + system-power-controller: + description: + Indicates that the ACT8600 is responsible for powering OFF + the system. + type: boolean + + active-semi,vsel-high: + description: + Indicates the VSEL pin is high. If this property is missing, + the VSEL pin is assumed to be low. + type: boolean + + regulators: + type: object + additionalProperties: false + + properties: + DCDC1: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp1-supply: + description: Handle to the VP1 input supply + + DCDC2: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp2-supply: + description: Handle to the VP2 input supply + + DCDC3: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp3-supply: + description: Handle to the VP3 input supply + + patternProperties: + "^(SUDCDC_REG4|LDO_REG9|LDO_REG10)$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + "^LDO[5-8]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl-supply: + description: Handle to the INL input supply + +additionalProperties: false + +required: + - reg + - compatible + - regulators + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@5a { + compatible = "active-semi,act8600"; + reg = <0x5a>; + + regulators { + SUDCDC_REG4 { + regulator-min-microvolt = <5300000>; + regulator-max-microvolt = <5300000>; + inl-supply = <&vcc>; + }; + + LDO5 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + inl-supply = <&vcc>; + }; + + LDO6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + inl-supply = <&vcc>; + }; + + LDO7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + inl-supply = <&vcc>; + }; + + LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + inl-supply = <&vcc>; + }; + + LDO_REG9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + inl-supply = <&vcc>; + }; + + LDO_REG10 { + inl-supply = <&vcc>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/active-semi,act8846.yaml b/Documentation/devicetree/bindings/regulator/active-semi,act8846.yaml new file mode 100644 index 000000000000..3725348bb235 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/active-semi,act8846.yaml @@ -0,0 +1,205 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/active-semi,act8846.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Active-semi ACT8846 regulator + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + compatible: + const: active-semi,act8846 + + reg: + maxItems: 1 + + system-power-controller: + description: + Indicates that the ACT8846 is responsible for powering OFF + the system. + type: boolean + + active-semi,vsel-high: + description: + Indicates the VSEL pin is high. If this property is missing, + the VSEL pin is assumed to be low. + type: boolean + + regulators: + type: object + additionalProperties: false + + properties: + REG1: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp1-supply: + description: Handle to the VP1 input supply + + REG2: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp2-supply: + description: Handle to the VP2 input supply + + REG3: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp3-supply: + description: Handle to the VP3 input supply + + REG4: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp4-supply: + description: Handle to the VP4 input supply + + patternProperties: + "^REG[5-7]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl1-supply: + description: Handle to the INL1 input supply + + "^REG[8-9]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl2-supply: + description: Handle to the INL2 input supply + + "^REG1[0-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl3-supply: + description: Handle to the INL3 input supply + +additionalProperties: false + +required: + - reg + - compatible + - regulators + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + + system-power-controller; + + regulators { + REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + REG7 { + regulator-name = "VCC_WL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + REG9 { + regulator-name = "VCC_LAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/active-semi,act8865.yaml b/Documentation/devicetree/bindings/regulator/active-semi,act8865.yaml new file mode 100644 index 000000000000..e8bf09faafb8 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/active-semi,act8865.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/active-semi,act8865.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Active-semi ACT8865 regulator + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + compatible: + const: active-semi,act8865 + + reg: + maxItems: 1 + + system-power-controller: + description: + Indicates that the ACT8865 is responsible for powering OFF + the system. + type: boolean + + active-semi,vsel-high: + description: + Indicates the VSEL pin is high. If this property is missing, + the VSEL pin is assumed to be low. + type: boolean + + regulators: + type: object + additionalProperties: false + + properties: + DCDC_REG1: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp1-supply: + description: Handle to the VP1 input supply + + DCDC_REG2: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp2-supply: + description: Handle to the VP2 input supply + + DCDC_REG3: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp3-supply: + description: Handle to the VP3 input supply + + patternProperties: + "^LDO_REG[1-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl45-supply: + description: Handle to the INL45 input supply + + "^LDO_REG[3-4]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl67-supply: + description: Handle to the INL67 input supply + +additionalProperties: false + +required: + - reg + - compatible + - regulators + +examples: + - | + #include <dt-bindings/regulator/active-semi,8865-regulator.h> + + i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + pmic@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + active-semi,vsel-high; + + regulators { + DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + + regulator-allowed-modes = <ACT8865_REGULATOR_MODE_FIXED>, + <ACT8865_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8865_REGULATOR_MODE_FIXED>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1150000>; + regulator-suspend-max-microvolt = <1150000>; + regulator-changeable-in-suspend; + regulator-mode = <ACT8865_REGULATOR_MODE_LOWPOWER>; + }; + }; + + DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + LDO_REG1 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-allowed-modes = <ACT8865_REGULATOR_MODE_NORMAL>, + <ACT8865_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8865_REGULATOR_MODE_NORMAL>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG2 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml b/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml new file mode 100644 index 000000000000..bdf3f7d34ef5 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml @@ -0,0 +1,258 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/active-semi,act8945a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Active-semi ACT8945a regulator + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + compatible: + const: active-semi,act8945a + + reg: + maxItems: 1 + + system-power-controller: + description: + Indicates that the ACT8945a is responsible for powering OFF + the system. + type: boolean + + active-semi,vsel-high: + description: + Indicates the VSEL pin is high. If this property is missing, + the VSEL pin is assumed to be low. + type: boolean + + regulators: + type: object + additionalProperties: false + + properties: + REG_DCDC1: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp1-supply: + description: Handle to the VP1 input supply + + REG_DCDC2: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp2-supply: + description: Handle to the VP2 input supply + + REG_DCDC3: + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + vp3-supply: + description: Handle to the VP3 input supply + + patternProperties: + "^REG_LDO[1-2]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl45-supply: + description: Handle to the INL45 input supply + + "^REG_LDO[3-4]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + inl67-supply: + description: Handle to the INL67 input supply + + charger: + type: object + additionalProperties: false + + properties: + compatible: + const: active-semi,act8945a-charger + + interrupts: + maxItems: 1 + + active-semi,chglev-gpios: + description: CGHLEV GPIO + maxItems: 1 + + active-semi,lbo-gpios: + description: LBO GPIO + maxItems: 1 + + active-semi,input-voltage-threshold-microvolt: + description: Input voltage threshold + maxItems: 1 + + active-semi,precondition-timeout: + description: Precondition timeout + $ref: /schemas/types.yaml#/definitions/uint32 + + active-semi,total-timeout: + description: Total timeout + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - compatible + - interrupts + +additionalProperties: false + +required: + - reg + - compatible + - regulators + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mfd/atmel-flexcom.h> + #include <dt-bindings/regulator/active-semi,8945a-regulator.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@5b { + compatible = "active-semi,act8945a"; + reg = <0x5b>; + active-semi,vsel-high; + + regulators { + REG_DCDC1 { + regulator-name = "VDD_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1400000>; + regulator-suspend-max-microvolt = <1400000>; + regulator-changeable-in-suspend; + regulator-mode = <ACT8945A_REGULATOR_MODE_LOWPOWER>; + }; + }; + + REG_DCDC2 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + REG_DCDC3 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + REG_LDO1 { + regulator-name = "VDD_FUSE"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + REG_LDO2 { + regulator-name = "VDD_3V3_LP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + REG_LDO3 { + regulator-name = "VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + REG_LDO4 { + regulator-name = "VDD_SDHC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + compatible = "active-semi,act8945a-charger"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; + interrupt-parent = <&pioA>; + interrupts = <45 IRQ_TYPE_EDGE_RISING>; + + active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; + active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; + active-semi,input-voltage-threshold-microvolt = <6600>; + active-semi,precondition-timeout = <40>; + active-semi,total-timeout = <3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/fan53555.txt b/Documentation/devicetree/bindings/regulator/fan53555.txt deleted file mode 100644 index 013f096ac0aa..000000000000 --- a/Documentation/devicetree/bindings/regulator/fan53555.txt +++ /dev/null @@ -1,24 +0,0 @@ -Binding for Fairchild FAN53555 regulators - -Required properties: - - compatible: one of "fcs,fan53555", "fcs,fan53526", "silergy,syr827", - "silergy,syr828" or "tcs,tcs4525". - - reg: I2C address - -Optional properties: - - fcs,suspend-voltage-selector: declare which of the two available - voltage selector registers should be used for the suspend - voltage. The other one is used for the runtime voltage setting - Possible values are either <0> or <1> - - vin-supply: regulator supplying the vin pin - -Example: - - regulator@40 { - compatible = "fcs,fan53555"; - regulator-name = "fan53555"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&parent_reg>; - fcs,suspend-voltage-selector = <1>; - }; diff --git a/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml new file mode 100644 index 000000000000..c0dbba843f70 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/fcs,fan53555.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fairchild FAN53555 regulators + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + enum: + - fcs,fan53555 + - fcs,fan53526 + - silergy,syr827 + - silergy,syr828 + - tcs,tcs4525 + + reg: + maxItems: 1 + + fcs,suspend-voltage-selector: + description: Declares which of the two available voltage selector + registers should be used for the suspend voltage. The other one is used + for the runtime voltage setting. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + + vin-supply: + description: Supply for the vin pin + + vsel-gpios: + description: Voltage Select. When this pin is LOW, VOUT is set by the + VSEL0 register. When this pin is HIGH, VOUT is set by the VSEL1 register. + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@40 { + compatible = "fcs,fan53555"; + reg = <0x40>; + regulator-name = "fan53555"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&parent_reg>; + fcs,suspend-voltage-selector = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml index 84eeaef179a5..48af7cba4652 100644 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml @@ -35,6 +35,10 @@ allOf: required: - power-domains - required-opps + - not: + required: + - gpio + - gpios properties: compatible: @@ -49,6 +53,9 @@ properties: description: gpio to use for enable control maxItems: 1 + gpios: + maxItems: 1 + clocks: description: clock to use for enable control. This binding is only available if diff --git a/Documentation/devicetree/bindings/regulator/maxim,max20411.yaml b/Documentation/devicetree/bindings/regulator/maxim,max20411.yaml new file mode 100644 index 000000000000..5b3a42d24e51 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/maxim,max20411.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/maxim,max20411.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX20411 Step-Down DC-DC Converter + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + The MAX20411 is a high-efficiency, DC-DC step-down converter. It provides + configurable output voltage in the range of 0.5V to 1.275V, configurable over + I2C. + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + const: maxim,max20411 + + reg: + maxItems: 1 + + enable-gpios: + description: GPIO connected to the EN pin, active high + + vdd-supply: + description: Input supply for the device (VDD pin, 3.0V to 5.5V) + +required: + - compatible + - reg + - enable-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + enable-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/mps,mpq7932.yaml b/Documentation/devicetree/bindings/regulator/mps,mpq7932.yaml new file mode 100644 index 000000000000..2185cd011c46 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mps,mpq7932.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mps,mpq7932.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Monolithic Power System MPQ7932 PMIC + +maintainers: + - Saravanan Sekar <saravanan@linumiz.com> + +properties: + compatible: + enum: + - mps,mpq7932 + + reg: + maxItems: 1 + + regulators: + type: object + description: | + list of regulators provided by this controller, must be named + after their hardware counterparts BUCK[1-6] + + patternProperties: + "^buck[1-6]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@3 { + compatible = "mps,mpq7932"; + reg = <0x3>; + + regulators { + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/qcom,rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,rpm-regulator.yaml new file mode 100644 index 000000000000..8a08698e3484 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qcom,rpm-regulator.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,rpm-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPM regulator + +description: + The Qualcomm RPM regulator is modelled as a subdevice of the RPM. + + Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml + for information regarding the RPM node. + + The regulator node houses sub-nodes for each regulator within the device. + Each sub-node is identified using the node's name, with valid values listed + for each of the pmics below. + + For pm8058 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, + l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, s0, s1, s2, s3, s4, + lvs0, lvs1, ncp + + For pm8901 l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3, + mvs + + For pm8921 s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l14, l15, l16, l17, l18, l21, l22, l23, l24, l25, l26, l27, l28, + l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch, + ncp + + For pm8018 s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l14, lvs1 + + For smb208 s1a, s1b, s2a, s2b + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +properties: + compatible: + enum: + - qcom,rpm-pm8058-regulators + - qcom,rpm-pm8901-regulators + - qcom,rpm-pm8921-regulators + - qcom,rpm-pm8018-regulators + - qcom,rpm-smb208-regulators + +patternProperties: + ".*-supply$": + description: Input supply phandle(s) for this node + + "^((s|l|lvs)[0-9]*)|(s[1-2][a-b])|(ncp)|(mvs)|(usb-switch)|(hdmi-switch)$": + description: List of regulators and its properties + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + bias-pull-down: + description: enable pull down of the regulator when inactive + type: boolean + + qcom,switch-mode-frequency: + description: Frequency (Hz) of the switch-mode power supply + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 19200000 + - 9600000 + - 6400000 + - 4800000 + - 3840000 + - 3200000 + - 2740000 + - 2400000 + - 2130000 + - 1920000 + - 1750000 + - 1600000 + - 1480000 + - 1370000 + - 1280000 + - 1200000 + + qcom,force-mode: + description: Indicates that the regulator should be forced to a particular mode + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # QCOM_RPM_FORCE_MODE_NONE do not force any mode + - 1 # QCOM_RPM_FORCE_MODE_LPM force into low power mode + - 2 # QCOM_RPM_FORCE_MODE_HPM force into high power mode + - 3 # QCOM_RPM_FORCE_MODE_AUTO allow regulator to automatically select its own mode + # based on realtime current draw, only for pm8921 smps and ftsmps + + qcom,power-mode-hysteretic: + description: select that the power supply should operate in hysteretic mode, + instead of the default pwm mode + type: boolean + +additionalProperties: false + +required: + - compatible + +examples: + - | + #include <dt-bindings/mfd/qcom-rpm.h> + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + + s1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + bias-pull-down; + + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + + qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml index dbe78cd4adba..b1cff3adb21b 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml @@ -33,7 +33,7 @@ examples: pm8150b { #address-cells = <1>; #size-cells = <0>; - pm8150b_vbus: dcdc@1100 { + pm8150b_vbus: usb-vbus-regulator@1100 { compatible = "qcom,pm8150b-vbus-reg"; reg = <0x1100>; }; diff --git a/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml index f97b8083678f..e987c39b223e 100644 --- a/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml @@ -20,7 +20,8 @@ properties: lab: type: object - additionalProperties: false + $ref: regulator.yaml# + unevaluatedProperties: false properties: qcom,soft-start-us: @@ -46,7 +47,8 @@ properties: ibb: type: object - additionalProperties: false + $ref: regulator.yaml# + unevaluatedProperties: false properties: qcom,discharge-resistor-kohms: diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml b/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml index 01f9d4e236e9..a7feb497eb89 100644 --- a/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml +++ b/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml @@ -19,8 +19,8 @@ description: | additional information and example. patternProperties: - # 25 LDOs - "^LDO([1-9]|[1][0-9]|2[0-5])$": + # 25 LDOs, without LDO10-12 + "^LDO([1-9]|1[3-9]|2[0-5])$": type: object $ref: regulator.yaml# unevaluatedProperties: false @@ -30,6 +30,23 @@ patternProperties: required: - regulator-name + "^LDO(1[0-2])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + properties: + samsung,ext-control-gpios: + maxItems: 1 + description: + LDO10, LDO11 and LDO12 can be configured to external control over + GPIO. + + required: + - regulator-name + # 5 bucks "^BUCK[1-5]$": type: object diff --git a/Documentation/devicetree/bindings/regulator/socionext,uniphier-regulator.yaml b/Documentation/devicetree/bindings/regulator/socionext,uniphier-regulator.yaml index c0acf949753d..a6949a581cd1 100644 --- a/Documentation/devicetree/bindings/regulator/socionext,uniphier-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/socionext,uniphier-regulator.yaml @@ -89,18 +89,11 @@ required: examples: - | - usb-glue@65b00000 { - compatible = "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_vbus0: regulators@100 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; + usb_vbus0: regulators@100 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index c1d9cbc359b4..643ee787a81f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -17,201 +17,52 @@ properties: compatible: enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-cdsp-pas - - qcom,qcs404-wcss-pas - - qcom,sc7180-mpss-pas - - qcom,sc7280-mpss-pas - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8180x-mpss-pas - - qcom,sc8280xp-adsp-pas - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - qcom,sdm660-adsp-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - - qcom,sdx55-mpss-pas - - qcom,sm6350-adsp-pas - - qcom,sm6350-cdsp-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas - - qcom,sm8150-mpss-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-cdsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-mpss-pas - - qcom,sm8450-slpi-pas reg: maxItems: 1 - clocks: - minItems: 1 - maxItems: 8 - - clock-names: - minItems: 1 - maxItems: 8 - - interconnects: - maxItems: 1 - - interrupts: - minItems: 5 - items: - - description: Watchdog interrupt - - description: Fatal interrupt - - description: Ready interrupt - - description: Handover interrupt - - description: Stop acknowledge interrupt - - description: Shutdown acknowledge interrupt - - interrupt-names: - minItems: 5 - items: - - const: wdog - - const: fatal - - const: ready - - const: handover - - const: stop-ack - - const: shutdown-ack - - resets: - minItems: 1 - maxItems: 3 - - reset-names: - minItems: 1 - maxItems: 3 - cx-supply: description: Phandle to the CX regulator px-supply: description: Phandle to the PX regulator - power-domains: - minItems: 1 - maxItems: 3 - - power-domain-names: - minItems: 1 - maxItems: 3 - - firmware-name: - $ref: /schemas/types.yaml#/definitions/string - description: Firmware name for the Hexagon core - - memory-region: - maxItems: 1 - description: Reference to the reserved-memory for the Hexagon core - qcom,qmp: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM. - qcom,smem-states: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: States used by the AP to signal the Hexagon core - items: - - description: Stop the modem - - qcom,smem-state-names: - description: The names of the state bits used for SMP2P output - items: - - const: stop - - qcom,halt-regs: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: Phandle reference to a syscon representing TCSR - - description: offsets within syscon for q6 halt registers - - description: offsets within syscon for modem halt registers - - description: offsets within syscon for nc halt registers - description: - Phandle reference to a syscon representing TCSR followed by the - three offsets within syscon for q6, modem and nc halt registers. - - smd-edge: - $ref: /schemas/remoteproc/qcom,smd-edge.yaml# - description: - Qualcomm Shared Memory subnode which represents communication edge, - channels and devices related to the ADSP. - unevaluatedProperties: false - - glink-edge: - $ref: /schemas/remoteproc/qcom,glink-edge.yaml# - description: - Qualcomm G-Link subnode which represents communication edge, channels - and devices related to the ADSP. + memory-region: + maxItems: 1 + description: Reference to the reserved-memory for the Hexagon core required: - compatible - - clocks - - clock-names - - interrupts - - interrupt-names - - memory-region - - qcom,smem-states - - qcom,smem-state-names -additionalProperties: false +unevaluatedProperties: false allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# - if: properties: compatible: contains: enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-wcss-pas - - qcom,sc7280-mpss-pas - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8180x-mpss-pas - - qcom,sc8280xp-adsp-pas - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - - qcom,sm6350-adsp-pas - - qcom,sm6350-cdsp-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas - - qcom,sm8150-mpss-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-cdsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-slpi-pas - - qcom,sm8450-mpss-pas then: properties: clocks: @@ -226,6 +77,7 @@ allOf: compatible: contains: enum: + - qcom,msm8996-slpi-pil - qcom,msm8998-slpi-pas then: properties: @@ -243,90 +95,15 @@ allOf: compatible: contains: enum: - - qcom,qcs404-cdsp-pas - then: - properties: - clocks: - items: - - description: XO clock - - description: SWAY clock - - description: TBU clock - - description: BIMC clock - - description: AHB AON clock - - description: Q6SS SLAVE clock - - description: Q6SS MASTER clock - - description: Q6 AXIM clock - clock-names: - items: - - const: xo - - const: sway - - const: tbu - - const: bimc - - const: ahb_aon - - const: q6ss_slave - - const: q6ss_master - - const: q6_axim - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc7180-mpss-pas - then: - properties: - clocks: - items: - - description: XO clock - - description: IFACE clock - - description: BUS clock - - description: NAC clock - - description: SNOC AXI clock - - description: MNOC AXI clock - clock-names: - items: - - const: xo - - const: iface - - const: bus - - const: nav - - const: snoc_axi - - const: mnoc_axi - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-cdsp-pas - - qcom,qcs404-wcss-pas - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8280xp-adsp-pas - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - - qcom,sm6350-adsp-pas - - qcom,sm6350-cdsp-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-cdsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-slpi-pas then: properties: interrupts: @@ -339,26 +116,6 @@ allOf: compatible: contains: enum: - - qcom,sc7180-mpss-pas - - qcom,sc7280-mpss-pas - - qcom,sc8180x-mpss-pas - - qcom,sdx55-mpss-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-mpss-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-mpss-pas - then: - properties: - interrupts: - minItems: 6 - interrupt-names: - minItems: 6 - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8974-adsp-pil then: required: @@ -370,10 +127,9 @@ allOf: contains: enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8998-adsp-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas then: properties: power-domains: @@ -406,169 +162,14 @@ allOf: compatible: contains: enum: - - qcom,sc7180-mpss-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MX power domain - - description: MSS power domain - power-domain-names: - items: - - const: cx - - const: mx - - const: mss - - - if: - properties: - compatible: - contains: - enum: - - qcom,sm6350-cdsp-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MX power domain - power-domain-names: - items: - - const: cx - - const: mx - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc7280-mpss-pas - - qcom,sdx55-mpss-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-mpss-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-mpss-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MSS power domain - power-domain-names: - items: - - const: cx - - const: mss - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8280xp-adsp-pas - - qcom,sm6350-adsp-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-slpi-pas - then: - properties: - power-domains: - items: - - description: LCX power domain - - description: LMX power domain - power-domain-names: - items: - - const: lcx - - const: lmx - - - if: - properties: - compatible: - contains: - enum: - - qcom,sm8350-cdsp-pas - - qcom,sm8450-cdsp-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MXC power domain - power-domain-names: - items: - - const: cx - - const: mxc - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - then: - properties: - power-domains: - items: - - description: NSP power domain - power-domain-names: - items: - - const: nsp - - - if: - properties: - compatible: - contains: - enum: - - qcom,qcs404-cdsp-pas - then: - properties: - resets: - items: - - description: CDSP restart - reset-names: - items: - - const: restart - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc7180-mpss-pas - - qcom,sc7280-mpss-pas - then: - properties: - resets: - items: - - description: MSS restart - - description: PDC reset - reset-names: - items: - - const: mss_restart - - const: pdc_reset - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-cdsp-pas - - qcom,qcs404-wcss-pas - qcom,sdm660-adsp-pas - - qcom,sdx55-mpss-pas then: properties: qcom,qmp: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml index 25c27464ef25..15e6851e1ff8 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml @@ -22,7 +22,7 @@ properties: required: - qcom,glink-channels description: - Qualcomm APR/GPR (Asynchronous/Generic Packet Router) + Qualcomm APR (Asynchronous Packet Router) fastrpc: $ref: /schemas/misc/qcom,fastrpc.yaml# @@ -31,11 +31,20 @@ properties: description: Qualcomm FastRPC + gpr: + $ref: /schemas/soc/qcom/qcom,apr.yaml# + required: + - qcom,glink-channels + description: + Qualcomm GPR (Generic Packet Router) + interrupts: maxItems: 1 label: - description: The names of the state bits used for SMP2P output + description: + Name of the edge, used for debugging and identification purposes. The + node name will be used if this is not present. mboxes: maxItems: 1 @@ -52,6 +61,21 @@ required: - mboxes - qcom,remote-pid +allOf: + - if: + required: + - apr + then: + properties: + gpr: false + + - if: + required: + - gpr + then: + properties: + apr: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml new file mode 100644 index 000000000000..f5a044e20c4e --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,glink-rpm-edge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm G-Link RPM edge + +description: | + Qualcomm G-Link edge, a FIFO based mechanism for communication with Resource + Power Manager (RPM) on various Qualcomm platforms. + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +properties: + compatible: + const: qcom,glink-rpm + + label: + $ref: /schemas/types.yaml#/definitions/string + description: + Name of the edge, used for debugging and identification purposes. The + node name will be used if this is not present. + + interrupts: + maxItems: 1 + + mboxes: + items: + - description: rpm_hlos mailbox in APCS + + qcom,remote-pid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The identifier for the remote processor as known by the rest of the + system. + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + RPM message memory resource (compatible: qcom,rpm-msg-ram). + + rpm-requests: + type: object + $ref: /schemas/soc/qcom/qcom,smd-rpm.yaml# + unevaluatedProperties: false + description: + Qualcomm Resource Power Manager (RPM) over G-Link + + properties: + qcom,intents: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 32 + items: + items: + - description: size of each intent to preallocate + - description: amount of intents to preallocate + minimum: 1 + description: + List of (size, amount) pairs describing what intents should be + preallocated for this virtual channel. This can be used to tweak the + default intents available for the channel to meet expectations of the + remote. + + required: + - qcom,glink-channels + +required: + - compatible + - interrupts + - mboxes + +anyOf: + - required: + - qcom,remote-pid + - required: + - qcom,rpm-msg-ram + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 0>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + rpm-requests { + compatible = "qcom,rpm-msm8996"; + qcom,glink-channels = "rpm_requests"; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml new file mode 100644 index 000000000000..6e6e69ad9cd7 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml @@ -0,0 +1,289 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8916 MSS Peripheral Image Loader (and similar) + +maintainers: + - Stephan Gerhold <stephan@gerhold.net> + +description: + This document describes the hardware for a component that loads and boots + firmware on the Qualcomm MSM8916 Modem Hexagon Core (and similar). + +properties: + compatible: + oneOf: + - enum: + - qcom,msm8909-mss-pil + - qcom,msm8916-mss-pil + - qcom,msm8953-mss-pil + - qcom,msm8974-mss-pil + + - const: qcom,q6v5-pil + description: Deprecated, prefer using qcom,msm8916-mss-pil + deprecated: true + + reg: + items: + - description: MSS QDSP6 registers + - description: RMB registers + + reg-names: + items: + - const: qdsp6 + - const: rmb + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + clocks: + items: + - description: Configuration interface (AXI) clock + - description: Configuration bus (AHB) clock + - description: Boot ROM (AHB) clock + - description: XO proxy clock (control handed over after startup) + + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: xo + + power-domains: + items: + - description: CX proxy power domain (control handed over after startup) + - description: MX proxy power domain (control handed over after startup) + - description: MSS proxy power domain (control handed over after startup) + (only valid for qcom,msm8953-mss-pil) + minItems: 2 + + power-domain-names: + items: + - const: cx + - const: mx + - const: mss # only valid for qcom,msm8953-mss-pil + minItems: 2 + + pll-supply: + description: PLL proxy supply (control handed over after startup) + + mss-supply: + description: MSS power domain supply (only valid for qcom,msm8974-mss-pil) + + resets: + items: + - description: MSS restart control + + reset-names: + items: + - const: mss_restart + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop modem + + qcom,smem-state-names: + description: Names of the states used by the AP to signal the Hexagon core + items: + - const: stop + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Halt registers are used to halt transactions of various sub-components + within MSS. + items: + - items: + - description: phandle to TCSR syscon region + - description: offset to the Q6 halt register + - description: offset to the modem halt register + - description: offset to the nc halt register + + memory-region: + items: + - description: MBA reserved region + - description: MPSS reserved region + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Name of MBA firmware + - description: Name of modem firmware + + bam-dmux: + $ref: /schemas/net/qcom,bam-dmux.yaml# + description: + Qualcomm BAM Data Multiplexer (provides network interface to the modem) + + smd-edge: + $ref: qcom,smd-edge.yaml# + description: + Qualcomm SMD subnode which represents communication edge, channels + and devices related to the DSP. + properties: + label: + enum: + - modem + - hexagon + unevaluatedProperties: false + + # Deprecated properties + cx-supply: + description: CX power domain regulator supply (prefer using power-domains) + deprecated: true + + mx-supply: + description: MX power domain regulator supply (prefer using power-domains) + deprecated: true + + mba: + type: object + description: + MBA reserved region (prefer using memory-region with two items) + properties: + memory-region: true + required: + - memory-region + deprecated: true + + mpss: + type: object + description: + MPSS reserved region (prefer using memory-region with two items) + properties: + memory-region: true + required: + - memory-region + deprecated: true + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - pll-supply + - resets + - reset-names + - qcom,halt-regs + - qcom,smem-states + - qcom,smem-state-names + - smd-edge + +allOf: + - if: + properties: + compatible: + const: qcom,msm8953-mss-pil + then: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + required: + - power-domains + - power-domain-names + else: + properties: + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + + - if: + properties: + compatible: + const: qcom,msm8974-mss-pil + then: + required: + - mss-supply + else: + properties: + mss-supply: false + + # Fallbacks for deprecated properties + - oneOf: + - required: + - memory-region + - required: + - mba + - mpss + - oneOf: + - required: + - power-domains + - power-domain-names + - required: + - cx-supply + - mx-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8916.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,msm8916-mss-pil"; + reg = <0x04080000 0x100>, <0x04020000 0x40>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + pll-supply = <&pm8916_l7>; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + memory-region = <&mba_mem>, <&mpss_mem>; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,smd-edge = <0>; + qcom,ipc = <&apcs 8 12>; + qcom,remote-pid = <1>; + + label = "hexagon"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml new file mode 100644 index 000000000000..c1ac6ca1e759 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml @@ -0,0 +1,393 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8996 MSS Peripheral Image Loader (and similar) + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Sibi Sankar <quic_sibis@quicinc.com> + +description: + MSS Peripheral Image Loader loads and boots firmware on the + Qualcomm Technology Inc. MSM8996 Modem Hexagon Core (and similar). + +properties: + compatible: + enum: + - qcom,msm8996-mss-pil + - qcom,msm8998-mss-pil + - qcom,sdm845-mss-pil + + reg: + items: + - description: MSS QDSP6 registers + - description: RMB registers + + reg-names: + items: + - const: qdsp6 + - const: rmb + + iommus: + items: + - description: MSA Stream 1 + - description: MSA Stream 2 + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + maxItems: 9 + + power-domains: + items: + - description: CX power domain + - description: MX power domain + - description: MSS power domain (only valid for qcom,sdm845-mss-pil) + minItems: 2 + + power-domain-names: + items: + - const: cx + - const: mx + - const: mss # only valid for qcom,sdm845-mss-pil + minItems: 2 + + pll-supply: + description: PLL supply + + resets: + items: + - description: AOSS restart + - description: PDC reset (only valid for qcom,sdm845-mss-pil) + minItems: 1 + + reset-names: + items: + - const: mss_restart + - const: pdc_reset # only valid for qcom,sdm845-mss-pil + minItems: 1 + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop modem + + qcom,smem-state-names: + description: Names of the states used by the AP to signal the Hexagon core + items: + - const: stop + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Halt registers are used to halt transactions of various sub-components + within MSS. + items: + - items: + - description: phandle to TCSR syscon region + - description: offset to the Q6 halt register + - description: offset to the modem halt register + - description: offset to the nc halt register + + memory-region: + items: + - description: MBA reserved region + - description: Modem reserved region + - description: Metadata reserved region + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Name of MBA firmware + - description: Name of modem firmware + + smd-edge: + $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + description: + Qualcomm Shared Memory subnode which represents communication edge, + channels and devices related to the Modem. + unevaluatedProperties: false + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + unevaluatedProperties: false + + # Deprecated properties + mba: + type: object + description: + MBA reserved region + + properties: + memory-region: true + + required: + - memory-region + + additionalProperties: false + deprecated: true + + mpss: + type: object + description: + MPSS reserved region + + properties: + memory-region: true + + required: + - memory-region + + additionalProperties: false + deprecated: true + + metadata: + type: object + description: + Metadata reserved region + + properties: + memory-region: true + + required: + - memory-region + + additionalProperties: false + deprecated: true + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - qcom,halt-regs + - qcom,smem-states + - qcom,smem-state-names + +allOf: + - if: + properties: + compatible: + const: qcom,msm8996-mss-pil + then: + properties: + clocks: + items: + - description: GCC MSS IFACE clock + - description: GCC MSS BUS clock + - description: GCC MSS MEM clock + - description: RPMH XO clock + - description: GCC MSS GPLL0 clock + - description: GCC MSS SNOC_AXI clock + - description: GCC MSS MNOC_AXI clock + - description: RPMH PNOC clock + - description: GCC MSS PRNG clock + - description: RPMH QDSS clock + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: xo + - const: gpll0_mss + - const: snoc_axi + - const: mnoc_axi + - const: pnoc + - const: qdss + glink-edge: false + required: + - pll-supply + - smd-edge + else: + properties: + pll-supply: false + smd-edge: false + + - if: + properties: + compatible: + const: qcom,msm8998-mss-pil + then: + properties: + clocks: + items: + - description: GCC MSS IFACE clock + - description: GCC MSS BUS clock + - description: GCC MSS MEM clock + - description: GCC MSS GPLL0 clock + - description: GCC MSS SNOC_AXI clock + - description: GCC MSS MNOC_AXI clock + - description: RPMH QDSS clock + - description: RPMH XO clock + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: gpll0_mss + - const: snoc_axi + - const: mnoc_axi + - const: qdss + - const: xo + required: + - glink-edge + + - if: + properties: + compatible: + const: qcom,sdm845-mss-pil + then: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + resets: + minItems: 2 + reset-names: + minItems: 2 + clocks: + items: + - description: GCC MSS IFACE clock + - description: GCC MSS BUS clock + - description: GCC MSS MEM clock + - description: GCC MSS GPLL0 clock + - description: GCC MSS SNOC_AXI clock + - description: GCC MSS MNOC_AXI clock + - description: GCC MSS PRNG clock + - description: RPMH XO clock + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: gpll0_mss + - const: snoc_axi + - const: mnoc_axi + - const: prng + - const: xo + required: + - qcom,qmp + - glink-edge + else: + properties: + iommus: false + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 + qcom,qmp: false + + # Fallbacks for deprecated properties + - oneOf: + - required: + - memory-region + - required: + - mba + - mpss + - metadata + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/reset/qcom,sdm845-aoss.h> + #include <dt-bindings/reset/qcom,sdm845-pdc.h> + + remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0x04080000 0x408>, <0x04180000 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + power-domains = <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "cx", "mx", "mss"; + + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml new file mode 100644 index 000000000000..171ef85de193 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,pas-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Peripheral Authentication Service Common Properties + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Common properties of Qualcomm SoCs Peripheral Authentication Service. + +properties: + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + interconnects: + maxItems: 1 + + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + power-domains: + minItems: 1 + maxItems: 3 + + power-domain-names: + minItems: 1 + maxItems: 3 + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the modem + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + items: + - const: stop + + smd-edge: + $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + description: + Qualcomm Shared Memory subnode which represents communication edge, + channels and devices related to the ADSP. + unevaluatedProperties: false + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the ADSP. + unevaluatedProperties: false + +required: + - clocks + - clock-names + - interrupts + - interrupt-names + - memory-region + - qcom,smem-states + - qcom,smem-state-names + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index d0ebd16ee0e1..573a88b60677 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -7,14 +7,8 @@ on the Qualcomm Hexagon core. Usage: required Value type: <string> Definition: must be one of: - "qcom,q6v5-pil", "qcom,ipq8074-wcss-pil" "qcom,qcs404-wcss-pil" - "qcom,msm8916-mss-pil", - "qcom,msm8974-mss-pil" - "qcom,msm8996-mss-pil" - "qcom,msm8998-mss-pil" - "qcom,sdm845-mss-pil" - reg: Usage: required @@ -35,26 +29,7 @@ on the Qualcomm Hexagon core. - interrupt-names: Usage: required Value type: <stringlist> - Definition: The interrupts needed depends on the compatible - string: - qcom,q6v5-pil: - qcom,ipq8074-wcss-pil: - qcom,qcs404-wcss-pil: - qcom,msm8916-mss-pil: - qcom,msm8974-mss-pil: - must be "wdog", "fatal", "ready", "handover", "stop-ack" - qcom,msm8996-mss-pil: - qcom,msm8998-mss-pil: - qcom,sdm845-mss-pil: - must be "wdog", "fatal", "ready", "handover", "stop-ack", - "shutdown-ack" - -- firmware-name: - Usage: optional - Value type: <stringlist> - Definition: must list the relative firmware image paths for mba and - modem. They are used for booting and authenticating the - Hexagon core. + Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" - clocks: Usage: required @@ -72,67 +47,23 @@ on the Qualcomm Hexagon core. "gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc", "lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc", "lcc_axim_cbc", "lcc_bcr_sleep" - qcom,q6v5-pil: - qcom,msm8916-mss-pil: - qcom,msm8974-mss-pil: - must be "iface", "bus", "mem", "xo" - qcom,msm8996-mss-pil: - must be "iface", "bus", "mem", "xo", "gpll0_mss", - "snoc_axi", "mnoc_axi", "pnoc", "qdss" - qcom,msm8998-mss-pil: - must be "iface", "bus", "mem", "xo", "gpll0_mss", - "snoc_axi", "mnoc_axi", "qdss" - qcom,sdm845-mss-pil: - must be "iface", "bus", "mem", "xo", "gpll0_mss", - "snoc_axi", "mnoc_axi", "prng" - resets: Usage: required Value type: <phandle> - Definition: reference to the reset-controller for the modem sub-system - reference to the list of 3 reset-controllers for the + Definition: reference to the list of 3 reset-controllers for the wcss sub-system - reference to the list of 2 reset-controllers for the modem - sub-system on SDM845 SoCs - reset-names: Usage: required Value type: <stringlist> - Definition: must be "mss_restart" for the modem sub-system - must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" + Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" for the wcss sub-system - must be "mss_restart", "pdc_reset" for the modem - sub-system on SDM845 SoCs -For devices where the mba and mpss sub-nodes are not specified, mba/mpss region -should be referenced as follows: - memory-region: Usage: required Value type: <phandle> - Definition: reference to the reserved-memory for the mba region followed - by the mpss region - -For the compatible strings below the following supplies are required: - "qcom,q6v5-pil" - "qcom,msm8916-mss-pil", -- cx-supply: (deprecated, use power domain instead) -- mx-supply: (deprecated, use power domain instead) -- pll-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core - -For the compatible string below the following supplies are required: - "qcom,msm8974-mss-pil" -- cx-supply: (deprecated, use power domain instead) -- mss-supply: -- mx-supply: (deprecated, use power domain instead) -- pll-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core + Definition: reference to wcss reserved-memory region. For the compatible string below the following supplies are required: "qcom,qcs404-wcss-pil" @@ -142,39 +73,6 @@ For the compatible string below the following supplies are required: Definition: reference to the regulators to be held on behalf of the booting of the Hexagon core -For the compatible string below the following supplies are required: - "qcom,msm8996-mss-pil" -- pll-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core - -- power-domains: - Usage: required - Value type: <phandle> - Definition: reference to power-domains that match power-domain-names - -- power-domain-names: - Usage: required - Value type: <stringlist> - Definition: The power-domains needed depend on the compatible string: - qcom,ipq8074-wcss-pil: - no power-domain names required - qcom,q6v5-pil: - qcom,msm8916-mss-pil: - qcom,msm8974-mss-pil: - qcom,msm8996-mss-pil: - qcom,msm8998-mss-pil: - must be "cx", "mx" - qcom,sdm845-mss-pil: - must be "cx", "mx", "mss" - -- qcom,qmp: - Usage: optional - Value type: <phandle> - Definition: reference to the AOSS side-channel message RAM. - - qcom,smem-states: Usage: required Value type: <phandle> @@ -190,16 +88,9 @@ For the compatible string below the following supplies are required: Usage: required Value type: <prop-encoded-array> Definition: a phandle reference to a syscon representing TCSR followed - by the three offsets within syscon for q6, modem and nc + by the three offsets within syscon for q6, wcss and nc halt registers. -The Hexagon node must contain iommus property as described in ../iommu/iommu.txt -on platforms which do not have TrustZone. - -= SUBNODES: -The Hexagon node must contain two subnodes, named "mba" and "mpss" representing -the memory regions used by the Hexagon firmware. Each sub-node must contain: - - memory-region: Usage: required Value type: <phandle> @@ -209,56 +100,3 @@ The Hexagon node may also have an subnode named either "smd-edge" or "glink-edge" that describes the communication edge, channels and devices related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and ../soc/qcom/qcom,glink.txt for details on how to describe these. - -= EXAMPLE -The following example describes the resources needed to boot control the -Hexagon, as it is found on MSM8974 boards. - - remoteproc@fc880000 { - compatible = "qcom,msm8974-mss-pil"; - reg = <0xfc880000 0x100>, <0xfc820000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - - qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - smd-edge { - interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - - label = "modem"; - }; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml new file mode 100644 index 000000000000..5efa0e5c0439 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS404 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm QCS404 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,qcs404-adsp-pas + - qcom,qcs404-cdsp-pas + - qcom,qcs404-wcss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + interrupts: + maxItems: 5 + + interrupt-names: + maxItems: 5 + + power-domains: false + power-domain-names: false + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + remoteproc@c700000 { + compatible = "qcom,qcs404-adsp-pas"; + reg = <0x0c700000 0x4040>; + + clocks = <&xo_board>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_fw_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + label = "adsp"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml index e4a7da8020f4..b1402bef0ebe 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml @@ -95,6 +95,7 @@ properties: items: - description: MBA reserved region - description: modem reserved region + - description: metadata reserved region firmware-name: $ref: /schemas/types.yaml#/definitions/string-array @@ -223,7 +224,7 @@ examples: <&rpmhpd SC7180_MSS>; power-domain-names = "cx", "mx", "mss"; - memory-region = <&mba_mem>, <&mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; qcom,qmp = <&aoss_qmp>; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml new file mode 100644 index 000000000000..5cefd2c58593 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7180/SC7280 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + + power-domains: + minItems: 2 + items: + - description: CX power domain + - description: MX power domain + - description: MSS power domain + + power-domain-names: + minItems: 2 + items: + - const: cx + - const: mx + - const: mss + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sc7180-mpss-pas + then: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + else: + properties: + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@4080000 { + compatible = "qcom,sc7180-mpss-pas"; + reg = <0x04080000 0x4040>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + memory-region = <&mpss_mem>; + + power-domains = <&rpmhpd SC7180_CX>, + <&rpmhpd SC7180_MX>, + <&rpmhpd SC7180_MSS>; + power-domain-names = "cx", "mx", "mss"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml new file mode 100644 index 000000000000..94ca7a0cc203 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 ADSP Peripheral Image Loader + +maintainers: + - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> + +description: + This document describes the hardware for a component that loads and boots firmware + on the Qualcomm Technology Inc. ADSP. + +properties: + compatible: + enum: + - qcom,sc7280-adsp-pil + + reg: + items: + - description: qdsp6ss register + - description: efuse q6ss register + + iommus: + items: + - description: Phandle to apps_smmu node with sid mask + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + clocks: + items: + - description: XO clock + - description: GCC CFG NOC LPASS clock + + clock-names: + items: + - const: xo + - const: gcc_cfg_noc_lpass + + power-domains: + items: + - description: LCX power domain + + resets: + items: + - description: PDC AUDIO SYNC RESET + - description: CC LPASS restart + + reset-names: + items: + - const: pdc_sync + - const: cc_lpass + + memory-region: + maxItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle reference to a syscon representing TCSR followed by the + four offsets within syscon for q6, modem, nc and qv6 halt registers. + items: + - items: + - description: phandle to TCSR_MUTEX registers + - description: offset to the Q6 halt register + - description: offset to the modem halt register + - description: offset to the nc halt register + - description: offset to the vq6 halt register + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the modem + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + const: stop + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + glink-edge: + $ref: qcom,glink-edge.yaml# + type: object + unevaluatedProperties: false + description: | + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the ADSP. + + properties: + label: + const: lpass + + gpr: true + apr: false + fastrpc: false + + required: + - label + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + - qcom,halt-regs + - memory-region + - qcom,smem-states + - qcom,smem-state-names + - qcom,qmp + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpass-sc7280.h> + #include <dt-bindings/reset/qcom,sdm845-aoss.h> + #include <dt-bindings/reset/qcom,sdm845-pdc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + + remoteproc@3000000 { + compatible = "qcom,sc7280-adsp-pil"; + reg = <0x03000000 0x5000>, + <0x0355b000 0x10>; + + interrupts-extended = <&pdc 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "xo", "gcc_cfg_noc_lpass"; + + power-domains = <&rpmhpd SC7280_LCX>; + + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, + <&aoss_reset AOSS_CC_LPASS_RESTART>; + reset-names = "pdc_sync", "cc_lpass"; + + qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + qcom,qmp = <&aoss_qmp>; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml index b4de0521a89d..005cb21732af 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml @@ -95,6 +95,7 @@ properties: items: - description: MBA reserved region - description: modem reserved region + - description: metadata reserved region firmware-name: $ref: /schemas/types.yaml#/definitions/string-array @@ -240,7 +241,7 @@ examples: <&rpmhpd SC7280_MSS>; power-domain-names = "cx", "mss"; - memory-region = <&mba_mem>, <&mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; qcom,qmp = <&aoss_qmp>; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml new file mode 100644 index 000000000000..c1f8dd8d0e4c --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180X Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + - qcom,sc8180x-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + else: + properties: + # TODO: incomplete + power-domains: false + power-domain-names: false + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml new file mode 100644 index 000000000000..f6fbc531dc28 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC8280XP SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sc8280xp-adsp-pas + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sc8280xp-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + else: + properties: + power-domains: + items: + - description: NSP power domain + power-domain-names: + items: + - const: nsp + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@3000000 { + compatible = "qcom,sc8280xp-adsp-pas"; + reg = <0x03000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + memory-region = <&pil_adsp_mem>; + + power-domains = <&rpmhpd SC8280XP_LCX>, + <&rpmhpd SC8280XP_LMX>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml new file mode 100644 index 000000000000..c66e298462c7 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sdx55-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDX55 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SDX55 SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sdx55-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + + power-domains: + items: + - description: CX power domain + - description: MSS power domain + + power-domain-names: + items: + - const: cx + - const: mss + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + memory-region = <&mpss_adsp_mem>; + + power-domains = <&rpmhpd SDX55_CX>, <&rpmhpd SDX55_MSS>; + power-domain-names = "cx", "mss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; + label = "mpss"; + mboxes = <&apcs 15>; + qcom,remote-pid = <1>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml new file mode 100644 index 000000000000..f5d1fa9f45f1 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm6115-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Peripheral Authentication Service + +maintainers: + - Bhupesh Sharma <bhupesh.sharma@linaro.org> + +description: + Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm6115-adsp-pas + - qcom,sm6115-cdsp-pas + - qcom,sm6115-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm6115-adsp-pas + - qcom,sm6115-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm6115-cdsp-pas + - qcom,sm6115-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + power-domain-names: + items: + - const: cx + + - if: + properties: + compatible: + enum: + - qcom,sm6115-adsp-pas + then: + properties: + power-domains: + items: + - description: LPI CX power domain + - description: LPI MX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@ab00000 { + compatible = "qcom,sm6115-adsp-pas"; + reg = <0x0ab00000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + firmware-name = "qcom/sm6115/adsp.mdt"; + + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&pil_adsp_mem>; + + power-domains = <&rpmpd SM6115_VDD_LPI_CX>, + <&rpmpd SM6115_VDD_LPI_MX>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + /* ... */ + + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml new file mode 100644 index 000000000000..fee02fa800b5 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM6350 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm6350-adsp-pas + - qcom,sm6350-cdsp-pas + - qcom,sm6350-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm6350-adsp-pas + - qcom,sm6350-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm6350-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm6350-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MX power domain + power-domain-names: + items: + - const: cx + - const: mx + + - if: + properties: + compatible: + enum: + - qcom,sm6350-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@3000000 { + compatible = "qcom,sm6350-adsp-pas"; + reg = <0x03000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&pil_adsp_mem>; + + power-domains = <&rpmhpd SM6350_LCX>, + <&rpmhpd SM6350_LMX>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml new file mode 100644 index 000000000000..2c085ac2c3fb --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8150-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150/SM8250 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8150/SM8250 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8150-adsp-pas + - qcom,sm8150-cdsp-pas + - qcom,sm8150-mpss-pas + - qcom,sm8150-slpi-pas + - qcom,sm8250-adsp-pas + - qcom,sm8250-cdsp-pas + - qcom,sm8250-slpi-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8150-adsp-pas + - qcom,sm8150-cdsp-pas + - qcom,sm8150-slpi-pas + - qcom,sm8250-adsp-pas + - qcom,sm8250-cdsp-pas + - qcom,sm8250-slpi-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm8150-adsp-pas + - qcom,sm8150-cdsp-pas + - qcom,sm8250-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + power-domain-names: + items: + - const: cx + + - if: + properties: + compatible: + enum: + - qcom,sm8150-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + + - if: + properties: + compatible: + enum: + - qcom,sm8150-slpi-pas + - qcom,sm8250-adsp-pas + - qcom,sm8250-slpi-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@17300000 { + compatible = "qcom,sm8150-adsp-pas"; + reg = <0x17300000 0x4040>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + firmware-name = "qcom/sm8150/adsp.mbn"; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>; + + power-domains = <&rpmhpd SM8150_CX>; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + + /* ... */ + + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml new file mode 100644 index 000000000000..af24f9a3cdf1 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8350-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350/SM8450 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8350/SM8450 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8350-mpss-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-mpss-pas + - qcom,sm8450-slpi-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-slpi-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm8350-mpss-pas + - qcom,sm8450-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + + - if: + properties: + compatible: + enum: + - qcom,sm8350-adsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-slpi-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm8350-cdsp-pas + - qcom,sm8450-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + power-domain-names: + items: + - const: cx + - const: mxc + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@30000000 { + compatible = "qcom,sm8450-adsp-pas"; + reg = <0x030000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + firmware-name = "qcom/sm8450/adsp.mbn"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>; + + power-domains = <&rpmhpd SM8450_LCX>, + <&rpmhpd SM8450_LMX>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml new file mode 100644 index 000000000000..fe216aa531ed --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + - qcom,sm8550-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + memory-region: + minItems: 2 + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + - description: DSM Memory region + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + maxItems: 2 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 3 + + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm8550-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + - if: + properties: + compatible: + enum: + - qcom,sm8550-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + - description: NSP power domain + power-domain-names: + items: + - const: cx + - const: mxc + - const: nsp + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + + remoteproc@30000000 { + compatible = "qcom,sm8550-adsp-pas"; + reg = <0x030000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>, <&dtb_adsp_mem>; + + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + + power-domains = <&rpmhpd_sm8550_lcx>, + <&rpmhpd_sm8550_lmx>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt deleted file mode 100644 index ac423f4c3f1b..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt +++ /dev/null @@ -1,177 +0,0 @@ -Qualcomm WCNSS Peripheral Image Loader - -This document defines the binding for a component that loads and boots firmware -on the Qualcomm WCNSS core. - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,riva-pil", - "qcom,pronto-v1-pil", - "qcom,pronto-v2-pil" - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: must specify the base address and size of the CCU, DXE and - PMU register blocks - -- reg-names: - Usage: required - Value type: <stringlist> - Definition: must be "ccu", "dxe", "pmu" - -- interrupts-extended: - Usage: required - Value type: <prop-encoded-array> - Definition: must list the watchdog and fatal IRQs and may specify the - ready, handover and stop-ack IRQs - -- interrupt-names: - Usage: required - Value type: <stringlist> - Definition: should be "wdog", "fatal", optionally followed by "ready", - "handover", "stop-ack" - -- firmware-name: - Usage: optional - Value type: <string> - Definition: must list the relative firmware image path for the - WCNSS core. Defaults to "wcnss.mdt". - -- vddmx-supply: (deprecated for qcom,pronto-v1/2-pil) -- vddcx-supply: (deprecated for qcom,pronto-v1/2-pil) -- vddpx-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the WCNSS core - -- power-domains: - Usage: required (for qcom,pronto-v1/2-pil) - Value type: <phandle> - Definition: reference to the power domains to be held on behalf of the - booting of the WCNSS core - -- power-domain-names: - Usage: required (for qcom,pronto-v1/2-pil) - Value type: <stringlist> - Definition: must be "cx", "mx" - -- qcom,smem-states: - Usage: optional - Value type: <prop-encoded-array> - Definition: reference to the SMEM state used to indicate to WCNSS that - it should shut down - -- qcom,smem-state-names: - Usage: optional - Value type: <stringlist> - Definition: should be "stop" - -- memory-region: - Usage: required - Value type: <prop-encoded-array> - Definition: reference to reserved-memory node for the remote processor - see ../reserved-memory/reserved-memory.txt - -= SUBNODES -A required subnode of the WCNSS PIL is used to describe the attached rf module -and its resource dependencies. It is described by the following properties: - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,wcn3620", - "qcom,wcn3660", - "qcom,wcn3660b", - "qcom,wcn3680" - -- clocks: - Usage: required - Value type: <prop-encoded-array> - Definition: should specify the xo clock and optionally the rf clock - -- clock-names: - Usage: required - Value type: <stringlist> - Definition: should be "xo", optionally followed by "rf" - -- vddxo-supply: -- vddrfa-supply: -- vddpa-supply: -- vdddig-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the WCNSS core - - -The wcnss node can also have an subnode named "smd-edge" that describes the SMD -edge, channels and devices related to the WCNSS. -See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge. - -= EXAMPLE -The following example describes the resources needed to boot control the WCNSS, -with attached WCN3680, as it is commonly found on MSM8974 boards. - -pronto@fb204000 { - compatible = "qcom,pronto-v2-pil"; - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - interrupts-extended = <&intc 0 149 1>, - <&wcnss_smp2p_slave 0 0>, - <&wcnss_smp2p_slave 1 0>, - <&wcnss_smp2p_slave 2 0>, - <&wcnss_smp2p_slave 3 0>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - power-domains = <&rpmpd MSM8974_VDDCX>, <&rpmpd MSM8974_VDDMX>; - power-domain-names = "cx", "mx"; - - vddpx-supply = <&pm8941_s3>; - - qcom,smem-states = <&wcnss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - memory-region = <&wcnss_region>; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - iris { - compatible = "qcom,wcn3680"; - - clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>; - clock-names = "xo", "rf"; - - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; - }; - - smd-edge { - interrupts = <0 142 1>; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - qcom,remote-pid = <4>; - - label = "pronto"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml new file mode 100644 index 000000000000..45eb42bd3c2c --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml @@ -0,0 +1,294 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,wcnss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WCNSS Peripheral Image Loader + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + This document defines the binding for a component that loads and boots + firmware on the Qualcomm WCNSS core. + +properties: + compatible: + description: + Append "qcom,pronto" if the device is actually pronto, and not riva + oneOf: + - items: + - enum: + - qcom,pronto-v1-pil + - qcom,pronto-v2-pil + - qcom,pronto-v3-pil + - const: qcom,pronto + - const: qcom,riva-pil + + reg: + maxItems: 3 + description: + The base address and size of the CCU, DXE and PMU register blocks + + reg-names: + items: + - const: ccu + - const: dxe + - const: pmu + + interrupts: + minItems: 2 + maxItems: 5 + + interrupt-names: + minItems: 2 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Relative firmware image path for the WCNSS core. Defaults to + "wcnss.mdt". + + vddpx-supply: + description: + PX regulator to be held on behalf of the booting of the WCNSS core + + vddmx-supply: + description: + MX regulator to be held on behalf of the booting of the WCNSS core. + + vddcx-supply: + description: + CX regulator to be held on behalf of the booting of the WCNSS core. + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: cx + - const: mx + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + States used by the AP to signal the WCNSS core that it should shutdown + items: + - description: Stop the modem + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + items: + - const: stop + + memory-region: + maxItems: 1 + description: reserved-memory for the WCNSS core + + smd-edge: + $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + description: + Qualcomm Shared Memory subnode which represents communication edge, + channels and devices related to the ADSP. + + iris: + type: object + description: + The iris subnode of the WCNSS PIL is used to describe the attached RF module + and its resource dependencies. + + properties: + compatible: + enum: + - qcom,wcn3620 + - qcom,wcn3660 + - qcom,wcn3660b + - qcom,wcn3680 + + clocks: + minItems: 1 + items: + - description: XO clock + - description: RF clock + + clock-names: + minItems: 1 + items: + - const: xo + - const: rf + + vddxo-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + vddrfa-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + vddpa-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + vdddig-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + required: + - compatible + - clocks + - clock-names + - vddxo-supply + - vddrfa-supply + - vddpa-supply + - vdddig-supply + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - iris + - vddpx-supply + - memory-region + - smd-edge + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,riva-pil + then: + required: + - vddcx-supply + - vddmx-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,pronto-v1-pil + - qcom,pronto-v2-pil + then: + properties: + vddmx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil + + vddcx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil + + oneOf: + - required: + - power-domains + - power-domain-names + - required: + - vddmx-supply + - vddcx-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,pronto-v3-pil + then: + properties: + vddmx-supply: false + vddcx-supply: false + + required: + - power-domains + - power-domain-names + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + pronto@a21b000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + + vddpx-supply = <&pm8916_l7>; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + memory-region = <&wcnss_region>; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + iris { + compatible = "qcom,wcn3620"; + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; + + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&pronto>; + + bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml index cedbc5efdc56..f16e90380df1 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -31,10 +31,12 @@ allOf: properties: compatible: enum: + - ti,am62a-c7xv-dsp - ti,j721e-c66-dsp - ti,j721e-c71-dsp - ti,j721s2-c71-dsp description: + Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs @@ -109,6 +111,7 @@ else: properties: compatible: enum: + - ti,am62a-c7xv-dsp - ti,j721e-c71-dsp - ti,j721s2-c71-dsp then: diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml new file mode 100644 index 000000000000..c6d86964b72a --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common TI PRU Consumer Binding + +maintainers: + - Suman Anna <s-anna@ti.com> + +description: | + A PRU application/consumer/user node typically uses one or more PRU device + nodes to implement a PRU application/functionality. Each application/client + node would need a reference to at least a PRU node, and optionally define + some properties needed for hardware/firmware configuration. The below + properties are a list of common properties supported by the PRU remoteproc + infrastructure. + + The application nodes shall define their own bindings like regular platform + devices, so below are in addition to each node's bindings. + +properties: + ti,prus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: phandles to the PRU, RTU or Tx_PRU nodes used + minItems: 1 + maxItems: 6 + items: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + minItems: 1 + maxItems: 6 + description: | + firmwares for the PRU cores, the default firmware for the core from + the PRU node will be used if not provided. The firmware names should + correspond to the PRU cores listed in the 'ti,prus' property + + ti,pruss-gp-mux-sel: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 6 + items: + enum: [0, 1, 2, 3, 4] + description: | + array of values for the GP_MUX_SEL under PRUSS_GPCFG register for a PRU. + This selects the internal muxing scheme for the PRU instance. Values + should correspond to the PRU cores listed in the 'ti,prus' property. The + GP_MUX_SEL setting is a per-slice setting (one setting for PRU0, RTU0, + and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the + same slice in the associative array. If the array size is smaller than + the size of 'ti,prus' property, the default out-of-reset value (0) for the + PRU core is used. + +required: + - ti,prus + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml b/Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml new file mode 100644 index 000000000000..05b6648b3458 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/framebuffer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: /reserved-memory framebuffer node bindings + +maintainers: + - devicetree-spec@vger.kernel.org + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: framebuffer + description: > + This indicates a region of memory meant to be used as a framebuffer for + a set of display devices. It can be used by an operating system to keep + the framebuffer from being overwritten and use it as the backing memory + for a display device (such as simple-framebuffer). + +unevaluatedProperties: false + +examples: + - | + / { + compatible = "foo"; + model = "foo"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&fb>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fb: framebuffer@80000000 { + compatible = "framebuffer"; + reg = <0x80000000 0x007e9000>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml index 2998f1c8f0db..08eb10c25821 100644 --- a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml @@ -27,9 +27,11 @@ properties: identifier of the client to use this region for buffers qcom,vmid: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array description: > - vmid of the remote processor, to set up memory protection + Array of vmids of the remote processors, to set up memory protection + minItems: 1 + maxItems: 2 required: - qcom,client-id diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml index 44f72bcf1782..c680e397cfd2 100644 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml @@ -31,17 +31,17 @@ properties: reg: true size: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 2 + oneOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - $ref: /schemas/types.yaml#/definitions/uint64 description: > Length based on parent's \#size-cells. Size in bytes of memory to reserve. alignment: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 2 + oneOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - $ref: /schemas/types.yaml#/definitions/uint64 description: > Length based on parent's \#size-cells. Address boundary for alignment of allocation. @@ -52,6 +52,30 @@ properties: Address and Length pairs. Specifies regions of memory that are acceptable to allocate from. + iommu-addresses: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: > + A list of phandle and specifier pairs that describe static IO virtual + address space mappings and carveouts associated with a given reserved + memory region. The phandle in the first cell refers to the device for + which the mapping or carveout is to be created. + + The specifier consists of an address/size pair and denotes the IO + virtual address range of the region for the given device. The exact + format depends on the values of the "#address-cells" and "#size-cells" + properties of the device referenced via the phandle. + + When used in combination with a "reg" property, an IOVA mapping is to + be established for this memory region. One example where this can be + useful is to create an identity mapping for physical memory that the + firmware has configured some hardware to access (such as a bootsplash + framebuffer). + + If no "reg" property is specified, the "iommu-addresses" property + defines carveout regions in the IOVA space for the given device. This + can be useful if a certain memory region should not be mapped through + the IOMMU. + no-map: type: boolean description: > @@ -89,12 +113,69 @@ allOf: - no-map oneOf: - - required: - - reg + - oneOf: + - required: + - reg + + - required: + - size + + - oneOf: + # IOMMU reservations + - required: + - iommu-addresses - - required: - - size + # IOMMU mappings + - required: + - reg + - iommu-addresses additionalProperties: true +examples: + - | + / { + compatible = "foo"; + model = "foo"; + + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + adsp_resv: reservation-adsp { + /* + * Restrict IOVA mappings for ADSP buffers to the 512 MiB region + * from 0x40000000 - 0x5fffffff. Anything outside is reserved by + * the ADSP for I/O memory and private memory allocations. + */ + iommu-addresses = <&adsp 0x0 0x00000000 0x00 0x40000000>, + <&adsp 0x0 0x60000000 0xff 0xa0000000>; + }; + + fb: framebuffer@90000000 { + reg = <0x0 0x90000000 0x0 0x00800000>; + iommu-addresses = <&dc0 0x0 0x90000000 0x0 0x00800000>; + }; + }; + + bus@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + + adsp: adsp@2990000 { + reg = <0x2990000 0x2000>; + memory-region = <&adsp_resv>; + }; + + dc0: display@15200000 { + reg = <0x15200000 0x10000>; + memory-region = <&fb>; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml b/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml index 0a2c13e1e230..fa253c518d79 100644 --- a/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml +++ b/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml @@ -95,19 +95,12 @@ required: examples: - | - usb-glue@65b00000 { - compatible = "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_rst: reset@0 { - compatible = "socionext,uniphier-ld20-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; + usb_rst: reset-controller@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; }; diff --git a/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml b/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml index 6566804ec567..033b252a3dfe 100644 --- a/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml +++ b/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml @@ -66,53 +66,7 @@ required: examples: - | - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - - // other nodes ... - }; - - - | - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - }; - - // other nodes ... - }; - - - | - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - - // other nodes ... - }; - - - | - adamv@57920000 { - compatible = "socionext,uniphier-ld11-adamv", "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - reset { - compatible = "socionext,uniphier-ld11-adamv-reset"; - #reset-cells = <1>; - }; - - // other nodes ... + reset-controller { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..001931d526ec 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -83,7 +83,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false @@ -114,6 +114,12 @@ properties: List of phandles to idle state nodes supported by this hart (see ./idle-states.yaml). + capacity-dmips-mhz: + description: + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + required: - riscv,isa - interrupt-controller diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 714d0fcab399..4a29c890619a 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: + - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp - microchip,mpfs-sev-kit - sundance,polarberry diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index bf3f07421f7e..eb6ab73c0f31 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Composable Cache Controller maintainers: - - Sagar Kadam <sagar.kadam@sifive.com> - - Paul Walmsley <paul.walmsley@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> description: The SiFive Composable Cache Controller is used to provide access to fast copies @@ -39,6 +38,10 @@ properties: - sifive,fu740-c000-ccache - const: cache - items: + - const: starfive,jh7110-ccache + - const: sifive,ccache0 + - const: cache + - items: - const: microchip,mpfs-ccache - const: sifive,fu540-c000-ccache - const: cache @@ -85,6 +88,7 @@ allOf: contains: enum: - sifive,fu740-c000-ccache + - starfive,jh7110-ccache - microchip,mpfs-ccache then: @@ -105,7 +109,9 @@ allOf: properties: compatible: contains: - const: sifive,fu740-c000-ccache + enum: + - sifive,fu740-c000-ccache + - starfive,jh7110-ccache then: properties: diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 5d3fcee52d59..cc4d92f0a1bf 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -24,6 +24,12 @@ properties: - starfive,visionfive-v1 - const: starfive,jh7100 + - items: + - enum: + - starfive,visionfive-2-v1.2a + - starfive,visionfive-2-v1.3b + - const: starfive,jh7110 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documentation/devicetree/bindings/riscv/sunxi.yaml new file mode 100644 index 000000000000..9edb5e5992b1 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sunxi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner RISC-V SoC-based boards + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Jernej Skrabec <jernej.skrabec@gmail.com> + - Samuel Holland <samuel@sholland.org> + +description: + Allwinner RISC-V SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Dongshan Nezha STU SoM + items: + - const: 100ask,dongshan-nezha-stu + - const: allwinner,sun20i-d1 + + - description: D1 Nezha board + items: + - const: allwinner,d1-nezha + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM and v3.14 board + items: + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion + items: + - const: clockwork,r-01-devterm-v3.14 + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: Lichee RV SoM + items: + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: Carrier boards for the Lichee RV SoM + items: + - enum: + - sipeed,lichee-rv-86-panel-480p + - sipeed,lichee-rv-86-panel-720p + - sipeed,lichee-rv-dock + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: MangoPi MQ board + items: + - const: widora,mangopi-mq + - const: allwinner,sun20i-d1s + + - description: MangoPi MQ Pro board + items: + - const: widora,mangopi-mq-pro + - const: allwinner,sun20i-d1 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml b/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml new file mode 100644 index 000000000000..2b76ce25acc4 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive SoC TRNG Module + +maintainers: + - Jia Jie Ho <jiajie.ho@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-trng + + reg: + maxItems: 1 + + clocks: + items: + - description: Hardware reference clock + - description: AHB reference clock + + clock-names: + items: + - const: hclk + - const: ahb + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - interrupts + +additionalProperties: false + +examples: + - | + rng: rng@1600C000 { + compatible = "starfive,jh7110-trng"; + reg = <0x1600C000 0x4000>; + clocks = <&clk 15>, <&clk 16>; + clock-names = "hclk", "ahb"; + resets = <&reset 3>; + interrupts = <30>; + }; +... diff --git a/Documentation/devicetree/bindings/rtc/amlogic,meson-vrtc.yaml b/Documentation/devicetree/bindings/rtc/amlogic,meson-vrtc.yaml new file mode 100644 index 000000000000..a89865fa676a --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/amlogic,meson-vrtc.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/amlogic,meson-vrtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Virtual RTC (VRTC) + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: | + This is a Linux interface to an RTC managed by firmware, hence it's + virtual from a Linux perspective. The interface is 1 register where + an alarm time (in seconds) is to be written. + The alarm register is a simple scratch register shared between the + application processors (AP) and the secure co-processor (SCP.) When + the AP suspends, the SCP will use the value of this register to + program an always-on timer before going sleep. When the timer expires, + the SCP will wake up and will then wake the AP. + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - amlogic,meson-vrtc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rtc@a8 { + compatible = "amlogic,meson-vrtc"; + reg = <0x000a8 0x4>; + }; diff --git a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml b/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml index 9fe079917a98..c6c57636c729 100644 --- a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml +++ b/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml @@ -11,7 +11,8 @@ maintainers: description: The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the - ability to wake up the system from low-power suspend/standby modes. + ability to wake up the system from low-power suspend/standby modes and + optionally generate RTC alarm interrupts. allOf: - $ref: "rtc.yaml#" @@ -24,8 +25,14 @@ properties: maxItems: 1 interrupts: - description: the TIMER interrupt - maxItems: 1 + minItems: 1 + items: + - description: the TIMER interrupt + - description: the ALARM interrupt + description: + The TIMER interrupt wakes the system from low-power suspend/standby modes. + An ALARM interrupt may be specified to interrupt the CPU when an RTC alarm + is enabled. clocks: description: clock reference in the 27MHz domain @@ -35,10 +42,10 @@ additionalProperties: false examples: - | - rtc@f0411580 { + rtc@f041a080 { compatible = "brcm,brcmstb-waketimer"; - reg = <0xf0411580 0x14>; - interrupts = <0x3>; - interrupt-parent = <&aon_pm_l2_intc>; + reg = <0xf041a080 0x14>; + interrupts-extended = <&aon_pm_l2_intc 0x04>, + <&upg_aux_aon_intr2_intc 0x08>; clocks = <&upg_fixed>; }; diff --git a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml index af78b67b3da4..de9879bdb317 100644 --- a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml @@ -11,6 +11,17 @@ maintainers: allOf: - $ref: rtc.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - ingenic,jz4770-rtc + - ingenic,jz4780-rtc + then: + properties: + "#clock-cells": false properties: compatible: @@ -39,6 +50,9 @@ properties: clock-names: const: rtc + "#clock-cells": + const: 0 + system-power-controller: description: | Indicates that the RTC is responsible for powering OFF @@ -83,3 +97,18 @@ examples: clocks = <&cgu JZ4740_CLK_RTC>; clock-names = "rtc"; }; + + - | + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> + rtc: rtc@10003000 { + compatible = "ingenic,jz4780-rtc", "ingenic,jz4760-rtc"; + reg = <0x10003000 0x4c>; + + interrupt-parent = <&intc>; + interrupts = <32>; + + clocks = <&cgu JZ4780_CLK_RTCLK>; + clock-names = "rtc"; + + #clock-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/rtc/microcrystal,rv3028.yaml b/Documentation/devicetree/bindings/rtc/microcrystal,rv3028.yaml new file mode 100644 index 000000000000..5ade5dfad048 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microcrystal,rv3028.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microcrystal,rv3028.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip RV-3028 RTC + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +properties: + compatible: + const: microcrystal,rv3028 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + trickle-resistor-ohms: + enum: + - 3000 + - 5000 + - 9000 + - 15000 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@51 { + compatible = "microcrystal,rv3028"; + reg = <0x51>; + pinctrl-0 = <&rtc_nint_pins>; + interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>; + trickle-resistor-ohms = <3000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt b/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt index c9d3ac1477fe..1374df7bf9d6 100644 --- a/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt @@ -3,15 +3,15 @@ MOXA ART real-time clock Required properties: - compatible : Should be "moxa,moxart-rtc" -- gpio-rtc-sclk : RTC sclk gpio, with zero flags -- gpio-rtc-data : RTC data gpio, with zero flags -- gpio-rtc-reset : RTC reset gpio, with zero flags +- rtc-sclk-gpios : RTC sclk gpio, with zero flags +- rtc-data-gpios : RTC data gpio, with zero flags +- rtc-reset-gpios : RTC reset gpio, with zero flags Example: rtc: rtc { compatible = "moxa,moxart-rtc"; - gpio-rtc-sclk = <&gpio 5 0>; - gpio-rtc-data = <&gpio 6 0>; - gpio-rtc-reset = <&gpio 7 0>; + rtc-sclk-gpios = <&gpio 5 0>; + rtc-data-gpios = <&gpio 6 0>; + rtc-reset-gpios = <&gpio 7 0>; }; diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml index cde7b1675ead..a1148eb22c24 100644 --- a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml @@ -14,7 +14,10 @@ maintainers: properties: compatible: - const: nxp,pcf2127 + enum: + - nxp,pca2129 + - nxp,pcf2127 + - nxp,pcf2129 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85363.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf85363.yaml new file mode 100644 index 000000000000..52aa3e2091e9 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85363.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,pcf85363.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Philips PCF85263/PCF85363 Real Time Clock + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - nxp,pcf85263 + - nxp,pcf85363 + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + interrupts: + maxItems: 1 + + quartz-load-femtofarads: + description: + The capacitive load of the quartz(x-tal). + enum: [6000, 7000, 12500] + default: 7000 + + start-year: true + wakeup-source: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@51 { + compatible = "nxp,pcf85363"; + reg = <0x51>; + #clock-cells = <0>; + quartz-load-femtofarads = <12500>; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml index a98b72752349..22909a96123e 100644 --- a/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml @@ -19,8 +19,6 @@ properties: - microcrystal,rv8564 - nxp,pca8565 - nxp,pcf8563 - - nxp,pcf85263 - - nxp,pcf85363 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml index 0a7aa29563c1..b95a69cc9ae0 100644 --- a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -40,6 +40,18 @@ properties: description: Indicates that the setting of RTC time is allowed by the host CPU. + nvmem-cells: + items: + - description: + four-byte nvmem cell holding a little-endian offset from the Unix + epoch representing the time when the RTC timer was last reset + + nvmem-cell-names: + items: + - const: offset + + wakeup-source: true + required: - compatible - reg @@ -67,6 +79,8 @@ examples: compatible = "qcom,pm8921-rtc"; reg = <0x11d>; interrupts = <0x27 0>; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; }; }; }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-meson-vrtc.txt b/Documentation/devicetree/bindings/rtc/rtc-meson-vrtc.txt deleted file mode 100644 index c014f54a9853..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-meson-vrtc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Amlogic Virtual RTC (VRTC) - -This is a Linux interface to an RTC managed by firmware, hence it's -virtual from a Linux perspective. The interface is 1 register where -an alarm time (in seconds) is to be written. - -Required properties: -- compatible: should be "amlogic,meson-vrtc" -- reg: physical address for the alarm register - -The alarm register is a simple scratch register shared between the -application processors (AP) and the secure co-processor (SCP.) When -the AP suspends, the SCP will use the value of this register to -program an always-on timer before going sleep. When the timer expires, -the SCP will wake up and will then wake the AP. - -Example: - - vrtc: rtc@0a8 { - compatible = "amlogic,meson-vrtc"; - reg = <0x0 0x000a8 0x0 0x4>; - }; diff --git a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml index d9fc120c61cc..eb75861c28c3 100644 --- a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml @@ -47,14 +47,12 @@ properties: - isil,isl1218 # Intersil ISL12022 Real-time Clock - isil,isl12022 - # Real Time Clock Module with I2C-Bus - - microcrystal,rv3028 + # Loongson-2K Socs/LS7A bridge Real-time Clock + - loongson,ls2x-rtc # Real Time Clock Module with I2C-Bus - microcrystal,rv3029 # Real Time Clock - microcrystal,rv8523 - - nxp,pca2129 - - nxp,pcf2129 # Real-time Clock Module - pericom,pt7c4338 # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index 34b8e59aa9d4..692aa05500fd 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: serial.yaml# + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# - if: anyOf: - required: @@ -62,7 +63,6 @@ properties: - const: mrvl,pxa-uart - const: nuvoton,wpcm450-uart - const: nuvoton,npcm750-uart - - const: nuvoton,npcm845-uart - const: nvidia,tegra20-uart - const: nxp,lpc3220-uart - items: @@ -94,6 +94,10 @@ properties: - ns16550a - items: - enum: + - nuvoton,npcm845-uart + - const: nuvoton,npcm750-uart + - items: + - enum: - ralink,mt7620a-uart - ralink,rt3052-uart - ralink,rt3883-uart @@ -200,12 +204,13 @@ properties: deprecated: true aspeed,lpc-io-reg: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 description: | The VUART LPC address. Only applicable to aspeed,ast2500-vuart. aspeed,lpc-interrupts: - $ref: "/schemas/types.yaml#/definitions/uint32-array" + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 maxItems: 2 description: | diff --git a/Documentation/devicetree/bindings/serial/8250_omap.yaml b/Documentation/devicetree/bindings/serial/8250_omap.yaml index 53dc1212ad2e..eb3488d8f9ee 100644 --- a/Documentation/devicetree/bindings/serial/8250_omap.yaml +++ b/Documentation/devicetree/bindings/serial/8250_omap.yaml @@ -70,11 +70,6 @@ properties: dsr-gpios: true rng-gpios: true dcd-gpios: true - rs485-rts-delay: true - rs485-rts-active-low: true - rs485-rx-during-tx: true - rs485-rts-active-high: true - linux,rs485-enabled-at-boot-time: true rts-gpio: true power-domains: true clock-frequency: true @@ -109,12 +104,12 @@ else: examples: - | - serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; + serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 7822705ad16c..3cbdde85ed71 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -19,6 +19,9 @@ description: | is active since power-on and does not need any clock gating and is usable as very early serial console. +allOf: + - $ref: serial.yaml# + properties: compatible: oneOf: @@ -69,14 +72,14 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x84c0 0x14>; - interrupts = <26>; - clocks = <&xtal>, <&pclk>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; + compatible = "amlogic,meson-gx-uart"; + reg = <0x84c0 0x14>; + interrupts = <26>; + clocks = <&xtal>, <&pclk>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; }; diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index 876b8cf1cafb..a8b323d7bf94 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -9,9 +9,6 @@ title: Cadence UART Controller maintainers: - Michal Simek <michal.simek@xilinx.com> -allOf: - - $ref: /schemas/serial.yaml# - properties: compatible: oneOf: @@ -46,6 +43,9 @@ properties: port does not use this pin. type: boolean + power-domains: + maxItems: 1 + required: - compatible - reg @@ -53,14 +53,25 @@ required: - clocks - clock-names +allOf: + - $ref: serial.yaml# + - if: + properties: + compatible: + contains: + const: cdns,uart-r1p8 + then: + properties: + power-domains: false + unevaluatedProperties: false examples: - | uart0: serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - clocks = <&clkc 23>, <&clkc 40>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "uart_clk", "pclk"; + reg = <0xe0000000 0x1000>; + interrupts = <0 27 4>; }; diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml index 8b643bae3c7b..920539926d7e 100644 --- a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml @@ -16,7 +16,7 @@ maintainers: - Chester Lin <clin@suse.com> allOf: - - $ref: "serial.yaml" + - $ref: serial.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml index 9d949296a142..4cbe76e1715b 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml @@ -10,8 +10,8 @@ maintainers: - Fabio Estevam <festevam@gmail.com> allOf: - - $ref: "serial.yaml" - - $ref: "rs485.yaml" + - $ref: serial.yaml# + - $ref: rs485.yaml# properties: compatible: @@ -83,13 +83,6 @@ properties: are sensible for most use cases. If you need low latency processing on slow connections this needs to be configured appropriately. - uart-has-rtscts: true - - rs485-rts-delay: true - rs485-rts-active-low: true - rs485-rx-during-tx: true - linux,rs485-enabled-at-boot-time: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index 74f75f669e77..ab81722293d3 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -10,7 +10,8 @@ maintainers: - Fugang Duan <fugang.duan@nxp.com> allOf: - - $ref: "rs485.yaml" + - $ref: rs485.yaml# + - $ref: serial.yaml# properties: compatible: @@ -64,9 +65,6 @@ properties: - const: rx - const: tx - rs485-rts-active-low: true - linux,rs485-enabled-at-boot-time: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml index 14c7594c88c6..6a400a5e6fc7 100644 --- a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml @@ -10,7 +10,7 @@ maintainers: - Fabio Estevam <festevam@gmail.com> allOf: - - $ref: "serial.yaml" + - $ref: serial.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index 80af72859876..9571041030b7 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -10,6 +10,7 @@ maintainers: - Rob Herring <robh@kernel.org> allOf: + - $ref: /schemas/arm/primecell.yaml# - $ref: serial.yaml# # Need a custom select here or 'arm,primecell' will match on lots of nodes diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt deleted file mode 100644 index ce8c90161959..000000000000 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt +++ /dev/null @@ -1,25 +0,0 @@ -* MSM Serial UART - -The MSM serial UART hardware is designed for low-speed use cases where a -dma-engine isn't needed. From a software perspective it's mostly compatible -with the MSM serial UARTDM except that it only supports reading and writing one -character at a time. - -Required properties: -- compatible: Should contain "qcom,msm-uart" -- reg: Should contain UART register location and length. -- interrupts: Should contain UART interrupt. -- clocks: Should contain the core clock. -- clock-names: Should be "core". - -Example: - -A uart device at 0xa9c00000 with interrupt 11. - -serial@a9c00000 { - compatible = "qcom,msm-uart"; - reg = <0xa9c00000 0x1000>; - interrupts = <11>; - clocks = <&uart_cxc>; - clock-names = "core"; -}; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml new file mode 100644 index 000000000000..a052aaef21f4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM SoC Serial UART + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: + The MSM serial UART hardware is designed for low-speed use cases where a + dma-engine isn't needed. From a software perspective it's mostly compatible + with the MSM serial UARTDM except that it only supports reading and writing + one character at a time. + +properties: + compatible: + const: qcom,msm-uart + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clock-names + - clocks + - interrupts + - reg + +unevaluatedProperties: false + +allOf: + - $ref: /schemas/serial/serial.yaml# + +examples: + - | + serial@a9c00000 { + compatible = "qcom,msm-uart"; + reg = <0xa9c00000 0x1000>; + interrupts = <11>; + clocks = <&uart_cxc>; + clock-names = "core"; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml index b25aca733b72..12d0fa34f9f9 100644 --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml @@ -66,9 +66,9 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> uart0: serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; + compatible = "renesas,em-uart"; + reg = <0xe1020000 0x38>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml index 1957b9d782e8..afedb6edfc34 100644 --- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml @@ -131,20 +131,20 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7795-sysc.h> aliases { - serial1 = &hscif1; + serial1 = &hscif1; }; hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0xe6550000 96>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; - uart-has-rtscts; + compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0xe6550000 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; + uart-has-rtscts; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml index bf7708a7a2c0..dc445b327e0b 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml @@ -91,19 +91,19 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> aliases { - serial0 = &sci0; + serial0 = &sci0; }; sci0: serial@1004d000 { - compatible = "renesas,r9a07g044-sci", "renesas,sci"; - reg = <0x1004d000 0x400>; - interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCI0_RST>; + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0x1004d000 0x400>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI0_RST>; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index f81f2d67a1ed..1989bd67d04e 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -180,19 +180,19 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7791-sysc.h> aliases { - serial0 = &scif0; + serial0 = &scif0; }; scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0xe6e60000 64>; - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; + compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0xe6e60000 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml index 3c67d3202e1b..4c3b5e7270da 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml @@ -95,18 +95,18 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7790-sysc.h> aliases { - serial0 = &scifa0; + serial0 = &scifa0; }; scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", - "renesas,scifa"; - reg = <0xe6c40000 64>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; + compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", + "renesas,scifa"; + reg = <0xe6c40000 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml index d5571c7a4424..2f7cbbb48960 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml @@ -94,10 +94,10 @@ examples: #include <dt-bindings/clock/r8a7740-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> scifb: serial@e6c30000 { - compatible = "renesas,scifb-r8a7740", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; + compatible = "renesas,scifb-r8a7740", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; }; diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml index 789763cf427a..303a443d9e29 100644 --- a/Documentation/devicetree/bindings/serial/rs485.yaml +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -51,6 +51,12 @@ properties: description: GPIO pin to enable RS485 bus termination. maxItems: 1 + rs485-rx-during-tx-gpios: + description: Output GPIO pin that sets the state of rs485-rx-during-tx. This + signal can be used to control the RX part of an RS485 transceiver. Thereby + the active state enables RX during TX. + maxItems: 1 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml index 11e822bf09e2..c9231e501f1f 100644 --- a/Documentation/devicetree/bindings/serial/serial.yaml +++ b/Documentation/devicetree/bindings/serial/serial.yaml @@ -96,7 +96,7 @@ then: rts-gpios: false patternProperties: - ".*": + "^bluetooth|gnss|gps|mcu$": if: type: object then: @@ -141,13 +141,13 @@ additionalProperties: true examples: - | serial@1234 { - compatible = "ns16550a"; - reg = <0x1234 0x20>; - interrupts = <1>; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - interrupt-parent = <&gpio>; - interrupts = <10>; - }; + compatible = "ns16550a"; + reg = <0x1234 0x20>; + interrupts = <1>; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + interrupt-parent = <&gpio>; + interrupts = <10>; + }; }; diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index b0a8871e3641..b0df1cac4968 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -53,13 +53,13 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/clock/sifive-fu540-prci.h> - serial@10010000 { + #include <dt-bindings/clock/sifive-fu540-prci.h> + serial@10010000 { compatible = "sifive,fu540-c000-uart", "sifive,uart0"; interrupt-parent = <&plic0>; interrupts = <80>; reg = <0x10010000 0x1000>; clocks = <&prci FU540_PRCI_CLK_TLCLK>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index b9c2287c5d1e..2becdfab4f15 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -67,6 +67,14 @@ properties: - const: baudclk - const: apb_pclk + dmas: + minItems: 2 + + dma-names: + items: + - const: rx + - const: tx + snps,uart-16550-compatible: description: reflects the value of UART_16550_COMPATIBLE configuration parameter. Define this if your UART does not implement the busy functionality. diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 85876c668f6d..1df8ffe95fc6 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -35,8 +35,6 @@ properties: description: enable hardware flow control (deprecated) $ref: /schemas/types.yaml#/definitions/flag - uart-has-rtscts: true - rx-tx-swap: true dmas: @@ -60,11 +58,6 @@ properties: wakeup-source: true - rs485-rts-delay: true - rs485-rts-active-low: true - linux,rs485-enabled-at-boot-time: true - rs485-rx-during-tx: true - rx-threshold: description: If value is set to 1, RX FIFO threshold is disabled. diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml index 2f4390e8d4e8..08dcb275d8e2 100644 --- a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml @@ -63,7 +63,7 @@ required: - xlnx,use-parity allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# - if: properties: xlnx,use-parity: @@ -76,7 +76,7 @@ unevaluatedProperties: false examples: - | - serial@800c0000 { + serial@800c0000 { compatible = "xlnx,xps-uartlite-1.00.a"; reg = <0x800c0000 0x10000>; interrupts = <0x0 0x6e 0x1>; @@ -84,5 +84,5 @@ examples: current-speed = <115200>; xlnx,data-bits = <8>; xlnx,use-parity = <0>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml new file mode 100644 index 000000000000..1da1b758b4ae --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IOMUX Controller General Purpose Registers + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: + i.MX Processors have an IOMUXC General Purpose Register group for + various System Settings + +properties: + compatible: + oneOf: + - items: + - const: fsl,imx8mq-iomuxc-gpr + - const: syscon + - const: simple-mfd + - items: + - enum: + - fsl,imx8mm-iomuxc-gpr + - fsl,imx8mn-iomuxc-gpr + - fsl,imx8mp-iomuxc-gpr + - const: syscon + + reg: + maxItems: 1 + + mux-controller: + type: object + $ref: /schemas/mux/reg-mux.yaml + +additionalProperties: false + +required: + - compatible + - reg + +examples: + # Pinmux controller node + - | + iomuxc_gpr: syscon@30340000 { + compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd"; + reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ + }; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml index c29181a9745b..1fe68b53b1d8 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -39,6 +39,9 @@ properties: - const: pcie - const: pcie-phy + '#clock-cells': + const: 0 + clocks: minItems: 2 maxItems: 2 @@ -85,4 +88,5 @@ examples: power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; #power-domain-cells = <1>; + #clock-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 9241e5fc7cff..15c133cac315 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8183-disp-mutex - mediatek,mt8186-disp-mutex - mediatek,mt8186-mdp3-mutex + - mediatek,mt8188-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml new file mode 100644 index 000000000000..3fefd634bc69 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek PMIC Wrapper + +maintainers: + - Flora Fu <flora.fu@mediatek.com> + - Alexandre Mergnat <amergnat@baylibre.com> + +description: + On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface + is not directly visible to the CPU, but only through the PMIC wrapper + inside the SoC. The communication between the SoC and the PMIC can + optionally be encrypted. Also a non standard Dual IO SPI mode can be + used to increase speed. + + IP Pairing + + On MT8135 the pins of some SoC internal peripherals can be on the PMIC. + The signals of these pins are routed over the SPI bus using the pwrap + bridge. In the binding description below the properties needed for bridging + are marked with "IP Pairing". These are optional on SoCs which do not support + IP Pairing + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-pwrap + - mediatek,mt6765-pwrap + - mediatek,mt6779-pwrap + - mediatek,mt6797-pwrap + - mediatek,mt6873-pwrap + - mediatek,mt7622-pwrap + - mediatek,mt8135-pwrap + - mediatek,mt8173-pwrap + - mediatek,mt8183-pwrap + - mediatek,mt8186-pwrap + - mediatek,mt8188-pwrap + - mediatek,mt8195-pwrap + - mediatek,mt8365-pwrap + - mediatek,mt8516-pwrap + - items: + - enum: + - mediatek,mt8186-pwrap + - mediatek,mt8195-pwrap + - const: syscon + + reg: + minItems: 1 + items: + - description: PMIC wrapper registers + - description: IP pairing registers + + reg-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + items: + - description: SPI bus clock + - description: Main module clock + - description: System module clock + - description: Timer module clock + + clock-names: + minItems: 2 + items: + - const: spi + - const: wrap + - const: sys + - const: tmr + + resets: + minItems: 1 + items: + - description: PMIC wrapper reset + - description: IP pairing reset + + reset-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + pmic: + type: object + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +dependentRequired: + resets: [reset-names] + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8365-pwrap + then: + properties: + clocks: + minItems: 4 + + clock-names: + minItems: 4 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/mt8135-resets.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt deleted file mode 100644 index 12e4b4260b40..000000000000 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ /dev/null @@ -1,75 +0,0 @@ -MediaTek PMIC Wrapper Driver - -This document describes the binding for the MediaTek PMIC wrapper. - -On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface -is not directly visible to the CPU, but only through the PMIC wrapper -inside the SoC. The communication between the SoC and the PMIC can -optionally be encrypted. Also a non standard Dual IO SPI mode can be -used to increase speed. - -IP Pairing - -on MT8135 the pins of some SoC internal peripherals can be on the PMIC. -The signals of these pins are routed over the SPI bus using the pwrap -bridge. In the binding description below the properties needed for bridging -are marked with "IP Pairing". These are optional on SoCs which do not support -IP Pairing - -Required properties in pwrap device node. -- compatible: - "mediatek,mt2701-pwrap" for MT2701/7623 SoCs - "mediatek,mt6765-pwrap" for MT6765 SoCs - "mediatek,mt6779-pwrap" for MT6779 SoCs - "mediatek,mt6797-pwrap" for MT6797 SoCs - "mediatek,mt6873-pwrap" for MT6873/8192 SoCs - "mediatek,mt7622-pwrap" for MT7622 SoCs - "mediatek,mt8135-pwrap" for MT8135 SoCs - "mediatek,mt8173-pwrap" for MT8173 SoCs - "mediatek,mt8183-pwrap" for MT8183 SoCs - "mediatek,mt8186-pwrap" for MT8186 SoCs - "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs - "mediatek,mt8195-pwrap" for MT8195 SoCs - "mediatek,mt8365-pwrap" for MT8365 SoCs - "mediatek,mt8516-pwrap" for MT8516 SoCs -- interrupts: IRQ for pwrap in SOC -- reg-names: "pwrap" is required; "pwrap-bridge" is optional. - "pwrap": Main registers base - "pwrap-bridge": bridge base (IP Pairing) -- reg: Must contain an entry for each entry in reg-names. -- clock-names: Must include the following entries: - "spi": SPI bus clock - "wrap": Main module clock - "sys": Optional system module clock - "tmr": Optional timer module clock -- clocks: Must contain an entry for each entry in clock-names. - -Optional properities: -- reset-names: Some SoCs include the following entries: - "pwrap" - "pwrap-bridge" (IP Pairing) -- resets: Must contain an entry for each entry in reset-names. -- pmic: Using either MediaTek PMIC MFD as the child device of pwrap - See the following for child node definitions: - Documentation/devicetree/bindings/mfd/mt6397.txt - or the regulator-only device as the child device of pwrap, such as MT6380. - See the following definitions for such kinds of devices. - Documentation/devicetree/bindings/regulator/mt6380-regulator.txt - -Example: - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - reg = <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names = "pwrap", "pwrap-bridge"; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names = "pwrap", "pwrap-bridge"; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "wrap"; - - pmic { - compatible = "mediatek,mt6397"; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml index 290555426c39..bdf482db32aa 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml @@ -39,8 +39,8 @@ properties: qcom,protection-domain: $ref: /schemas/types.yaml#/definitions/string-array description: | - Protection domain service name and path for APR service - possible values are:: + Protection domain service name and path for APR service (if supported). + Possible values are:: "avs/audio", "msm/adsp/audio_pd". "kernel/elf_loader", "msm/modem/wlan_pd". "tms/servreg", "msm/adsp/audio_pd". @@ -49,6 +49,5 @@ properties: required: - reg - - qcom,protection-domain additionalProperties: true diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml new file mode 100644 index 000000000000..ce7e20dd22c9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,dcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Data Capture and Compare + +maintainers: + - Souradeep Chowdhury <quic_schowdhu@quicinc.com> + +description: | + DCC (Data Capture and Compare) is a DMA engine which is used to save + configuration data or system memory contents during catastrophic failure + or SW trigger. DCC is used to capture and store data for debugging purpose + +properties: + compatible: + items: + - enum: + - qcom,sm8150-dcc + - qcom,sc7280-dcc + - qcom,sc7180-dcc + - qcom,sdm845-dcc + - const: qcom,dcc + + reg: + items: + - description: DCC base + - description: DCC RAM base + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + dma@10a2000{ + compatible = "qcom,sm8150-dcc", "qcom,dcc"; + reg = <0x010a2000 0x1000>, + <0x010ad000 0x2000>; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt deleted file mode 100644 index 1214192847ac..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt +++ /dev/null @@ -1,94 +0,0 @@ -Qualcomm GLINK edge binding - -This binding describes a Qualcomm GLINK edge, a fifo based mechanism for -communication between subsystem-pairs on various Qualcomm platforms. Two types -of edges can be described by the binding; the GLINK RPM edge and a SMEM based -edge. - -- compatible: - Usage: required for glink-rpm - Value type: <stringlist> - Definition: must be "qcom,glink-rpm" - -- label: - Usage: optional - Value type: <string> - Definition: should specify the subsystem name this edge corresponds to. - -- interrupts: - Usage: required - Value type: <prop-encoded-array> - Definition: should specify the IRQ used by the remote processor to - signal this processor about communication related events - -- qcom,remote-pid: - Usage: required for glink-smem - Value type: <u32> - Definition: specifies the identifier of the remote endpoint of this edge - -- qcom,rpm-msg-ram: - Usage: required for glink-rpm - Value type: <prop-encoded-array> - Definition: handle to RPM message memory resource - -- mboxes: - Usage: required - Value type: <prop-encoded-array> - Definition: reference to the "rpm_hlos" mailbox in APCS, as described - in mailbox/mailbox.txt - -= GLINK DEVICES -Each subnode of the GLINK node represent function tied to a virtual -communication channel. The name of the nodes are not important. The properties -of these nodes are defined by the individual bindings for the specific function -- but must contain the following property: - -- qcom,glink-channels: - Usage: required - Value type: <stringlist> - Definition: a list of channels tied to this function, used for matching - the function to a set of virtual channels - -- qcom,intents: - Usage: optional - Value type: <prop-encoded-array> - Definition: a list of size,amount pairs describing what intents should - be preallocated for this virtual channel. This can be used - to tweak the default intents available for the channel to - meet expectations of the remote. - -= EXAMPLE -The following example represents the GLINK RPM node on a MSM8996 device, with -the function for the "rpm_request" channel defined, which is used for -regulators and root clocks. - - apcs_glb: mailbox@9820000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - reg = <0x9820000 0x1000>; - - #mbox-cells = <1>; - }; - - rpm_msg_ram: memory@68000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x68000 0x6000>; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - - rpm-requests { - compatible = "qcom,rpm-msm8996"; - qcom,glink-channels = "rpm_requests"; - - qcom,intents = <0x400 5 - 0x800 1>; - ... - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml new file mode 100644 index 000000000000..aae9cf7b8caf --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,msm8976-ramp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Ramp Controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The Ramp Controller is used to program the sequence ID for pulse + swallowing, enable sequences and link Sequence IDs (SIDs) for the + CPU cores on some Qualcomm SoCs. + +properties: + compatible: + enum: + - qcom,msm8976-ramp-controller + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cpu-power-controller@b014000 { + compatible = "qcom,msm8976-ramp-controller"; + reg = <0x0b014000 0x68>; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml new file mode 100644 index 000000000000..cf863683c21a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,pmic-glink.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC GLINK firmware interface for battery management, USB + Type-C and other things. + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + The PMIC GLINK service, running on a coprocessor on some modern Qualcomm + platforms and implement USB Type-C handling and battery management. This + binding describes the component in the OS used to communicate with the + firmware and connect it's resources to those described in the Devicetree, + particularly the USB Type-C controllers relationship with USB and DisplayPort + components. + +properties: + compatible: + items: + - enum: + - qcom,sc8180x-pmic-glink + - qcom,sc8280xp-pmic-glink + - qcom,sm8350-pmic-glink + - const: qcom,pmic-glink + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^connector@\d$': + $ref: /schemas/connector/usb-connector.yaml# + + properties: + reg: true + + required: + - reg + + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - |+ + pmic-glink { + compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_role>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&ss_phy_out>; + }; + }; + + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&sbu_mux>; + }; + }; + }; + }; + }; +... + diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml new file mode 100644 index 000000000000..b00be9e01206 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,rpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Resource Power Manager (RPM) + +description: + This driver is used to interface with the Resource Power Manager (RPM) found + in various Qualcomm platforms. The RPM allows each component in the system + to vote for state of the system resources, such as clocks, regulators and bus + frequencies. + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +properties: + compatible: + enum: + - qcom,rpm-apq8064 + - qcom,rpm-msm8660 + - qcom,rpm-msm8960 + - qcom,rpm-ipq8064 + - qcom,rpm-mdm9615 + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: ack + - const: err + - const: wakeup + + qcom,ipc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to a syscon node representing the APCS registers + - description: u32 representing offset to the register within the syscon + - description: u32 representing the ipc bit within the register + description: + Three entries specifying the outgoing ipc bit used for signaling the RPM. + +patternProperties: + "^regulators(-[01])?$": + type: object + $ref: /schemas/regulator/qcom,rpm-regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - qcom,ipc + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mfd/qcom-rpm.h> + + rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&apcs 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_NONE>, <GIC_SPI 21 IRQ_TYPE_NONE>, <GIC_SPI 22 IRQ_TYPE_NONE>; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + + s1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + bias-pull-down; + + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + + qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index b246500d3d5d..a4046ba60846 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -112,8 +112,9 @@ properties: $ref: /schemas/power/qcom,rpmpd.yaml# patternProperties: - '-regulators$': + '^regulators(-[0-9])?$': $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# + unevaluatedProperties: false required: - compatible diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 11c0f4dd797c..16fd67c0bd1f 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -80,6 +80,7 @@ if: enum: - qcom,rpm-apq8084 - qcom,rpm-msm8916 + - qcom,rpm-msm8936 - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8953 diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml new file mode 100644 index 000000000000..12df33f58484 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzv2m-pwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc # RZ/V2M + - renesas,r9a09g055-pwc # RZ/V2MA + - const: renesas,rzv2m-pwc + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + renesas,rzv2m-pwc-power: + description: The PWC is used to control the system power supplies. + type: boolean + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; + reg = <0xa3700000 0x800>; + gpio-controller; + #gpio-cells = <2>; + renesas,rzv2m-pwc-power; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 2ed8cca79b59..e697c928900d 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -20,6 +20,11 @@ properties: - rockchip,rk3568-pipe-grf - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-bigcore0-grf + - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-ioc + - rockchip,rk3588-php-grf + - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf @@ -92,8 +97,9 @@ allOf: then: properties: edp-phy: - description: - Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt + type: object + $ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml# + unevaluatedProperties: false - if: properties: @@ -200,7 +206,7 @@ allOf: "usb2phy@[0-9a-f]+$": type: object - $ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#" + $ref: /schemas/phy/rockchip,inno-usb2phy.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 13bb8dfcefe6..f7c141dd11ec 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -31,20 +31,28 @@ select: properties: compatible: - items: - - enum: - - samsung,exynos3250-pmu - - samsung,exynos4210-pmu - - samsung,exynos4412-pmu - - samsung,exynos5250-pmu - - samsung,exynos5260-pmu - - samsung,exynos5410-pmu - - samsung,exynos5420-pmu - - samsung,exynos5433-pmu - - samsung,exynos7-pmu - - samsung,exynos850-pmu - - samsung-s5pv210-pmu - - const: syscon + oneOf: + - items: + - enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + - samsung,exynos850-pmu + - samsung-s5pv210-pmu + - const: syscon + - items: + - enum: + - samsung,exynos5250-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - const: simple-mfd + - const: syscon reg: maxItems: 1 @@ -64,6 +72,10 @@ properties: minItems: 1 maxItems: 32 + dp-phy: + $ref: /schemas/phy/samsung,dp-video-phy.yaml + unevaluatedProperties: false + interrupt-controller: description: Some PMUs are capable of behaving as an interrupt controller (mostly @@ -74,6 +86,10 @@ properties: Must be identical to the that of the parent interrupt controller. const: 3 + mipi-phy: + $ref: /schemas/phy/samsung,mipi-video-phy.yaml + unevaluatedProperties: false + reboot-mode: $ref: /schemas/power/reset/syscon-reboot-mode.yaml type: object @@ -117,6 +133,23 @@ allOf: - clock-names - clocks + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5250-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + then: + properties: + dp-phy: true + mipi-phy: true + else: + properties: + dp-phy: false + mipi-phy: false + examples: - | #include <dt-bindings/clock/exynos5250.h> @@ -130,4 +163,14 @@ examples: #clock-cells = <1>; clock-names = "clkout16"; clocks = <&clock CLK_FIN_PLL>; + + dp-phy { + compatible = "samsung,exynos5250-dp-video-phy"; + #phy-cells = <0>; + }; + + mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; }; diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml new file mode 100644 index 000000000000..163e912e9cad --- /dev/null +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/samsung,exynos-sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series System Registers (SYSREG) + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + compatible: + oneOf: + - items: + - enum: + - samsung,exynos3-sysreg + - samsung,exynos4-sysreg + - samsung,exynos5-sysreg + - tesla,fsd-cam-sysreg + - tesla,fsd-fsys0-sysreg + - tesla,fsd-fsys1-sysreg + - tesla,fsd-peric-sysreg + - const: syscon + - items: + - enum: + - samsung,exynos5433-cam0-sysreg + - samsung,exynos5433-cam1-sysreg + - samsung,exynos5433-disp-sysreg + - samsung,exynos5433-fsys-sysreg + - const: samsung,exynos5433-sysreg + - const: syscon + - items: + - enum: + - samsung,exynos5433-sysreg + - samsung,exynos850-sysreg + - samsung,exynosautov9-sysreg + - const: syscon + deprecated: true + - items: + - enum: + - samsung,exynos850-cmgp-sysreg + - samsung,exynos850-peri-sysreg + - const: samsung,exynos850-sysreg + - const: syscon + - items: + - enum: + - samsung,exynosautov9-fsys2-sysreg + - samsung,exynosautov9-peric0-sysreg + - samsung,exynosautov9-peric1-sysreg + - const: samsung,exynosautov9-sysreg + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-cmgp-sysreg + - samsung,exynos850-peri-sysreg + - samsung,exynos850-sysreg + then: + required: + - clocks + else: + properties: + clocks: false + +additionalProperties: false + +examples: + - | + system-controller@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml new file mode 100644 index 000000000000..32d9cc2d72a8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-adamv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier ADAMV block + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + ADAMV block implemented on Socionext UniPhier SoCs is an analog signal + amplifier that is a part of the external video and audio I/O system. + + This block is defined for controlling audio I/O reset only. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld11-adamv + - socionext,uniphier-ld20-adamv + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + reset-controller: + $ref: /schemas/reset/socionext,uniphier-reset.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@57920000 { + compatible = "socionext,uniphier-ld20-adamv", + "simple-mfd", "syscon"; + reg = <0x57920000 0x1000>; + + reset-controller { + compatible = "socionext,uniphier-ld20-adamv-reset"; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml new file mode 100644 index 000000000000..09f861cc068f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier SoC AHCI glue layer + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband + logic handling signals to AHCI host controller inside AHCI component. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-pro4-ahci-glue + - socionext,uniphier-pxs2-ahci-glue + - socionext,uniphier-pxs3-ahci-glue + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^reset-controller@[0-9a-f]+$": + $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml# + + "phy@[0-9a-f]+$": + $ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd"; + reg = <0x65b00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + reset-controller@0 { + compatible = "socionext,uniphier-pxs3-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link"; + resets = <&sys_rst 28>; + #reset-cells = <1>; + }; + + phy@10 { + compatible = "socionext,uniphier-pxs3-ahci-phy"; + reg = <0x10 0x10>; + clock-names = "link", "phy"; + clocks = <&sys_clk 28>, <&sys_clk 30>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml new file mode 100644 index 000000000000..bd0def7236b5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier SoC DWC3 USB3.0 glue layer + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is + a sideband logic handling signals to DWC3 host controller inside + USB3.0 component. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-pro4-dwc3-glue + - socionext,uniphier-pro5-dwc3-glue + - socionext,uniphier-pxs2-dwc3-glue + - socionext,uniphier-ld20-dwc3-glue + - socionext,uniphier-pxs3-dwc3-glue + - socionext,uniphier-nx1-dwc3-glue + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^reset-controller@[0-9a-f]+$": + $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml# + + "^regulator@[0-9a-f]+$": + $ref: /schemas/regulator/socionext,uniphier-regulator.yaml# + + "^phy@[0-9a-f]+$": + oneOf: + - $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml# + - $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + usb@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd"; + reg = <0x65b00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + reset-controller@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + regulator@100 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + }; + + phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml new file mode 100644 index 000000000000..2cc38bb5038e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-mioctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier media I/O block (MIO) controller + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + Media I/O block implemented on Socionext UniPhier SoCs is a legacy + integrated component of the stream type peripherals including USB2.0, + SD/eMMC, and MIO-DMAC. + Media I/O block has a common logic to control the component. + + Recent SoCs have SD interface logic specialized only for SD functions + as a subset of media I/O block. See socionext,uniphier-sdctrl.yaml. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld4-mioctrl + - socionext,uniphier-pro4-mioctrl + - socionext,uniphier-sld8-mioctrl + - socionext,uniphier-ld11-mioctrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/socionext,uniphier-clock.yaml# + + reset-controller: + $ref: /schemas/reset/socionext,uniphier-reset.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@5b3e0000 { + compatible = "socionext,uniphier-ld11-mioctrl", + "simple-mfd", "syscon"; + reg = <0x5b3e0000 0x800>; + + clock-controller { + compatible = "socionext,uniphier-ld11-mio-clock"; + #clock-cells = <1>; + }; + + reset-controller { + compatible = "socionext,uniphier-ld11-mio-reset"; + #reset-cells = <1>; + resets = <&sys_rst 7>; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml new file mode 100644 index 000000000000..0adcffe859ab --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier peripheral block controller + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + Peripheral block implemented on Socionext UniPhier SoCs is an integrated + component of the peripherals including UART, I2C/FI2C, and SCSSI. + Peripheral block controller is a logic to control the component. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld4-perictrl + - socionext,uniphier-pro4-perictrl + - socionext,uniphier-pro5-perictrl + - socionext,uniphier-pxs2-perictrl + - socionext,uniphier-sld8-perictrl + - socionext,uniphier-ld11-perictrl + - socionext,uniphier-ld20-perictrl + - socionext,uniphier-pxs3-perictrl + - socionext,uniphier-nx1-perictrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/socionext,uniphier-clock.yaml# + + reset-controller: + $ref: /schemas/reset/socionext,uniphier-reset.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@59820000 { + compatible = "socionext,uniphier-ld20-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + clock-controller { + compatible = "socionext,uniphier-ld20-peri-clock"; + #clock-cells = <1>; + }; + + reset-controller { + compatible = "socionext,uniphier-ld20-peri-reset"; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sdctrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sdctrl.yaml new file mode 100644 index 000000000000..cb3b0d42739f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sdctrl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sdctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier SD interface logic + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + SD interface logic implemented on Socionext UniPhier SoCs is + attached outside SDHC, and has some SD related functions such as + clock control, reset control, mode switch, and so on. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-pro5-sdctrl + - socionext,uniphier-pxs2-sdctrl + - socionext,uniphier-ld11-sdctrl + - socionext,uniphier-ld20-sdctrl + - socionext,uniphier-pxs3-sdctrl + - socionext,uniphier-nx1-sdctrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/socionext,uniphier-clock.yaml# + + reset-controller: + $ref: /schemas/reset/socionext,uniphier-reset.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@59810000 { + compatible = "socionext,uniphier-ld20-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x400>; + + clock-controller { + compatible = "socionext,uniphier-ld20-sd-clock"; + #clock-cells = <1>; + }; + + reset-controller { + compatible = "socionext,uniphier-ld20-sd-reset"; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml new file mode 100644 index 000000000000..1341544d1df5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier SoC-glue logic debug part + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + SoC-glue logic debug part implemented on Socionext UniPhier SoCs is + a collection of miscellaneous function registers handling signals outside + system components for debug and monitor use. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld4-soc-glue-debug + - socionext,uniphier-pro4-soc-glue-debug + - socionext,uniphier-pro5-soc-glue-debug + - socionext,uniphier-pxs2-soc-glue-debug + - socionext,uniphier-sld8-soc-glue-debug + - socionext,uniphier-ld11-soc-glue-debug + - socionext,uniphier-ld20-soc-glue-debug + - socionext,uniphier-pxs3-soc-glue-debug + - socionext,uniphier-nx1-soc-glue-debug + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^efuse@[0-9a-f]+$": + $ref: /schemas/nvmem/socionext,uniphier-efuse.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@5f900000 { + compatible = "socionext,uniphier-pxs2-soc-glue-debug", + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml new file mode 100644 index 000000000000..7845dcfca986 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier SoC-glue logic + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of + miscellaneous function registers handling signals outside system components. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld4-soc-glue + - socionext,uniphier-pro4-soc-glue + - socionext,uniphier-pro5-soc-glue + - socionext,uniphier-pxs2-soc-glue + - socionext,uniphier-sld8-soc-glue + - socionext,uniphier-ld11-soc-glue + - socionext,uniphier-ld20-soc-glue + - socionext,uniphier-pxs3-soc-glue + - socionext,uniphier-nx1-soc-glue + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + pinctrl: + $ref: /schemas/pinctrl/socionext,uniphier-pinctrl.yaml# + + usb-hub: + $ref: /schemas/phy/socionext,uniphier-usb2-phy.yaml# + + clock-controller: + $ref: /schemas/clock/socionext,uniphier-clock.yaml# + +allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pro4-soc-glue + - socionext,uniphier-ld11-soc-glue + then: + properties: + usb-hub: false + + - if: + not: + properties: + compatible: + contains: + const: socionext,uniphier-pro4-soc-glue + then: + properties: + clock-controller: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@5f800000 { + compatible = "socionext,uniphier-pro4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; + }; + + usb-hub { + compatible = "socionext,uniphier-pro4-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + + clock-controller { + compatible = "socionext,uniphier-pro4-sg-clock"; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sysctrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sysctrl.yaml new file mode 100644 index 000000000000..3acb14201d1a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sysctrl.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier system controller + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + System controller implemented on Socionext UniPhier SoCs has multiple + functions such as clock control, reset control, internal watchdog timer, + thermal management, and so on. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld4-sysctrl + - socionext,uniphier-pro4-sysctrl + - socionext,uniphier-pro5-sysctrl + - socionext,uniphier-pxs2-sysctrl + - socionext,uniphier-sld8-sysctrl + - socionext,uniphier-ld11-sysctrl + - socionext,uniphier-ld20-sysctrl + - socionext,uniphier-pxs3-sysctrl + - socionext,uniphier-nx1-sysctrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/socionext,uniphier-clock.yaml# + + reset-controller: + $ref: /schemas/reset/socionext,uniphier-reset.yaml# + + watchdog: + $ref: /schemas/watchdog/socionext,uniphier-wdt.yaml# + + thermal-sensor: + $ref: /schemas/thermal/socionext,uniphier-thermal.yaml# + +allOf: + - if: + properties: + compatible: + contains: + const: socionext,uniphier-ld4-sysctrl + then: + properties: + watchdog: false + + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-ld4-sysctrl + - socionext,uniphier-pro4-sysctrl + - socionext,uniphier-sld8-sysctrl + - socionext,uniphier-ld11-sysctrl + then: + properties: + thermal-sensor: false + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + syscon@61840000 { + compatible = "socionext,uniphier-ld20-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + clock-controller { + compatible = "socionext,uniphier-ld20-clock"; + #clock-cells = <1>; + }; + + reset-controller { + compatible = "socionext,uniphier-ld20-reset"; + #reset-cells = <1>; + }; + + watchdog { + compatible = "socionext,uniphier-wdt"; + }; + + thermal-sensor { + compatible = "socionext,uniphier-ld20-thermal"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml index ddea3d41971d..22cf9002fee7 100644 --- a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml @@ -25,6 +25,9 @@ description: | The Ring Accelerator is a hardware module that is responsible for accelerating management of the packet queues. The K3 SoCs can have more than one RA instances +allOf: + - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# + properties: compatible: items: @@ -54,14 +57,6 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: TI-SCI RM subtype for GP ring range - ti,sci: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: phandle on TI-SCI compatible System controller node - - ti,sci-dev-id: - $ref: /schemas/types.yaml#/definitions/uint32 - description: TI-SCI device id of the ring accelerator - required: - compatible - reg @@ -72,7 +67,7 @@ required: - ti,sci - ti,sci-dev-id -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/sound/adi,adau7002.txt b/Documentation/devicetree/bindings/sound/adi,adau7002.txt deleted file mode 100644 index f144ee1abf85..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,adau7002.txt +++ /dev/null @@ -1,19 +0,0 @@ -Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter - -Required properties: - - - compatible: Must be "adi,adau7002" - -Optional properties: - - - IOVDD-supply: Phandle and specifier for the power supply providing the IOVDD - supply as covered in Documentation/devicetree/bindings/regulator/regulator.txt - - If this property is not present it is assumed that the supply pin is - hardwired to always on. - -Example: - adau7002: pdm-to-i2s { - compatible = "adi,adau7002"; - IOVDD-supply = <&supply>; - }; diff --git a/Documentation/devicetree/bindings/sound/adi,adau7002.yaml b/Documentation/devicetree/bindings/sound/adi,adau7002.yaml new file mode 100644 index 000000000000..fcca0fde7d86 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/adi,adau7002.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/adi,adau7002.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: adi,adau7002 + + IOVDD-supply: + description: + IOVDD power supply, if skipped then it is assumed that the supply pin is + hardwired to always on. + + wakeup-delay-ms: + description: + Delay after power up needed for device to settle. + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + audio-codec { + compatible = "adi,adau7002"; + IOVDD-supply = <&pp1800_l15a>; + #sound-dai-cells = <0>; + wakeup-delay-ms = <80>; + }; diff --git a/Documentation/devicetree/bindings/sound/ak4613.yaml b/Documentation/devicetree/bindings/sound/ak4613.yaml index 010574645e6a..75e13414d6eb 100644 --- a/Documentation/devicetree/bindings/sound/ak4613.yaml +++ b/Documentation/devicetree/bindings/sound/ak4613.yaml @@ -25,6 +25,13 @@ properties: "#sound-dai-cells": const: 0 + ports: + $ref: audio-graph-port.yaml#/definitions/ports + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + patternProperties: "^asahi-kasei,in[1-2]-single-end$": description: Input Pin 1 - 2. diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt deleted file mode 100644 index fa4545ed81ca..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt +++ /dev/null @@ -1,34 +0,0 @@ -* Amlogic Audio FIFO controllers - -Required properties: -- compatible: 'amlogic,axg-toddr' or - 'amlogic,axg-toddr' or - 'amlogic,g12a-frddr' or - 'amlogic,g12a-toddr' or - 'amlogic,sm1-frddr' or - 'amlogic,sm1-toddr' -- reg: physical base address of the controller and length of memory - mapped region. -- interrupts: interrupt specifier for the fifo. -- clocks: phandle to the fifo peripheral clock provided by the audio - clock controller. -- resets: list of reset phandle, one for each entry reset-names. -- reset-names: should contain the following: - * "arb" : memory ARB line (required) - * "rst" : dedicated device reset line (optional) -- #sound-dai-cells: must be 0. -- amlogic,fifo-depth: The size of the controller's fifo in bytes. This - is useful for determining certain configuration such - as the flush threshold of the fifo - -Example of FRDDR A on the A113 SoC: - -frddr_a: audio-controller@1c0 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x1c>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>; - fifo-depth = <512>; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.yaml new file mode 100644 index 000000000000..b1b48d683101 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,axg-fifo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic AXG Audio FIFO controllers + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + compatible: + oneOf: + - enum: + - amlogic,axg-toddr + - amlogic,axg-frddr + - items: + - enum: + - amlogic,g12a-toddr + - amlogic,sm1-toddr + - const: amlogic,axg-toddr + - items: + - enum: + - amlogic,g12a-frddr + - amlogic,sm1-frddr + - const: amlogic,axg-frddr + + reg: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + clocks: + items: + - description: Peripheral clock + + interrupts: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + + amlogic,fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Size of the controller's fifo in bytes + +required: + - compatible + - reg + - "#sound-dai-cells" + - clocks + - interrupts + - resets + - amlogic,fifo-depth + +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - amlogic,g12a-toddr + - amlogic,sm1-toddr + - amlogic,g12a-frddr + - amlogic,sm1-frddr + + then: + properties: + resets: + minItems: 2 + reset-names: + items: + - const: arb + - const: rst + required: + - reset-names + + else: + properties: + resets: + maxItems: 1 + reset-names: + const: arb + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-audio-clkc.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> + #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> + + audio-controller@1c0 { + compatible = "amlogic,g12a-frddr", "amlogic,axg-frddr"; + reg = <0x1c0 0x1c>; + #sound-dai-cells = <0>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; + interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; + resets = <&arb>, <&clkc_audio AUD_RESET_FRDDR_A>; + reset-names = "arb", "rst"; + amlogic,fifo-depth = <512>; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt deleted file mode 100644 index 716878107a24..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Amlogic Audio PDM input - -Required properties: -- compatible: 'amlogic,axg-pdm' or - 'amlogic,g12a-pdm' or - 'amlogic,sm1-pdm' -- reg: physical base address of the controller and length of memory - mapped region. -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "pclk" : peripheral clock. - * "dclk" : pdm digital clock - * "sysclk" : dsp system clock -- #sound-dai-cells: must be 0. - -Optional property: -- resets: phandle to the dedicated reset line of the pdm input. - -Example of PDM on the A113 SoC: - -pdm: audio-controller@ff632000 { - compatible = "amlogic,axg-pdm"; - reg = <0x0 0xff632000 0x0 0x34>; - #sound-dai-cells = <0>; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.yaml new file mode 100644 index 000000000000..df21dd72fc65 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,axg-pdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Audio AXG PDM input + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - amlogic,g12a-pdm + - amlogic,sm1-pdm + - const: amlogic,axg-pdm + - const: amlogic,axg-pdm + + reg: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + clocks: + items: + - description: Peripheral clock + - description: PDM digital clock + - description: DSP system clock + + clock-names: + items: + - const: pclk + - const: dclk + - const: sysclk + + resets: + maxItems: 1 + +required: + - compatible + - reg + - "#sound-dai-cells" + - clocks + - clock-names + +allOf: + - $ref: dai-common.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,g12a-pdm + - amlogic,sm1-pdm + then: + required: + - resets + + else: + properties: + resets: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-audio-clkc.h> + + audio-controller@ff632000 { + compatible = "amlogic,axg-pdm"; + reg = <0xff632000 0x34>; + #sound-dai-cells = <0>; + clocks = <&clkc_audio AUD_CLKID_PDM>, + <&clkc_audio AUD_CLKID_PDM_DCLK>, + <&clkc_audio AUD_CLKID_PDM_SYSCLK>; + clock-names = "pclk", "dclk", "sysclk"; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt deleted file mode 100644 index 80b411296480..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt +++ /dev/null @@ -1,124 +0,0 @@ -Amlogic AXG sound card: - -Required properties: - -- compatible: "amlogic,axg-sound-card" -- model : User specified audio sound card name, one string - -Optional properties: - -- audio-aux-devs : List of phandles pointing to auxiliary devices -- audio-widgets : Please refer to widgets.txt. -- audio-routing : A list of the connections between audio components. - -Subnodes: - -- dai-link: Container for dai-link level properties and the CODEC - sub-nodes. There should be at least one (and probably more) - subnode of this type. - -Required dai-link properties: - -- sound-dai: phandle and port of the CPU DAI. - -Required TDM Backend dai-link properties: -- dai-format : CPU/CODEC common audio format - -Optional TDM Backend dai-link properties: -- dai-tdm-slot-rx-mask-{0,1,2,3}: Receive direction slot masks -- dai-tdm-slot-tx-mask-{0,1,2,3}: Transmit direction slot masks - When omitted, mask is assumed to have to no - slots. A valid must have at one slot, so at - least one these mask should be provided with - an enabled slot. -- dai-tdm-slot-num : Please refer to tdm-slot.txt. - If omitted, slot number is set to accommodate the largest - mask provided. -- dai-tdm-slot-width : Please refer to tdm-slot.txt. default to 32 if omitted. -- mclk-fs : Multiplication factor between stream rate and mclk - -Backend dai-link subnodes: - -- codec: dai-link representing backend links should have at least one subnode. - One subnode for each codec of the dai-link. - dai-link representing frontend links have no codec, therefore have no - subnodes - -Required codec subnodes properties: - -- sound-dai: phandle and port of the CODEC DAI. - -Optional codec subnodes properties: - -- dai-tdm-slot-tx-mask : Please refer to tdm-slot.txt. -- dai-tdm-slot-rx-mask : Please refer to tdm-slot.txt. - -Example: - -sound { - compatible = "amlogic,axg-sound-card"; - model = "AXG-S420"; - audio-aux-devs = <&tdmin_a>, <&tdmout_c>; - audio-widgets = "Line", "Lineout", - "Line", "Linein", - "Speaker", "Speaker1 Left", - "Speaker", "Speaker1 Right"; - "Speaker", "Speaker2 Left", - "Speaker", "Speaker2 Right"; - audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 2", "TDM_C Capture", - "TDMIN_A IN 5", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "Lineout", "Lineout AOUTL", - "Lineout", "Lineout AOUTR", - "Speaker1 Left", "SPK1 OUT_A", - "Speaker2 Left", "SPK2 OUT_A", - "Speaker1 Right", "SPK1 OUT_B", - "Speaker2 Right", "SPK2 OUT_B", - "Linein AINL", "Linein", - "Linein AINR", "Linein"; - - dai-link@0 { - sound-dai = <&frddr_a>; - }; - - dai-link@1 { - sound-dai = <&toddr_a>; - }; - - dai-link@2 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - dai-tdm-slot-rx-mask-1 = <1 1>; - mclk-fs = <256>; - - codec@0 { - sound-dai = <&lineout>; - }; - - codec@1 { - sound-dai = <&speaker_amp1>; - }; - - codec@2 { - sound-dai = <&speaker_amp2>; - }; - - codec@3 { - sound-dai = <&linein>; - }; - - }; - - dai-link@3 { - sound-dai = <&spdifout>; - - codec { - sound-dai = <&spdif_dit>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.yaml new file mode 100644 index 000000000000..bf1234550343 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.yaml @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,axg-sound-card.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic AXG sound card + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + compatible: + const: amlogic,axg-sound-card + + audio-aux-devs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: list of auxiliary devices + + audio-routing: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + A list of the connections between audio components. Each entry is a + pair of strings, the first being the connection's sink, the second + being the connection's source. + + audio-widgets: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + A list off component DAPM widget. Each entry is a pair of strings, + the first being the widget type, the second being the widget name + + model: + $ref: /schemas/types.yaml#/definitions/string + description: User specified audio sound card name + +patternProperties: + "^dai-link-[0-9]+$": + type: object + additionalProperties: false + description: + Container for dai-link level properties and the CODEC sub-nodes. + There should be at least one (and probably more) subnode of this type + + properties: + dai-format: + $ref: /schemas/types.yaml#/definitions/string + enum: [ i2s, left-j, dsp_a ] + + dai-tdm-slot-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of slots in use. If omitted, slot number is set to + accommodate the largest mask provided. + maximum: 32 + + dai-tdm-slot-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Width in bits for each slot + enum: [ 8, 16, 20, 24, 32 ] + default: 32 + + mclk-fs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Multiplication factor between the frame rate and master clock + rate + + sound-dai: + maxItems: 1 + description: phandle of the CPU DAI + + patternProperties: + "^dai-tdm-slot-(t|r)x-mask-[0-3]$": + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + Transmit and receive cpu slot masks of each TDM lane + When omitted, mask is assumed to have to no slots. A valid + interface must have at least one slot, so at least one these + mask should be provided with an enabled slot. + + "^codec(-[0-9]+)?$": + type: object + additionalProperties: false + description: + dai-link representing backend links should have at least one subnode. + One subnode for each codec of the dai-link. dai-link representing + frontend links have no codec, therefore have no subnodes + + properties: + sound-dai: + maxItems: 1 + description: phandle of the codec DAI + + patternProperties: + "^dai-tdm-slot-(t|r)x-mask$": + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: Transmit and receive codec slot masks + + required: + - sound-dai + + required: + - sound-dai + +required: + - model + - dai-link-0 + +unevaluatedProperties: false + +examples: + - | + sound { + compatible = "amlogic,axg-sound-card"; + model = "AXG-S420"; + audio-aux-devs = <&tdmin_a>, <&tdmout_c>; + audio-widgets = "Line", "Lineout", + "Line", "Linein", + "Speaker", "Speaker1 Left", + "Speaker", "Speaker1 Right", + "Speaker", "Speaker2 Left", + "Speaker", "Speaker2 Right"; + audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "SPDIFOUT IN 0", "FRDDR_A OUT 3", + "TDM_C Playback", "TDMOUT_C OUT", + "TDMIN_A IN 2", "TDM_C Capture", + "TDMIN_A IN 5", "TDM_C Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "Lineout", "Lineout AOUTL", + "Lineout", "Lineout AOUTR", + "Speaker1 Left", "SPK1 OUT_A", + "Speaker2 Left", "SPK2 OUT_A", + "Speaker1 Right", "SPK1 OUT_B", + "Speaker2 Right", "SPK2 OUT_B", + "Linein AINL", "Linein", + "Linein AINR", "Linein"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&toddr_a>; + }; + + dai-link-2 { + sound-dai = <&tdmif_c>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + dai-tdm-slot-rx-mask-1 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&lineout>; + }; + + codec-1 { + sound-dai = <&speaker_amp1>; + }; + + codec-2 { + sound-dai = <&speaker_amp2>; + }; + + codec-3 { + sound-dai = <&linein>; + }; + }; + + dai-link-3 { + sound-dai = <&spdifout>; + + codec { + sound-dai = <&spdif_dit>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.txt deleted file mode 100644 index df92a4ecf288..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Amlogic Audio SPDIF Input - -Required properties: -- compatible: 'amlogic,axg-spdifin' or - 'amlogic,g12a-spdifin' or - 'amlogic,sm1-spdifin' -- interrupts: interrupt specifier for the spdif input. -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "pclk" : peripheral clock. - * "refclk" : spdif input reference clock -- #sound-dai-cells: must be 0. - -Optional property: -- resets: phandle to the dedicated reset line of the spdif input. - -Example on the A113 SoC: - -spdifin: audio-controller@400 { - compatible = "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.yaml new file mode 100644 index 000000000000..a0bd7a5fb9b3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,axg-spdifin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Audio AXG SPDIF Input + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + compatible: + oneOf: + - const: amlogic,axg-spdifin + - items: + - enum: + - amlogic,g12a-spdifin + - amlogic,sm1-spdifin + - const: amlogic,axg-spdifin + + reg: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + clocks: + items: + - description: Peripheral clock + - description: SPDIF input reference clock + + clock-names: + items: + - const: pclk + - const: refclk + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - "#sound-dai-cells" + - clocks + - clock-names + - interrupts + +allOf: + - $ref: dai-common.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,g12a-spdifin + - amlogic,sm1-spdifin + then: + required: + - resets + + else: + properties: + resets: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-audio-clkc.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + audio-controller@400 { + compatible = "amlogic,axg-spdifin"; + reg = <0x400 0x30>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.txt deleted file mode 100644 index 28381dd1f633..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Amlogic Audio SPDIF Output - -Required properties: -- compatible: 'amlogic,axg-spdifout' or - 'amlogic,g12a-spdifout' or - 'amlogic,sm1-spdifout' -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "pclk" : peripheral clock. - * "mclk" : master clock -- #sound-dai-cells: must be 0. - -Optional property: -- resets: phandle to the dedicated reset line of the spdif output. - -Example on the A113 SoC: - -spdifout: audio-controller@480 { - compatible = "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.yaml new file mode 100644 index 000000000000..15be8dae9398 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,axg-spdifout.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Audio AXG SPDIF Output + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + compatible: + oneOf: + - const: amlogic,axg-spdifout + - items: + - enum: + - amlogic,g12a-spdifout + - amlogic,sm1-spdifout + - const: amlogic,axg-spdifout + + reg: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + clocks: + items: + - description: Peripheral clock + - description: SPDIF output master clock + + clock-names: + items: + - const: pclk + - const: mclk + + resets: + maxItems: 1 + +required: + - compatible + - reg + - "#sound-dai-cells" + - clocks + - clock-names + +allOf: + - $ref: dai-common.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,g12a-spdifout + - amlogic,sm1-spdifout + then: + required: + - resets + + else: + properties: + resets: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-audio-clkc.h> + + audio-controller@480 { + compatible = "amlogic,axg-spdifout"; + reg = <0x480 0x50>; + #sound-dai-cells = <0>; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt deleted file mode 100644 index 5996c0cd89c2..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Amlogic Audio TDM formatters - -Required properties: -- compatible: 'amlogic,axg-tdmin' or - 'amlogic,axg-tdmout' or - 'amlogic,g12a-tdmin' or - 'amlogic,g12a-tdmout' or - 'amlogic,sm1-tdmin' or - 'amlogic,sm1-tdmout -- reg: physical base address of the controller and length of memory - mapped region. -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "pclk" : peripheral clock. - * "sclk" : bit clock. - * "sclk_sel" : bit clock input multiplexer. - * "lrclk" : sample clock - * "lrclk_sel": sample clock input multiplexer - -Optional property: -- resets: phandle to the dedicated reset line of the tdm formatter. - -Example of TDMOUT_A on the S905X2 SoC: - -tdmout_a: audio-controller@500 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.yaml new file mode 100644 index 000000000000..719ca8fc98c7 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Audio AXG TDM formatters + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + compatible: + enum: + - amlogic,g12a-tdmout + - amlogic,sm1-tdmout + - amlogic,axg-tdmout + - amlogic,g12a-tdmin + - amlogic,sm1-tdmin + - amlogic,axg-tdmin + + clocks: + items: + - description: Peripheral clock + - description: Bit clock + - description: Bit clock input multiplexer + - description: Sample clock + - description: Sample clock input multiplexer + + clock-names: + items: + - const: pclk + - const: sclk + - const: sclk_sel + - const: lrclk + - const: lrclk_sel + + reg: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + +allOf: + - $ref: component-common.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,g12a-tdmin + - amlogic,sm1-tdmin + - amlogic,g12a-tdmout + - amlogic,sm1-tdmout + then: + required: + - resets + + else: + properties: + resets: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-audio-clkc.h> + #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> + + audio-controller@500 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x500 0x40>; + resets = <&clkc_audio AUD_RESET_TDMOUT_A>; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.txt deleted file mode 100644 index cabfb26a5f22..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Amlogic Audio TDM Interfaces - -Required properties: -- compatible: 'amlogic,axg-tdm-iface' -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "sclk" : bit clock. - * "lrclk": sample clock - * "mclk" : master clock - -> optional if the interface is in clock slave mode. -- #sound-dai-cells: must be 0. - -Example of TDM_A on the A113 SoC: - -tdmif_a: audio-controller@0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.yaml new file mode 100644 index 000000000000..320f0002649d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Audio TDM Interfaces + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: amlogic,axg-tdm-iface + + "#sound-dai-cells": + const: 0 + + clocks: + minItems: 2 + items: + - description: Bit clock + - description: Sample clock + - description: Master clock #optional + + clock-names: + minItems: 2 + items: + - const: sclk + - const: lrclk + - const: mclk + +required: + - compatible + - "#sound-dai-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-audio-clkc.h> + + audio-controller { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>, + <&clkc_audio AUD_CLKID_MST_A_MCLK>; + clock-names = "sclk", "lrclk", "mclk"; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml index 5b8d59245f82..b358fd601ed3 100644 --- a/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml +++ b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml @@ -62,7 +62,7 @@ patternProperties: description: phandle of the CPU DAI patternProperties: - "^codec-[0-9]+$": + "^codec(-[0-9]+)?$": type: object additionalProperties: false description: |- diff --git a/Documentation/devicetree/bindings/sound/apple,mca.yaml b/Documentation/devicetree/bindings/sound/apple,mca.yaml index 40e3a202f443..5c6ec08c7d24 100644 --- a/Documentation/devicetree/bindings/sound/apple,mca.yaml +++ b/Documentation/devicetree/bindings/sound/apple,mca.yaml @@ -23,6 +23,7 @@ properties: - enum: - apple,t6000-mca - apple,t8103-mca + - apple,t8112-mca - const: apple,mca reg: diff --git a/Documentation/devicetree/bindings/sound/audio-graph-port.yaml b/Documentation/devicetree/bindings/sound/audio-graph-port.yaml index f5b8b6d13077..6b4e02a0695a 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-port.yaml +++ b/Documentation/devicetree/bindings/sound/audio-graph-port.yaml @@ -11,32 +11,24 @@ maintainers: select: false -allOf: - - $ref: /schemas/graph.yaml#/$defs/port-base - -properties: - prefix: - description: "device name prefix" - $ref: /schemas/types.yaml#/definitions/string - convert-rate: - $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-rate" - convert-channels: - $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-channels" - convert-sample-format: - $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-format" +definitions: + port-base: + $ref: /schemas/graph.yaml#/$defs/port-base + properties: + convert-rate: + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-rate" + convert-channels: + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-channels" + convert-sample-format: + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-format" + mclk-fs: + $ref: "simple-card.yaml#/definitions/mclk-fs" -patternProperties: - "^endpoint(@[0-9a-f]+)?": + endpoint-base: $ref: /schemas/graph.yaml#/$defs/endpoint-base - unevaluatedProperties: false - properties: mclk-fs: - description: | - Multiplication factor between stream rate and codec mclk. - When defined, mclk-fs property defined in dai-link sub nodes are - ignored. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: "simple-card.yaml#/definitions/mclk-fs" frame-inversion: description: dai-link uses frame clock inversion $ref: /schemas/types.yaml#/definitions/flag @@ -53,6 +45,15 @@ patternProperties: oneOf: - $ref: /schemas/types.yaml#/definitions/flag - $ref: /schemas/types.yaml#/definitions/phandle + clocks: + description: Indicates system clock + $ref: /schemas/types.yaml#/definitions/phandle + system-clock-frequency: + $ref: "simple-card.yaml#/definitions/system-clock-frequency" + system-clock-direction-out: + $ref: "simple-card.yaml#/definitions/system-clock-direction-out" + system-clock-fixed: + $ref: "simple-card.yaml#/definitions/system-clock-fixed" dai-format: description: audio format. @@ -100,4 +101,24 @@ patternProperties: minimum: 1 maximum: 64 + ports: + $ref: "#/definitions/port-base" + unevaluatedProperties: false + patternProperties: + "^port(@[0-9a-f]+)?$": + $ref: "#/definitions/port-base" + unevaluatedProperties: false + patternProperties: + "^endpoint(@[0-9a-f]+)?": + $ref: "#/definitions/endpoint-base" + unevaluatedProperties: false + +allOf: + - $ref: "#/definitions/port-base" + +patternProperties: + "^endpoint(@[0-9a-f]+)?": + $ref: "#/definitions/endpoint-base" + unevaluatedProperties: false + additionalProperties: true diff --git a/Documentation/devicetree/bindings/sound/awinic,aw88395.yaml b/Documentation/devicetree/bindings/sound/awinic,aw88395.yaml new file mode 100644 index 000000000000..35eef7d818a2 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/awinic,aw88395.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/awinic,aw88395.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW88395 Smart Audio Amplifier + +maintainers: + - Weidong Wang <wangweidong.a@awinic.com> + +description: + The Awinic AW88395 is an I2S/TDM input, high efficiency + digital Smart K audio amplifier with an integrated 10.25V + smart boost convert. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: awinic,aw88395 + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - '#sound-dai-cells' + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + audio-codec@34 { + compatible = "awinic,aw88395"; + reg = <0x34>; + #sound-dai-cells = <0>; + reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml index 82062d80d700..18fb471aa891 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml @@ -22,6 +22,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + '#sound-dai-cells': description: The first cell indicating the audio interface. @@ -42,7 +45,7 @@ properties: Configures the peak current by monitoring the current through the boost FET. Range starts at 1600 mA and goes to a maximum of 4500 mA with increments of 50 mA. See section 4.3.6 of the datasheet for details. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1600 maximum: 4500 default: 4500 @@ -51,7 +54,7 @@ properties: description: Boost inductor value, expressed in nH. Valid values include 1000, 1200, 1500 and 2200. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1000 maximum: 2200 @@ -60,7 +63,7 @@ properties: Total equivalent boost capacitance on the VBST and VAMP pins, derated at 11 volts DC. The value must be rounded to the nearest integer and expressed in uF. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 cirrus,asp-sdout-hiz: description: @@ -70,7 +73,7 @@ properties: 1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled 2 = (Default) Logic 0 during unused slots, but Hi-Z while all transmit channels disabled 3 = Hi-Z during unused slots and while all transmit channels disabled - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 default: 2 @@ -84,7 +87,7 @@ properties: enable boost voltage. 0 = Internal Boost 1 = External Boost - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1 @@ -109,7 +112,7 @@ properties: 1 = GPIO 2 = Sync 3 = MCLK input - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 @@ -136,7 +139,7 @@ properties: 3 = MCLK input 4 = Push-pull INTB (active low) 5 = Push-pull INT (active high) - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 5 @@ -176,21 +179,23 @@ unevaluatedProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> + spi { #address-cells = <1>; #size-cells = <0>; - cs35l41: cs35l41@2 { - #sound-dai-cells = <1>; - compatible = "cirrus,cs35l41"; - reg = <2>; - VA-supply = <&dummy_vreg>; - VP-supply = <&dummy_vreg>; - reset-gpios = <&gpio 110 0>; - - cirrus,boost-type = <0>; - cirrus,boost-peak-milliamp = <4500>; - cirrus,boost-ind-nanohenry = <1000>; - cirrus,boost-cap-microfarad = <15>; + cs35l41: speaker-amp@2 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + reg = <2>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + reset-gpios = <&gpio 110 GPIO_ACTIVE_HIGH>; + + cirrus,boost-type = <0>; + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; }; }; diff --git a/Documentation/devicetree/bindings/sound/component-common.yaml b/Documentation/devicetree/bindings/sound/component-common.yaml new file mode 100644 index 000000000000..37766c5f3974 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/component-common.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/component-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Component Common Properties + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +properties: + sound-name-prefix: + $ref: /schemas/types.yaml#/definitions/string + description: | + Card implementing the routing property define the connection between + audio components as list of string pair. Component using the same + sink/source names may use this property to prepend the name of their + sinks/sources with the provided string. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/sound/dai-common.yaml b/Documentation/devicetree/bindings/sound/dai-common.yaml index d858eea73ed7..1aed2f0f1775 100644 --- a/Documentation/devicetree/bindings/sound/dai-common.yaml +++ b/Documentation/devicetree/bindings/sound/dai-common.yaml @@ -9,15 +9,10 @@ title: Digital Audio Interface Common Properties maintainers: - Jerome Brunet <jbrunet@baylibre.com> -properties: - sound-name-prefix: - $ref: /schemas/types.yaml#/definitions/string - description: | - Card implementing the routing property define the connection between - audio components as list of string pair. Component using the same - sink/source names may use this property to prepend the name of their - sinks/sources with the provided string. +allOf: + - $ref: component-common.yaml# +properties: '#sound-dai-cells': true additionalProperties: true diff --git a/Documentation/devicetree/bindings/sound/everest,es8326.yaml b/Documentation/devicetree/bindings/sound/everest,es8326.yaml index 07781408e788..07781408e788 100755..100644 --- a/Documentation/devicetree/bindings/sound/everest,es8326.yaml +++ b/Documentation/devicetree/bindings/sound/everest,es8326.yaml diff --git a/Documentation/devicetree/bindings/sound/fsl,sai.yaml b/Documentation/devicetree/bindings/sound/fsl,sai.yaml index 7e56337d8edc..088c26b001cc 100644 --- a/Documentation/devicetree/bindings/sound/fsl,sai.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,sai.yaml @@ -76,10 +76,14 @@ properties: minItems: 4 dmas: - maxItems: 2 + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX dma-names: - maxItems: 2 + items: + - const: rx + - const: tx interrupts: items: @@ -143,31 +147,6 @@ properties: allOf: - $ref: dai-common.yaml# - if: - properties: - compatible: - contains: - const: fsl,vf610-sai - then: - properties: - dmas: - items: - - description: DMA controller phandle and request line for TX - - description: DMA controller phandle and request line for RX - dma-names: - items: - - const: tx - - const: rx - else: - properties: - dmas: - items: - - description: DMA controller phandle and request line for RX - - description: DMA controller phandle and request line for TX - dma-names: - items: - - const: rx - - const: tx - - if: required: - fsl,sai-asynchronous then: @@ -199,9 +178,8 @@ examples: <&clks VF610_CLK_SAI2>, <&clks 0>, <&clks 0>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 21>, - <&edma0 0 20>; + dma-names = "rx", "tx"; + dmas = <&edma0 0 20>, <&edma0 0 21>; big-endian; lsb-first; }; diff --git a/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml b/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml index 223b8ea693dc..799b362ba498 100644 --- a/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - fsl,imx8mp-xcvr + - fsl,imx93-xcvr reg: items: diff --git a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml index 869b40363af8..0b1a01a4c14e 100644 --- a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml +++ b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml @@ -75,6 +75,18 @@ patternProperties: additionalProperties: false + platform: + description: Holds subnode which includes the phandle of q6apm platform device. + type: object + properties: + sound-dai: + maxItems: 1 + + required: + - sound-dai + + additionalProperties: false + required: - link-name - cpu diff --git a/Documentation/devicetree/bindings/sound/infineon,peb2466.yaml b/Documentation/devicetree/bindings/sound/infineon,peb2466.yaml new file mode 100644 index 000000000000..66993d378aaf --- /dev/null +++ b/Documentation/devicetree/bindings/sound/infineon,peb2466.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/infineon,peb2466.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Infineon PEB2466 codec + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: | + The Infineon PEB2466 codec is a programmable DSP-based four channels codec + with filters capabilities. + + The time-slots used by the codec must be set and so, the properties + 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and + 'dai-tdm-slot-rx-mask' must be present in the sound card node for sub-nodes + that involve the codec. The codec uses one 8bit time-slot per channel. + 'dai-tdm-tdm-slot-with' must be set to 8. + + The PEB2466 codec also supports 28 gpios (signaling pins). + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml + - $ref: dai-common.yaml# + +properties: + compatible: + const: infineon,peb2466 + + reg: + description: + SPI device address. + maxItems: 1 + + clocks: + items: + - description: Master clock + + clock-names: + items: + - const: mclk + + spi-max-frequency: + maximum: 8192000 + + reset-gpios: + description: + GPIO used to reset the device. + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Filters coefficients file to load. If this property is omitted, internal + filters are disabled. + + '#sound-dai-cells': + const: 0 + + '#gpio-cells': + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - '#sound-dai-cells' + - gpio-controller + - '#gpio-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + audio-codec@0 { + compatible = "infineon,peb2466"; + reg = <0>; + spi-max-frequency = <8192000>; + reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/irondevice,sma1303.yaml b/Documentation/devicetree/bindings/sound/irondevice,sma1303.yaml new file mode 100644 index 000000000000..b36c35e5da1a --- /dev/null +++ b/Documentation/devicetree/bindings/sound/irondevice,sma1303.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/irondevice,sma1303.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Iron Device SMA1303 Audio Amplifier + +maintainers: + - Kiseok Jo <kiseok.jo@irondevice.com> + +description: + SMA1303 digital class-D audio amplifier + with an integrated boost converter. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - irondevice,sma1303 + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + +required: + - compatible + - reg + - '#sound-dai-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + amplifier@1e { + compatible = "irondevice,sma1303"; + reg = <0x1e>; + #sound-dai-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/max98090.txt b/Documentation/devicetree/bindings/sound/max98090.txt deleted file mode 100644 index 39d640294c62..000000000000 --- a/Documentation/devicetree/bindings/sound/max98090.txt +++ /dev/null @@ -1,59 +0,0 @@ -MAX98090 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "maxim,max98090" or "maxim,max98091". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC - -- clock-names: Should be "mclk" - -- #sound-dai-cells : should be 0. - -- maxim,dmic-freq: Frequency at which to clock DMIC - -- maxim,micbias: Micbias voltage applies to the analog mic, valid voltages value are: - 0 - 2.2v - 1 - 2.55v - 2 - 2.4v - 3 - 2.8v - -Pins on the device (for linking into audio routes): - - * MIC1 - * MIC2 - * DMICL - * DMICR - * IN1 - * IN2 - * IN3 - * IN4 - * IN5 - * IN6 - * IN12 - * IN34 - * IN56 - * HPL - * HPR - * SPKL - * SPKR - * RCVL - * RCVR - * MICBIAS - -Example: - -audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/sound/max98095.txt b/Documentation/devicetree/bindings/sound/max98095.txt deleted file mode 100644 index 318a4c82f17f..000000000000 --- a/Documentation/devicetree/bindings/sound/max98095.txt +++ /dev/null @@ -1,22 +0,0 @@ -MAX98095 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "maxim,max98095". - -- reg : The I2C address of the device. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC - -- clock-names: Should be "mclk" - -Example: - -max98095: codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; -}; diff --git a/Documentation/devicetree/bindings/sound/maxim,max98090.yaml b/Documentation/devicetree/bindings/sound/maxim,max98090.yaml new file mode 100644 index 000000000000..65e4c516912f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/maxim,max98090.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/maxim,max98090.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX98090/MAX98091 audio codecs + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: | + Pins on the device (for linking into audio routes): + MIC1, MIC2, DMICL, DMICR, IN1, IN2, IN3, IN4, IN5, IN6, IN12, IN34, IN56, + HPL, HPR, SPKL, SPKR, RCVL, RCVR, MICBIAS + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - maxim,max98090 + - maxim,max98091 + + reg: + maxItems: 1 + + clocks: + items: + - description: master clock + + clock-names: + items: + - const: mclk + + interrupts: + maxItems: 1 + + maxim,dmic-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 2500000 + description: + DMIC clock frequency + + maxim,micbias: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + default: 3 + description: | + Micbias voltage applied to the analog mic, valid voltages value are: + 0 - 2.2v + 1 - 2.55v + 2 - 2.4v + 3 - 2.8v + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + clocks = <&i2s0 0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/maxim,max98095.yaml b/Documentation/devicetree/bindings/sound/maxim,max98095.yaml new file mode 100644 index 000000000000..77544a9e1587 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/maxim,max98095.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/maxim,max98095.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX98095 audio codec + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - maxim,max98095 + + reg: + maxItems: 1 + + clocks: + items: + - description: master clock + + clock-names: + items: + - const: mclk + + '#sound-dai-cells': + const: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + audio-codec@11 { + compatible = "maxim,max98095"; + reg = <0x11>; + clocks = <&i2s0 0>; + clock-names = "mclk"; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml new file mode 100644 index 000000000000..82ccb32f08f2 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AFE PCM controller for mt8188 + +maintainers: + - Trevor Wu <trevor.wu@mediatek.com> + +properties: + compatible: + const: mediatek,mt8188-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + mediatek,topckgen: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the mediatek topckgen controller + + power-domains: + maxItems: 1 + + clocks: + items: + - description: 26M clock + - description: audio pll1 clock + - description: audio pll2 clock + - description: clock divider for i2si1_mck + - description: clock divider for i2si2_mck + - description: clock divider for i2so1_mck + - description: clock divider for i2so2_mck + - description: clock divider for dptx_mck + - description: a1sys hoping clock + - description: audio intbus clock + - description: audio hires clock + - description: audio local bus clock + - description: mux for dptx_mck + - description: mux for i2so1_mck + - description: mux for i2so2_mck + - description: mux for i2si1_mck + - description: mux for i2si2_mck + - description: audio 26m clock + + clock-names: + items: + - const: clk26m + - const: apll1 + - const: apll2 + - const: apll12_div0 + - const: apll12_div1 + - const: apll12_div2 + - const: apll12_div3 + - const: apll12_div9 + - const: a1sys_hp_sel + - const: aud_intbus_sel + - const: audio_h_sel + - const: audio_local_bus_sel + - const: dptx_m_sel + - const: i2so1_m_sel + - const: i2so2_m_sel + - const: i2si1_m_sel + - const: i2si2_m_sel + - const: adsp_audio_26m + + mediatek,etdm-in1-cowork-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm in module. + enum: + - 1 # etdm2_in + - 2 # etdm1_out + - 3 # etdm2_out + + mediatek,etdm-in2-cowork-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm in module. + enum: + - 0 # etdm1_in + - 2 # etdm1_out + - 3 # etdm2_out + + mediatek,etdm-out1-cowork-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm out module. + enum: + - 0 # etdm1_in + - 1 # etdm2_in + - 3 # etdm2_out + + mediatek,etdm-out2-cowork-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm out module. + enum: + - 0 # etdm1_in + - 1 # etdm2_in + - 2 # etdm1_out + +patternProperties: + "^mediatek,etdm-in[1-2]-chn-disabled$": + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 16 + description: + This is a list of channel IDs which should be disabled. + By default, all data received from ETDM pins will be outputed to + memory. etdm in supports disable_out in direct mode(w/o interconn), + so user can disable the specified channels by the property. + uniqueItems: true + items: + minimum: 0 + maximum: 15 + + "^mediatek,etdm-in[1-2]-multi-pin-mode$": + type: boolean + description: if present, the etdm data mode is I2S. + + "^mediatek,etdm-out[1-3]-multi-pin-mode$": + type: boolean + description: if present, the etdm data mode is I2S. + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + - mediatek,topckgen + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + afe@10b10000 { + compatible = "mediatek,mt8188-afe"; + reg = <0x10b10000 0x10000>; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&watchdog 14>; + reset-names = "audiosys"; + mediatek,topckgen = <&topckgen>; + power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO + mediatek,etdm-in2-cowork-source = <2>; + mediatek,etdm-out2-cowork-source = <0>; + mediatek,etdm-in1-multi-pin-mode; + mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>; + clocks = <&clk26m>, + <&apmixedsys 9>, //CLK_APMIXED_APLL1 + <&apmixedsys 10>, //CLK_APMIXED_APLL2 + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0 + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1 + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2 + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3 + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9 + <&topckgen 83>, //CLK_TOP_A1SYS_HP + <&topckgen 31>, //CLK_TOP_AUD_INTBUS + <&topckgen 32>, //CLK_TOP_AUDIO_H + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS + <&topckgen 81>, //CLK_TOP_DPTX + <&topckgen 77>, //CLK_TOP_I2SO1 + <&topckgen 78>, //CLK_TOP_I2SO2 + <&topckgen 79>, //CLK_TOP_I2SI1 + <&topckgen 80>, //CLK_TOP_I2SI2 + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M + clock-names = "clk26m", + "apll1", + "apll2", + "apll12_div0", + "apll12_div1", + "apll12_div2", + "apll12_div3", + "apll12_div9", + "a1sys_hp_sel", + "aud_intbus_sel", + "audio_h_sel", + "audio_local_bus_sel", + "dptx_m_sel", + "i2so1_m_sel", + "i2so2_m_sel", + "i2si1_m_sel", + "i2si2_m_sel", + "adsp_audio_26m"; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml new file mode 100644 index 000000000000..6640272b3f4f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8188-mt6359.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8188 ASoC sound card + +maintainers: + - Trevor Wu <trevor.wu@mediatek.com> + +properties: + compatible: + const: mediatek,mt8188-mt6359-evb + + model: + $ref: /schemas/types.yaml#/definitions/string + description: User specified audio sound card name + + audio-routing: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + A list of the connections between audio components. Each entry is a + sink/source pair of strings. Valid names could be the input or output + widgets of audio components, power supplies, MicBias of codec and the + software switch. + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of MT8188 ASoC platform. + +patternProperties: + "^dai-link-[0-9]+$": + type: object + description: + Container for dai-link level properties and CODEC sub-nodes. + + properties: + link-name: + description: + This property corresponds to the name of the BE dai-link to which + we are going to update parameters in this node. + items: + enum: + - ADDA_BE + - DPTX_BE + - ETDM1_IN_BE + - ETDM2_IN_BE + - ETDM1_OUT_BE + - ETDM2_OUT_BE + - ETDM3_OUT_BE + - PCM1_BE + + codec: + description: Holds subnode which indicates codec dai. + type: object + additionalProperties: false + properties: + sound-dai: + minItems: 1 + maxItems: 2 + required: + - sound-dai + + additionalProperties: false + + required: + - link-name + - codec + +additionalProperties: false + +required: + - compatible + - mediatek,platform + +examples: + - | + sound { + compatible = "mediatek,mt8188-mt6359-evb"; + mediatek,platform = <&afe>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + audio-routing = + "Headphone", "Headphone L", + "Headphone", "Headphone R", + "AIN1", "Headset Mic"; + dai-link-0 { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml index 621022872c8d..651f61c7c25a 100644 --- a/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/mchp,i2s-mcc.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip I2S Multi-Channel Controller diff --git a/Documentation/devicetree/bindings/sound/microchip,pdmc.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-pdmc.yaml index c37b89d94c12..9b40268537cb 100644 --- a/Documentation/devicetree/bindings/sound/microchip,pdmc.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-pdmc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/microchip,pdmc.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-pdmc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip Pulse Density Microphone Controller @@ -67,6 +67,12 @@ properties: maxItems: 4 uniqueItems: true + microchip,startup-delay-us: + description: | + Specifies the delay in microseconds that needs to be applied after + enabling the PDMC microphones to avoid unwanted noise due to microphones + not being ready. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/mchp,spdifrx.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdifrx.yaml index 70a47c6823b1..2f43c684ab88 100644 --- a/Documentation/devicetree/bindings/sound/mchp,spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdifrx.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/mchp,spdifrx.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-spdifrx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip S/PDIF Rx Controller diff --git a/Documentation/devicetree/bindings/sound/mchp,spdiftx.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdiftx.yaml index c383162140bb..4702c528700d 100644 --- a/Documentation/devicetree/bindings/sound/mchp,spdiftx.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdiftx.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/mchp,spdiftx.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-spdiftx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip S/PDIF Tx Controller diff --git a/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml b/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml index 9d3139990237..aa23b0024c46 100644 --- a/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml +++ b/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - mediatek,mt8186-mt6366-rt1019-rt5682s-sound + - mediatek,mt8186-mt6366-rt5682s-max98360-sound mediatek,platform: $ref: "/schemas/types.yaml#/definitions/phandle" diff --git a/Documentation/devicetree/bindings/sound/nau8822.txt b/Documentation/devicetree/bindings/sound/nau8822.txt deleted file mode 100644 index a471d162d4e5..000000000000 --- a/Documentation/devicetree/bindings/sound/nau8822.txt +++ /dev/null @@ -1,16 +0,0 @@ -NAU8822 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "nuvoton,nau8822" - - - reg : the I2C address of the device. - -Example: - -codec: nau8822@1a { - compatible = "nuvoton,nau8822"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/nuvoton,nau8822.yaml b/Documentation/devicetree/bindings/sound/nuvoton,nau8822.yaml new file mode 100644 index 000000000000..65105402a53d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nuvoton,nau8822.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nuvoton,nau8822.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NAU8822 audio CODEC + +description: | + 24 bit stereo audio codec with speaker driver. + This device supports I2C/SPI. + +maintainers: + - David Lin <CTLIN0@nuvoton.com> + +properties: + compatible: + enum: + - nuvoton,nau8822 + + reg: + maxItems: 1 + + nuvoton,spk-btl: + description: + If set, configure the two loudspeaker outputs as a Bridge Tied Load output + to drive a high power external loudspeaker. + $ref: /schemas/types.yaml#/definitions/flag + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml index 89f7805de274..c4abac81f207 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml @@ -50,10 +50,10 @@ properties: maxItems: 1 "#address-cells": - const: 1 + enum: [ 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] ranges: true diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml index 5fc03b8771b1..9017fb6d575d 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml @@ -34,10 +34,10 @@ properties: maxItems: 1 "#address-cells": - const: 1 + enum: [ 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] ranges: true diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml index bb42220916b3..6cc8f86c7531 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml @@ -35,7 +35,7 @@ properties: clocks: minItems: 3 - maxItems: 7 + maxItems: 10 clock-names: minItems: 1 @@ -65,6 +65,9 @@ properties: power-domain-names: maxItems: 1 + required-opps: + maxItems: 1 + '#sound-dai-cells': const: 1 @@ -75,7 +78,7 @@ properties: const: 0 patternProperties: - "^dai-link@[0-9a-f]$": + "^dai-link@[0-9a-f]+$": type: object description: | LPASS CPU dai node for each I2S device or Soundwire device. Bindings of each node @@ -121,6 +124,8 @@ allOf: then: properties: + clocks: + maxItems: 3 clock-names: items: - const: ahbix-clk @@ -135,6 +140,9 @@ allOf: then: properties: + clocks: + minItems: 7 + maxItems: 7 clock-names: items: - const: ahbix-clk @@ -153,33 +161,31 @@ allOf: then: properties: + clocks: + minItems: 6 + maxItems: 6 clock-names: - oneOf: - - items: #for I2S - - const: pcnoc-sway-clk - - const: audio-core - - const: mclk0 - - const: pcnoc-mport-clk - - const: mi2s-bit-clk0 - - const: mi2s-bit-clk1 - - items: #for HDMI - - const: pcnoc-sway-clk - - const: audio-core - - const: pcnoc-mport-clk + items: + - const: pcnoc-sway-clk + - const: audio-core + - const: mclk0 + - const: pcnoc-mport-clk + - const: mi2s-bit-clk0 + - const: mi2s-bit-clk1 + reg: + minItems: 2 + maxItems: 2 reg-names: - anyOf: - - items: #for I2S - - const: lpass-lpaif - - items: #for I2S and HDMI - - const: lpass-hdmiif - - const: lpass-lpaif + items: + - const: lpass-hdmiif + - const: lpass-lpaif + interrupts: + minItems: 2 + maxItems: 2 interrupt-names: - anyOf: - - items: #for I2S - - const: lpass-irq-lpaif - - items: #for I2S and HDMI - - const: lpass-irq-lpaif - - const: lpass-irq-hdmi + items: + - const: lpass-irq-lpaif + - const: lpass-irq-hdmi required: - iommus - power-domains @@ -192,54 +198,44 @@ allOf: then: properties: + clocks: + minItems: 10 + maxItems: 10 clock-names: - oneOf: - - items: #for I2S - - const: aon_cc_audio_hm_h - - const: audio_cc_ext_mclk0 - - const: core_cc_sysnoc_mport_core - - const: core_cc_ext_if0_ibit - - const: core_cc_ext_if1_ibit - - items: #for Soundwire - - const: aon_cc_audio_hm_h - - const: audio_cc_codec_mem - - const: audio_cc_codec_mem0 - - const: audio_cc_codec_mem1 - - const: audio_cc_codec_mem2 - - const: aon_cc_va_mem0 - - items: #for HDMI - - const: core_cc_sysnoc_mport_core - + items: + - const: aon_cc_audio_hm_h + - const: audio_cc_ext_mclk0 + - const: core_cc_sysnoc_mport_core + - const: core_cc_ext_if0_ibit + - const: core_cc_ext_if1_ibit + - const: audio_cc_codec_mem + - const: audio_cc_codec_mem0 + - const: audio_cc_codec_mem1 + - const: audio_cc_codec_mem2 + - const: aon_cc_va_mem0 + reg: + minItems: 6 + maxItems: 6 reg-names: - anyOf: - - items: #for I2S - - const: lpass-lpaif - - items: #for I2S and HDMI - - const: lpass-hdmiif - - const: lpass-lpaif - - items: #for I2S, soundwire and HDMI - - const: lpass-hdmiif - - const: lpass-lpaif - - const: lpass-rxtx-cdc-dma-lpm - - const: lpass-rxtx-lpaif - - const: lpass-va-lpaif - - const: lpass-va-cdc-dma-lpm + items: + - const: lpass-hdmiif + - const: lpass-lpaif + - const: lpass-rxtx-cdc-dma-lpm + - const: lpass-rxtx-lpaif + - const: lpass-va-lpaif + - const: lpass-va-cdc-dma-lpm + interrupts: + minItems: 4 + maxItems: 4 interrupt-names: - anyOf: - - items: #for I2S - - const: lpass-irq-lpaif - - items: #for I2S and HDMI - - const: lpass-irq-lpaif - - const: lpass-irq-hdmi - - items: #for I2S, soundwire and HDMI - - const: lpass-irq-lpaif - - const: lpass-irq-hdmi - - const: lpass-irq-vaif - - const: lpass-irq-rxtxif + items: + - const: lpass-irq-lpaif + - const: lpass-irq-hdmi + - const: lpass-irq-vaif + - const: lpass-irq-rxtxif power-domain-names: - allOf: - - items: - - const: lcx + items: + - const: lcx required: - iommus diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml index 66431aade3b7..da5f70910da5 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml @@ -30,7 +30,9 @@ properties: const: 0 clocks: - maxItems: 5 + oneOf: + - maxItems: 3 + - maxItems: 5 clock-names: oneOf: diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index 26f0343b5aac..0a3c688ef1ec 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -36,7 +36,7 @@ properties: oneOf: - items: #for ADSP based platforms - const: mclk - - const: core + - const: macro - const: dcodec - items: #for ADSP bypass based platforms - const: mclk @@ -77,7 +77,7 @@ examples: clocks = <&aoncc 0>, <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "mclk", "core", "dcodec"; + clock-names = "mclk", "macro", "dcodec"; clock-output-names = "fsgen"; qcom,dmic-sample-rate = <600000>; vdd-micb-supply = <&vreg_s4a_1p8>; diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml index 2bf8d082f8f1..66cbb1f5e31a 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml @@ -9,9 +9,6 @@ title: LPASS(Low Power Audio Subsystem) VA Macro audio codec maintainers: - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> -allOf: - - $ref: dai-common.yaml# - properties: compatible: enum: @@ -30,15 +27,12 @@ properties: const: 0 clocks: - maxItems: 5 + minItems: 5 + maxItems: 6 clock-names: - items: - - const: mclk - - const: npl - - const: macro - - const: dcodec - - const: fsgen + minItems: 5 + maxItems: 6 clock-output-names: maxItems: 1 @@ -55,10 +49,51 @@ required: - reg - "#sound-dai-cells" +allOf: + - $ref: dai-common.yaml# + + - if: + properties: + compatible: + enum: + - qcom,sc7280-lpass-wsa-macro + - qcom,sm8450-lpass-wsa-macro + - qcom,sc8280xp-lpass-wsa-macro + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: mclk + - const: npl + - const: macro + - const: dcodec + - const: fsgen + + - if: + properties: + compatible: + enum: + - qcom,sm8250-lpass-wsa-macro + then: + properties: + clocks: + minItems: 6 + clock-names: + items: + - const: mclk + - const: npl + - const: macro + - const: dcodec + - const: va + - const: fsgen + unevaluatedProperties: false examples: - | + #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> #include <dt-bindings/sound/qcom,q6afe.h> codec@3240000 { compatible = "qcom,sm8250-lpass-wsa-macro"; @@ -69,7 +104,8 @@ examples: <&audiocc 0>, <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&aoncc LPASS_CDC_VA_MCLK>, <&vamacro>; - clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; clock-output-names = "mclk"; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml index a53c9ef938fa..cdbb4096fa44 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml @@ -17,7 +17,8 @@ properties: const: qcom,q6apm-dais iommus: - maxItems: 1 + minItems: 1 + maxItems: 2 required: - compatible diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index 70080d04ddc9..262de7a60a73 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -15,16 +15,20 @@ description: properties: compatible: - enum: - - lenovo,yoga-c630-sndcard - - qcom,apq8016-sbc-sndcard - - qcom,db845c-sndcard - - qcom,msm8916-qdsp6-sndcard - - qcom,qrb5165-rb5-sndcard - - qcom,sc8280xp-sndcard - - qcom,sdm845-sndcard - - qcom,sm8250-sndcard - - qcom,sm8450-sndcard + oneOf: + - items: + - enum: + - lenovo,yoga-c630-sndcard + - qcom,db845c-sndcard + - const: qcom,sdm845-sndcard + - enum: + - qcom,apq8016-sbc-sndcard + - qcom,msm8916-qdsp6-sndcard + - qcom,qrb5165-rb5-sndcard + - qcom,sc8280xp-sndcard + - qcom,sdm845-sndcard + - qcom,sm8250-sndcard + - qcom,sm8450-sndcard audio-routing: $ref: /schemas/types.yaml#/definitions/non-unique-string-array diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml index 184e8ccbdd13..ea09590bfa30 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml @@ -28,7 +28,9 @@ properties: description: GPIO spec for reset line to use maxItems: 1 - slim-ifc-dev: true + slim-ifc-dev: + description: IFC device interface + $ref: /schemas/types.yaml#/definitions/phandle clocks: maxItems: 1 @@ -147,21 +149,49 @@ patternProperties: required: - compatible - reg - - reset-gpios - - slim-ifc-dev - - interrupts - - interrupt-controller - - clock-frequency - - clock-output-names - - qcom,micbias1-microvolt - - qcom,micbias2-microvolt - - qcom,micbias3-microvolt - - qcom,micbias4-microvolt - - "#interrupt-cells" - - "#clock-cells" - - "#sound-dai-cells" - - "#address-cells" - - "#size-cells" + +allOf: + - if: + required: + - slim-ifc-dev + then: + required: + - reset-gpios + - slim-ifc-dev + - interrupt-controller + - clock-frequency + - clock-output-names + - qcom,micbias1-microvolt + - qcom,micbias2-microvolt + - qcom,micbias3-microvolt + - qcom,micbias4-microvolt + - "#interrupt-cells" + - "#clock-cells" + - "#sound-dai-cells" + - "#address-cells" + - "#size-cells" + oneOf: + - required: + - interrupts-extended + - required: + - interrupts + else: + properties: + reset-gpios: false + slim-ifc-dev: false + interrupts: false + interrupt-controller: false + clock-frequency: false + clock-output-names: false + qcom,micbias1-microvolt: false + qcom,micbias2-microvolt: false + qcom,micbias3-microvolt: false + qcom,micbias4-microvolt: false + "#interrupt-cells": false + "#clock-cells": false + "#sound-dai-cells": false + "#address-cells": false + "#size-cells": false additionalProperties: false diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa881x.yaml b/Documentation/devicetree/bindings/sound/qcom,wsa881x.yaml index d702b489320f..ac03672ebf6d 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wsa881x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wsa881x.yaml @@ -15,6 +15,9 @@ description: | Their primary operating mode uses a SoundWire digital audio interface. This binding is for SoundWire interface. +allOf: + - $ref: dai-common.yaml# + properties: compatible: const: sdw10217201000 @@ -39,7 +42,7 @@ required: - "#thermal-sensor-cells" - "#sound-dai-cells" -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/sound/renesas,idt821034.yaml b/Documentation/devicetree/bindings/sound/renesas,idt821034.yaml new file mode 100644 index 000000000000..a2b92dba5529 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/renesas,idt821034.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/renesas,idt821034.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas IDT821034 codec device + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: | + The IDT821034 codec is a four channel PCM codec with onchip filters and + programmable gain setting. + + The time-slots used by the codec must be set and so, the properties + 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and + 'dai-tdm-slot-rx-mask' must be present in the ALSA sound card node for + sub-nodes that involve the codec. The codec uses one 8bit time-slot per + channel. + 'dai-tdm-tdm-slot-with' must be set to 8. + + The IDT821034 codec also supports 5 gpios (SLIC signals) per channel. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - $ref: dai-common.yaml# + +properties: + compatible: + const: renesas,idt821034 + + reg: + description: + SPI device address. + maxItems: 1 + + spi-max-frequency: + maximum: 8192000 + + spi-cpha: true + + '#sound-dai-cells': + const: 0 + + '#gpio-cells': + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - spi-cpha + - '#sound-dai-cells' + - gpio-controller + - '#gpio-cells' + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + audio-codec@0 { + compatible = "renesas,idt821034"; + reg = <0>; + spi-max-frequency = <8192000>; + spi-cpha; + #sound-dai-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml index cb90463c7297..12ccf29338d9 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.yaml @@ -18,8 +18,7 @@ properties: - enum: - renesas,rcar_sound-r8a7778 # R-Car M1A - renesas,rcar_sound-r8a7779 # R-Car H1 - - enum: - - renesas,rcar_sound-gen1 + - const: renesas,rcar_sound-gen1 # for Gen2 SoC - items: - enum: @@ -32,8 +31,7 @@ properties: - renesas,rcar_sound-r8a7791 # R-Car M2-W - renesas,rcar_sound-r8a7793 # R-Car M2-N - renesas,rcar_sound-r8a7794 # R-Car E2 - - enum: - - renesas,rcar_sound-gen2 + - const: renesas,rcar_sound-gen2 # for Gen3 SoC - items: - enum: @@ -47,14 +45,16 @@ properties: - renesas,rcar_sound-r8a77965 # R-Car M3-N - renesas,rcar_sound-r8a77990 # R-Car E3 - renesas,rcar_sound-r8a77995 # R-Car D3 - - enum: - - renesas,rcar_sound-gen3 - # for Generic + - const: renesas,rcar_sound-gen3 + # for Gen4 SoC - items: - - enum: - - renesas,rcar_sound-gen1 - - renesas,rcar_sound-gen2 - - renesas,rcar_sound-gen3 + - const: renesas,rcar_sound-r8a779g0 # R-Car V4H + - const: renesas,rcar_sound-gen4 + # for Generic + - enum: + - renesas,rcar_sound-gen1 + - renesas,rcar_sound-gen2 + - renesas,rcar_sound-gen3 reg: minItems: 1 @@ -68,6 +68,7 @@ properties: description: | it must be 0 if your system is using single DAI it must be 1 if your system is using multi DAIs + This is used on simple-audio-card enum: [0, 1] "#clock-cells": @@ -113,15 +114,34 @@ properties: - pattern: '^clk_(a|b|c|i)$' ports: - $ref: /schemas/graph.yaml#/properties/ports + $ref: audio-graph-port.yaml#/definitions/port-base + unevaluatedProperties: false patternProperties: '^port(@[0-9a-f]+)?$': - $ref: audio-graph-port.yaml# + $ref: audio-graph-port.yaml#/definitions/port-base unevaluatedProperties: false + patternProperties: + "^endpoint(@[0-9a-f]+)?": + $ref: audio-graph-port.yaml#/definitions/endpoint-base + properties: + playback: + $ref: /schemas/types.yaml#/definitions/phandle-array + capture: + $ref: /schemas/types.yaml#/definitions/phandle-array + unevaluatedProperties: false port: - $ref: audio-graph-port.yaml# + $ref: audio-graph-port.yaml#/definitions/port-base unevaluatedProperties: false + patternProperties: + "^endpoint(@[0-9a-f]+)?": + $ref: audio-graph-port.yaml#/definitions/endpoint-base + properties: + playback: + $ref: /schemas/types.yaml#/definitions/phandle-array + capture: + $ref: /schemas/types.yaml#/definitions/phandle-array + unevaluatedProperties: false rcar_sound,dvc: description: DVC subnode. @@ -178,10 +198,6 @@ properties: enum: - tx - rx - required: - - interrupts - - dmas - - dma-names additionalProperties: false rcar_sound,ssiu: @@ -240,8 +256,6 @@ properties: $ref: /schemas/types.yaml#/definitions/flag required: - interrupts - - dmas - - dma-names additionalProperties: false # For DAI base @@ -271,7 +285,6 @@ required: - reg-names - clocks - clock-names - - "#sound-dai-cells" allOf: - $ref: dai-common.yaml# @@ -285,7 +298,6 @@ allOf: reg: maxItems: 3 reg-names: - maxItems: 3 items: enum: - scu @@ -294,9 +306,8 @@ allOf: else: properties: reg: - maxItems: 5 + minItems: 5 reg-names: - maxItems: 5 items: enum: - scu diff --git a/Documentation/devicetree/bindings/sound/rt5640.txt b/Documentation/devicetree/bindings/sound/rt5640.txt index ff1228713f7e..0c398581d52b 100644 --- a/Documentation/devicetree/bindings/sound/rt5640.txt +++ b/Documentation/devicetree/bindings/sound/rt5640.txt @@ -20,6 +20,9 @@ Optional properties: - realtek,in3-differential Boolean. Indicate MIC1/2/3 input are differential, rather than single-ended. +- realtek,lout-differential + Boolean. Indicate LOUT output is differential, rather than stereo. + - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - realtek,dmic1-data-pin diff --git a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml index 7b4e08ddef6a..7774543b8819 100644 --- a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml +++ b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml @@ -43,9 +43,10 @@ properties: type: object properties: sound-dai: + minItems: 1 items: - - description: phandle of the MAX98090 CODEC - description: phandle of the HDMI IP block node + - description: phandle of the MAX98090 CODEC samsung,audio-routing: $ref: /schemas/types.yaml#/definitions/non-unique-string-array diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml index 8d5dcf9cd43e..30b3b6e9824b 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml @@ -37,12 +37,20 @@ properties: samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports stereo channels. Exynos7 I2S1 upgraded to 5.1 multichannel with slightly modified bit offsets. + + tesla,fsd-i2s: for 8/16/24bit stereo channel I2S for playback and + capture, secondary FIFO using external DMA, s/w reset control, + internal mux for root clock source with all root clock sampling + frequencies supported by Exynos7 I2S and 7.1 channel TDM support + for playback and capture TDM (Time division multiplexing) to allow + transfer of multiple channel audio data on single data line. enum: - samsung,s3c6410-i2s - samsung,s5pv210-i2s - samsung,exynos5420-i2s - samsung,exynos7-i2s - samsung,exynos7-i2s1 + - tesla,fsd-i2s '#address-cells': const: 1 @@ -67,9 +75,6 @@ properties: - const: rx - const: tx-sec - assigned-clock-parents: true - assigned-clocks: true - clocks: minItems: 1 maxItems: 3 diff --git a/Documentation/devicetree/bindings/sound/simple-card.yaml b/Documentation/devicetree/bindings/sound/simple-card.yaml index ed19899bc94b..f0d81bfe2598 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.yaml +++ b/Documentation/devicetree/bindings/sound/simple-card.yaml @@ -205,6 +205,8 @@ patternProperties: $ref: "#/definitions/dai" "^simple-audio-card,codec(@[0-9a-f]+)?$": $ref: "#/definitions/dai" + "^simple-audio-card,plat(@[0-9a-f]+)?$": + $ref: "#/definitions/dai" "^simple-audio-card,dai-link(@[0-9a-f]+)?$": description: | @@ -215,6 +217,10 @@ patternProperties: reg: maxItems: 1 + "#address-cells": + const: 1 + "#size-cells": + const: 0 # common properties frame-master: $ref: "#/definitions/frame-master" @@ -244,9 +250,9 @@ patternProperties: maxItems: 1 patternProperties: - "^cpu(@[0-9a-f]+)?": + "^cpu(-[0-9]+)?$": $ref: "#/definitions/dai" - "^codec(@[0-9a-f]+)?": + "^codec(-[0-9]+)?$": $ref: "#/definitions/dai" additionalProperties: false @@ -462,16 +468,16 @@ examples: convert-channels = <8>; /* TDM Split */ - sndcpu1: cpu0 { + sndcpu1: cpu-0 { sound-dai = <&rcar_sound 1>; }; - cpu1 { + cpu-1 { sound-dai = <&rcar_sound 2>; }; - cpu2 { + cpu-2 { sound-dai = <&rcar_sound 3>; }; - cpu3 { + cpu-3 { sound-dai = <&rcar_sound 4>; }; codec { diff --git a/Documentation/devicetree/bindings/sound/tas5720.txt b/Documentation/devicetree/bindings/sound/tas5720.txt index df99ca9451b0..7d851ae2bba2 100644 --- a/Documentation/devicetree/bindings/sound/tas5720.txt +++ b/Documentation/devicetree/bindings/sound/tas5720.txt @@ -6,11 +6,13 @@ audio playback. For more product information please see the links below: https://www.ti.com/product/TAS5720L https://www.ti.com/product/TAS5720M +https://www.ti.com/product/TAS5720A-Q1 https://www.ti.com/product/TAS5722L Required properties: - compatible : "ti,tas5720", + "ti,tas5720a-q1", "ti,tas5722" - reg : I2C slave address - dvdd-supply : phandle to a 3.3-V supply for the digital circuitry diff --git a/Documentation/devicetree/bindings/sound/ti,pcm3168a.txt b/Documentation/devicetree/bindings/sound/ti,pcm3168a.txt deleted file mode 100644 index a02ecaab5183..000000000000 --- a/Documentation/devicetree/bindings/sound/ti,pcm3168a.txt +++ /dev/null @@ -1,56 +0,0 @@ -Texas Instruments pcm3168a DT bindings - -This driver supports both SPI and I2C bus access for this codec - -Required properties: - - - compatible: "ti,pcm3168a" - - - clocks : Contains an entry for each entry in clock-names - - - clock-names : Includes the following entries: - "scki" The system clock - - - VDD1-supply : Digital power supply regulator 1 (+3.3V) - - - VDD2-supply : Digital power supply regulator 2 (+3.3V) - - - VCCAD1-supply : ADC power supply regulator 1 (+5V) - - - VCCAD2-supply : ADC power supply regulator 2 (+5V) - - - VCCDA1-supply : DAC power supply regulator 1 (+5V) - - - VCCDA2-supply : DAC power supply regulator 2 (+5V) - -For required properties on SPI/I2C, consult SPI/I2C device tree documentation - -Optional properties: - - - reset-gpios : Optional reset gpio line connected to RST pin of the codec. - The RST line is low active: - RST = low: device power-down - RST = high: device is enabled - -Examples: - -i2c0: i2c0@0 { - - ... - - pcm3168a: audio-codec@44 { - compatible = "ti,pcm3168a"; - reg = <0x44>; - reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - clocks = <&clk_core CLK_AUDIO>; - clock-names = "scki"; - VDD1-supply = <&supply3v3>; - VDD2-supply = <&supply3v3>; - VCCAD1-supply = <&supply5v0>; - VCCAD2-supply = <&supply5v0>; - VCCDA1-supply = <&supply5v0>; - VCCDA2-supply = <&supply5v0>; - pinctrl-names = "default"; - pinctrl-0 = <&dac_clk_pin>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/ti,pcm3168a.yaml b/Documentation/devicetree/bindings/sound/ti,pcm3168a.yaml new file mode 100644 index 000000000000..b6a4360ab845 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,pcm3168a.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,pcm3168a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PCM3168A Audio Codec + +maintainers: + - Damien Horsley <Damien.Horsley@imgtec.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + +description: + The Texas Instruments PCM3168A is a 24-bit Multi-channel Audio CODEC with + 96/192kHz sampling rate, supporting both SPI and I2C bus access. + +properties: + compatible: + const: ti,pcm3168a + + reg: + maxItems: 1 + + clocks: + items: + - description: System clock input + + clock-names: + items: + - const: scki + + reset-gpios: + items: + - description: | + GPIO line connected to the active-low RST pin of the codec. + RST = low: device power-down + RST = high: device is enabled + + "#sound-dai-cells": + enum: [0, 1] + + VDD1-supply: + description: Digital power supply regulator 1 (+3.3V) + + VDD2-supply: + description: Digital power supply regulator 2 (+3.3V) + + VCCAD1-supply: + description: ADC power supply regulator 1 (+5V) + + VCCAD2-supply: + description: ADC power supply regulator 2 (+5V) + + VCCDA1-supply: + description: DAC power supply regulator 1 (+5V) + + VCCDA2-supply: + description: DAC power supply regulator 2 (+5V) + + ports: + $ref: audio-graph-port.yaml#/definitions/port-base + properties: + port@0: + $ref: audio-graph-port.yaml# + description: Audio input port. + + port@1: + $ref: audio-graph-port.yaml# + description: Audio output port. + +required: + - compatible + - reg + - clocks + - clock-names + - VDD1-supply + - VDD2-supply + - VCCAD1-supply + - VCCAD2-supply + - VCCDA1-supply + - VCCDA2-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pcm3168a: audio-codec@44 { + compatible = "ti,pcm3168a"; + reg = <0x44>; + reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + clocks = <&clk_core 42>; + clock-names = "scki"; + VDD1-supply = <&supply3v3>; + VDD2-supply = <&supply3v3>; + VCCAD1-supply = <&supply5v0>; + VCCAD2-supply = <&supply5v0>; + VCCDA1-supply = <&supply5v0>; + VCCDA2-supply = <&supply5v0>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/ti,tlv320aic3x.yaml b/Documentation/devicetree/bindings/sound/ti,tlv320aic3x.yaml new file mode 100644 index 000000000000..e8ca9f3369f8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,tlv320aic3x.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (C) 2022 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,tlv320aic3x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TLV320AIC3x Codec + +description: | + TLV320AIC3x are a series of low-power stereo audio codecs with stereo + headphone amplifier, as well as multiple inputs and outputs programmable in + single-ended or fully differential configurations. + + The serial control bus supports SPI or I2C protocols, while the serial audio + data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. + + The following pins can be referred in the sound node's audio routing property: + + CODEC output pins: + LLOUT + RLOUT + MONO_LOUT + HPLOUT + HPROUT + HPLCOM + HPRCOM + + CODEC input pins for TLV320AIC3104: + MIC2L + MIC2R + LINE1L + LINE1R + + CODEC input pins for other compatible codecs: + MIC3L + MIC3R + LINE1L + LINE2L + LINE1R + LINE2R + +maintainers: + - Jai Luthra <j-luthra@ti.com> + +properties: + compatible: + enum: + - ti,tlv320aic3x + - ti,tlv320aic33 + - ti,tlv320aic3007 + - ti,tlv320aic3106 + - ti,tlv320aic3104 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: + GPIO specification for the active low RESET input. + + gpio-reset: + maxItems: 1 + description: + Deprecated, please use reset-gpios instead. + deprecated: true + + ai3x-gpio-func: + description: AIC3X_GPIO1 & AIC3X_GPIO2 Functionality + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + + ai3x-micbias-vg: + description: MicBias required voltage. If node is omitted then MicBias is powered down. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - const: 1 + description: MICBIAS output is powered to 2.0V. + - const: 2 + description: MICBIAS output is powered to 2.5V. + - const: 3 + description: MICBIAS output is connected to AVDD. + + ai3x-ocmv: + description: Output Common-Mode Voltage selection. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - const: 0 + description: 1.35V + - const: 1 + description: 1.5V + - const: 2 + description: 1.65V + - const: 3 + description: 1.8V + + AVDD-supply: + description: Analog DAC voltage. + + IOVDD-supply: + description: I/O voltage. + + DRVDD-supply: + description: ADC analog and output driver voltage. + + DVDD-supply: + description: Digital core voltage. + + '#sound-dai-cells': + const: 0 + + clocks: + maxItems: 1 + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tlv320aic3x_i2c: audio-codec@1b { + compatible = "ti,tlv320aic3x"; + reg = <0x1b>; + + reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + + AVDD-supply = <®ulator>; + IOVDD-supply = <®ulator>; + DRVDD-supply = <®ulator>; + DVDD-supply = <®ulator>; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + tlv320aic3x_spi: audio-codec@0 { + compatible = "ti,tlv320aic3x"; + reg = <0>; /* CS number */ + #sound-dai-cells = <0>; + + AVDD-supply = <®ulator>; + IOVDD-supply = <®ulator>; + DRVDD-supply = <®ulator>; + DVDD-supply = <®ulator>; + ai3x-ocmv = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt deleted file mode 100644 index 20931a63fd64..000000000000 --- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt +++ /dev/null @@ -1,97 +0,0 @@ -Texas Instruments - tlv320aic3x Codec module - -The tlv320aic3x serial control bus communicates through both I2C and SPI bus protocols - -Required properties: - -- compatible - "string" - One of: - "ti,tlv320aic3x" - Generic TLV320AIC3x device - "ti,tlv320aic33" - TLV320AIC33 - "ti,tlv320aic3007" - TLV320AIC3007 - "ti,tlv320aic3106" - TLV320AIC3106 - "ti,tlv320aic3104" - TLV320AIC3104 - - -- reg - <int> - I2C slave address - - -Optional properties: - -- reset-gpios - GPIO specification for the active low RESET input. -- ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality - - Not supported on tlv320aic3104 -- ai3x-micbias-vg - MicBias Voltage required. - 1 - MICBIAS output is powered to 2.0V, - 2 - MICBIAS output is powered to 2.5V, - 3 - MICBIAS output is connected to AVDD, - If this node is not mentioned or if the value is incorrect, then MicBias - is powered down. -- ai3x-ocmv - Output Common-Mode Voltage selection: - 0 - 1.35V, - 1 - 1.5V, - 2 - 1.65V, - 3 - 1.8V -- AVDD-supply, IOVDD-supply, DRVDD-supply, DVDD-supply : power supplies for the - device as covered in Documentation/devicetree/bindings/regulator/regulator.txt - -Deprecated properties: - -- gpio-reset - gpio pin number used for codec reset - -CODEC output pins: - * LLOUT - * RLOUT - * MONO_LOUT - * HPLOUT - * HPROUT - * HPLCOM - * HPRCOM - -CODEC input pins for TLV320AIC3104: - * MIC2L - * MIC2R - * LINE1L - * LINE1R - -CODEC input pins for other compatible codecs: - * MIC3L - * MIC3R - * LINE1L - * LINE2L - * LINE1R - * LINE2R - -The pins can be used in referring sound node's audio-routing property. - -I2C example: - -#include <dt-bindings/gpio/gpio.h> - -tlv320aic3x: tlv320aic3x@1b { - compatible = "ti,tlv320aic3x"; - reg = <0x1b>; - - reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - - AVDD-supply = <®ulator>; - IOVDD-supply = <®ulator>; - DRVDD-supply = <®ulator>; - DVDD-supply = <®ulator>; -}; - -SPI example: - -spi0: spi@f0000000 { - tlv320aic3x: codec@0 { - compatible = "ti,tlv320aic3x"; - reg = <0>; /* CS number */ - #sound-dai-cells = <0>; - spi-max-frequency = <1000000>; - - AVDD-supply = <®ulator>; - IOVDD-supply = <®ulator>; - DRVDD-supply = <®ulator>; - DVDD-supply = <®ulator>; - ai3x-ocmv = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml index f1176a28fd87..eb0567b2971a 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A10 SPI Controller allOf: - - $ref: "spi-controller.yaml" + - $ref: spi-controller.yaml maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 58b7056f4a70..acf218507d22 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A31 SPI Controller allOf: - - $ref: "spi-controller.yaml" + - $ref: spi-controller.yaml maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 53eb6562b979..4e28e6e9d8e0 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson SPI Communication Controller @@ -41,7 +41,7 @@ properties: maxItems: 2 allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# - if: properties: compatible: @@ -100,17 +100,17 @@ unevaluatedProperties: false examples: - | spi@c1108d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0xc1108d80 0x80>; - interrupts = <112>; - clocks = <&clk81>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - - display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <1000000>; - reg = <0>; - }; + compatible = "amlogic,meson-gx-spicc"; + reg = <0xc1108d80 0x80>; + interrupts = <112>; + clocks = <&clk81>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <1000000>; + reg = <0>; + }; }; diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml index ac3b2ec300ac..8e769ccda97f 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson SPI Flash Controller @@ -11,7 +11,7 @@ maintainers: - Neil Armstrong <neil.armstrong@linaro.org> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# description: | The Meson SPIFC is a controller optimized for communication with SPI @@ -40,15 +40,15 @@ unevaluatedProperties: false examples: - | spi@c1108c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0xc1108c80 0x80>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - - flash: flash@0 { - compatible = "spansion,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; + compatible = "amlogic,meson6-spifc"; + reg = <0xc1108c80 0x80>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + + flash: flash@0 { + compatible = "spansion,m25p80", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; }; diff --git a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml index e6c817de3449..57d932af4506 100644 --- a/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml +++ b/Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml @@ -15,7 +15,7 @@ description: | SPI) of the AST2400, AST2500 and AST2600 SOCs. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -60,23 +60,23 @@ examples: interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; }; flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; }; flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; }; }; diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index 4dd973e341e6..6c57dd6c3a36 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel SPI device maintainers: - - Tudor Ambarus <tudor.ambarus@microchip.com> + - Tudor Ambarus <tudor.ambarus@linaro.org> allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index 1d493add4053..b0d99bc10535 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Quad Serial Peripheral Interface (QSPI) maintainers: - - Tudor Ambarus <tudor.ambarus@microchip.com> + - Tudor Ambarus <tudor.ambarus@linaro.org> allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml new file mode 100644 index 000000000000..6554978583f8 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC High Speed SPI controller + +maintainers: + - William Zhang <william.zhang@broadcom.com> + - Kursad Oney <kursad.oney@broadcom.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: | + Broadcom Broadband SoC supports High Speed SPI master controller since the + early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0 + controller was carried over to recent ARM based chips, such as BCM63138, + BCM4908 and BCM6858. The old MIPS based chip should continue to use the + brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to + use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as + defined below to match the specific chip along with ip revision info. + + This rev 1.0 controller has a limitation that can not keep the chip select line + active between the SPI transfers within the same SPI message. This can + terminate the transaction to some SPI devices prematurely. The issue can be + worked around by either the controller's prepend mode or using the dummy chip + select workaround. Driver automatically picks the suitable mode based on + transfer type so it is transparent to the user. + + The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI + controller rev 1.1 that add the capability to allow the driver to control chip + select explicitly. This solves the issue in the old controller. + +properties: + compatible: + oneOf: + - const: brcm,bcm6328-hsspi + - items: + - enum: + - brcm,bcm47622-hsspi + - brcm,bcm4908-hsspi + - brcm,bcm63138-hsspi + - brcm,bcm63146-hsspi + - brcm,bcm63148-hsspi + - brcm,bcm63158-hsspi + - brcm,bcm63178-hsspi + - brcm,bcm6846-hsspi + - brcm,bcm6856-hsspi + - brcm,bcm6858-hsspi + - brcm,bcm6878-hsspi + - const: brcm,bcmbca-hsspi-v1.0 + - items: + - enum: + - brcm,bcm4912-hsspi + - brcm,bcm6756-hsspi + - brcm,bcm6813-hsspi + - brcm,bcm6855-hsspi + - const: brcm,bcmbca-hsspi-v1.1 + + reg: + items: + - description: main registers + - description: miscellaneous control registers + minItems: 1 + + reg-names: + items: + - const: hsspi + - const: spim-ctrl + minItems: 1 + + clocks: + items: + - description: SPI master reference clock + - description: SPI master pll clock + + clock-names: + items: + - const: hsspi + - const: pll + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm6328-hsspi + - brcm,bcmbca-hsspi-v1.0 + then: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + else: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + minItems: 2 + maxItems: 2 + required: + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + spi@ff801000 { + compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0xff801000 0x1000>, + <0xff802610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml index ec5873919170..28222aae3077 100644 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml @@ -99,98 +99,98 @@ required: examples: - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access spi@f03e3400 { - compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; - reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>; - reg-names = "mspi", "bspi", "cs_reg"; - interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>; - interrupt-parent = <&gic>; - interrupt-names = "mspi_done", - "mspi_halted", - "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overread"; - clocks = <&hif_spi>; - #address-cells = <0x1>; - #size-cells = <0x0>; - - flash@0 { - #size-cells = <0x2>; - #address-cells = <0x2>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <0x2625a00>; - spi-cpol; - spi-cpha; - }; + compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; + reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>; + reg-names = "mspi", "bspi", "cs_reg"; + interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>; + interrupt-parent = <&gic>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&hif_spi>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + flash@0 { + #size-cells = <0x2>; + #address-cells = <0x2>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <0x2625a00>; + spi-cpol; + spi-cpha; + }; }; - | # BRCMSTB SoC: MSPI master for any SPI device spi@f0416000 { - clocks = <&upg_fixed>; - compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; - reg = <0xf0416000 0x180>; - reg-names = "mspi"; - interrupts = <0x14>; - interrupt-parent = <&irq0_aon_intc>; - interrupt-names = "mspi_done"; - #address-cells = <1>; - #size-cells = <0>; + clocks = <&upg_fixed>; + compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; + reg = <0xf0416000 0x180>; + reg-names = "mspi"; + interrupts = <0x14>; + interrupt-parent = <&irq0_aon_intc>; + interrupt-names = "mspi_done"; + #address-cells = <1>; + #size-cells = <0>; }; - | # iProc SoC #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> spi@18027200 { - compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; - reg = <0x18027200 0x184>, - <0x18027000 0x124>, - <0x1811c408 0x004>, - <0x180273a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mspi_done", - "mspi_halted", - "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done"; - clocks = <&iprocmed>; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done"; + clocks = <&iprocmed>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; }; - | # NS2 SoC #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> spi@66470200 { - compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; - reg = <0x66470200 0x184>, - <0x66470000 0x124>, - <0x67017408 0x004>, - <0x664703a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "spi_l1_intr"; - clocks = <&iprocmed>; - num-cs = <2>; + compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { #address-cells = <1>; - #size-cells = <0>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - spi-cpol; - spi-cpha; - }; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + spi-cpol; + spi-cpha; + }; }; diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 4707294d8f59..5c01db128be0 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -47,7 +47,7 @@ properties: cdns,fifo-depth: description: Size of the data FIFO in words. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 128, 256 ] default: 128 @@ -103,21 +103,21 @@ unevaluatedProperties: false examples: - | qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst 0x1>, <&rst 0x2>; - reset-names = "qspi", "qspi-ocp"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - }; + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + resets = <&rst 0x1>, <&rst 0x2>; + reset-names = "qspi", "qspi-ocp"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + }; }; diff --git a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml index b8bb8a3dbf54..eb0f92468185 100644 --- a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml @@ -2,8 +2,8 @@ # Copyright 2020-21 Cadence %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/cdns,xspi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/cdns,xspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence XSPI Controller @@ -16,7 +16,7 @@ description: | read/write access to slaves such as SPI-NOR flash. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml index e58644558412..f2dd20370dbb 100644 --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml @@ -10,7 +10,7 @@ maintainers: - Han Xu <han.xu@nxp.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml index 12cb76711000..2f593c7225e5 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml @@ -10,7 +10,7 @@ maintainers: - Shawn Guo <shawnguo@kernel.org> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml index 8d2a6c084eab..b6249880c3f9 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml @@ -10,7 +10,7 @@ maintainers: - Leilk Liu <leilk.liu@mediatek.com> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index 6e6e02c91780..1e5e89a693c3 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -18,14 +18,12 @@ description: | using the accompanying ECC engine. There should be only one spi slave device following generic spi bindings. -allOf: - - $ref: /schemas/spi/spi-controller.yaml# - properties: compatible: enum: - mediatek,mt7622-snand - mediatek,mt7629-snand + - mediatek,mt7986-snand reg: items: @@ -36,19 +34,20 @@ properties: - description: NFI interrupt clocks: - items: - - description: clock used for the controller - - description: clock used for the SPI bus + minItems: 2 + maxItems: 3 clock-names: - items: - - const: nfi_clk - - const: pad_clk + minItems: 2 + maxItems: 3 nand-ecc-engine: description: device-tree node of the accompanying ECC engine. $ref: /schemas/types.yaml#/definitions/phandle + mediatek,rx-latch-latency-ns: + description: Data read latch latency, unit is nanoseconds. + required: - compatible - reg @@ -57,6 +56,43 @@ required: - clock-names - nand-ecc-engine +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + - if: + properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + - if: + properties: + compatible: + enum: + - mediatek,mt7986-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + - description: clock used for the AHB bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + - const: nfi_hclk + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml index 7977799a8ee1..d19c9f73978f 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml @@ -10,7 +10,7 @@ maintainers: - Leilk Liu <leilk.liu@mediatek.com> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/mikrotik,rb4xx-spi.yaml b/Documentation/devicetree/bindings/spi/mikrotik,rb4xx-spi.yaml index 3fd0a8adfe9a..303f6dca89c0 100644 --- a/Documentation/devicetree/bindings/spi/mikrotik,rb4xx-spi.yaml +++ b/Documentation/devicetree/bindings/spi/mikrotik,rb4xx-spi.yaml @@ -11,7 +11,7 @@ maintainers: - Bert Vermeulen <bert@biot.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/mxicy,mx25f0a-spi.yaml b/Documentation/devicetree/bindings/spi/mxicy,mx25f0a-spi.yaml index a3aa5e07c0e4..221fe6e2ef53 100644 --- a/Documentation/devicetree/bindings/spi/mxicy,mx25f0a-spi.yaml +++ b/Documentation/devicetree/bindings/spi/mxicy,mx25f0a-spi.yaml @@ -10,7 +10,7 @@ maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.yaml b/Documentation/devicetree/bindings/spi/mxs-spi.yaml index 51f8c664323e..e2512166c1cd 100644 --- a/Documentation/devicetree/bindings/spi/mxs-spi.yaml +++ b/Documentation/devicetree/bindings/spi/mxs-spi.yaml @@ -10,7 +10,7 @@ maintainers: - Marek Vasut <marex@denx.de> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 899100e783c9..9ae1611175f2 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -11,7 +11,7 @@ maintainers: - Jonathan Hunter <jonathanh@nvidia.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -74,25 +74,25 @@ examples: #include <dt-bindings/reset/tegra210-car.h> #include <dt-bindings/interrupt-controller/arm-gic.h> spi@70410000 { - compatible = "nvidia,tegra210-qspi"; - reg = <0x70410000 0x1000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_QSPI>, - <&tegra_car TEGRA210_CLK_QSPI_PM>; - clock-names = "qspi", "qspi_out"; - resets = <&tegra_car 211>; - dmas = <&apbdma 5>, <&apbdma 5>; - dma-names = "rx", "tx"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - nvidia,tx-clk-tap-delay = <0>; - nvidia,rx-clk-tap-delay = <0>; - }; + compatible = "nvidia,tegra210-qspi"; + reg = <0x70410000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_QSPI>, + <&tegra_car TEGRA210_CLK_QSPI_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&tegra_car 211>; + dmas = <&apbdma 5>, <&apbdma 5>; + dma-names = "rx", "tx"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + nvidia,tx-clk-tap-delay = <0>; + nvidia,rx-clk-tap-delay = <0>; + }; }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml index b622bb7363ec..ee8f7ea907b0 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml @@ -1,9 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Quad Serial Peripheral Interface (QSPI) @@ -53,6 +52,11 @@ properties: - const: qspi-config - const: qspi-memory + operating-points-v2: true + + power-domains: + maxItems: 1 + required: - compatible - reg @@ -88,7 +92,6 @@ examples: spi-tx-bus-width = <2>; spi-rx-bus-width = <2>; }; - }; }; ... diff --git a/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml b/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml index 2f938c293f70..70330d945a70 100644 --- a/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml +++ b/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml @@ -11,7 +11,7 @@ maintainers: - Birger Koblitz <mail@birger-koblitz.de> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/renesas,rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rspi.yaml index f45d3b75d6de..4d8ec69214c9 100644 --- a/Documentation/devicetree/bindings/spi/renesas,rspi.yaml +++ b/Documentation/devicetree/bindings/spi/renesas,rspi.yaml @@ -141,15 +141,15 @@ examples: #include <dt-bindings/power/r8a7791-sysc.h> qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0xe6b10000 0x2c>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; + compatible = "renesas,qspi-r8a7791", "renesas,qspi"; + reg = <0xe6b10000 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index d33b72fabc5d..a132b5fc56e0 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -10,7 +10,7 @@ maintainers: - Mark Brown <broonie@kernel.org> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt b/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt deleted file mode 100644 index 37b29ee13860..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Broadcom BCM6328 High Speed SPI controller - -Required properties: -- compatible: must contain of "brcm,bcm6328-hsspi". -- reg: Base address and size of the controllers memory area. -- interrupts: Interrupt for the SPI block. -- clocks: phandles of the SPI clock and the PLL clock. -- clock-names: must be "hsspi", "pll". -- #address-cells: <1>, as required by generic SPI binding. -- #size-cells: <0>, also as required by generic SPI binding. - -Optional properties: -- num-cs: some controllers have less than 8 cs signals. Defaults to 8 - if absent. - -Child nodes as per the generic SPI binding. - -Example: - - spi@10001000 { - compatible = "brcm,bcm6328-hsspi"; - reg = <0x10001000 0x600>; - - interrupts = <29>; - - clocks = <&clkctl 9>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - - num-cs = <2>; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml index 64bf4e621142..b0f83b5c2cdd 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -10,7 +10,7 @@ maintainers: - Michal Simek <michal.simek@xilinx.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml index 94caa2b7e241..e91425012319 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml @@ -10,7 +10,7 @@ maintainers: - Anson Huang <Anson.Huang@nxp.com> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.yaml b/Documentation/devicetree/bindings/spi/spi-gpio.yaml index f29b89076c99..9ce1df93d4c3 100644 --- a/Documentation/devicetree/bindings/spi/spi-gpio.yaml +++ b/Documentation/devicetree/bindings/spi/spi-gpio.yaml @@ -14,7 +14,7 @@ description: dedicated GPIO lines. allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: @@ -41,7 +41,7 @@ properties: num-chipselects: description: Number of chipselect lines. Should be <0> if a single device with no chip select is connected. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 # Deprecated properties gpio-sck: false diff --git a/Documentation/devicetree/bindings/spi/spi-mux.yaml b/Documentation/devicetree/bindings/spi/spi-mux.yaml index 7ea79f6d33f3..fb2a6039928c 100644 --- a/Documentation/devicetree/bindings/spi/spi-mux.yaml +++ b/Documentation/devicetree/bindings/spi/spi-mux.yaml @@ -30,8 +30,8 @@ description: | +------------+ allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" - - $ref: "/schemas/spi/spi-peripheral-props.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# maintainers: - Chris Packham <chris.packham@alliedtelesis.co.nz> diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml index 1b552c298277..a813c971ecf6 100644 --- a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml @@ -11,7 +11,7 @@ maintainers: - Kuldeep Singh <singh.kuldeep87k@gmail.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index ead2cccf658f..782a014b63a7 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -44,11 +44,21 @@ properties: description: Maximum SPI clocking speed of the device in Hz. - spi-cs-setup-ns: + spi-cs-setup-delay-ns: description: - Delay in nanosecods to be introduced by the controller after CS is + Delay in nanoseconds to be introduced by the controller after CS is asserted. + spi-cs-hold-delay-ns: + description: + Delay in nanoseconds to be introduced by the controller before CS is + de-asserted. + + spi-cs-inactive-delay-ns: + description: + Delay in nanoseconds to be introduced by the controller after CS is + de-asserted. + spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml index 0e382119c64f..91e540a92faf 100644 --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml @@ -10,7 +10,7 @@ maintainers: - Linus Walleij <linus.walleij@linaro.org> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: @@ -45,7 +45,7 @@ properties: description: delay in ms following transfer completion before the runtime power management system suspends the device. A setting of 0 indicates no delay and the device will be suspended immediately. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 pl022,rt: description: indicates the controller should run the message pump with realtime @@ -81,7 +81,7 @@ patternProperties: properties: pl022,interface: description: SPI interface type - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: - 0 # SPI - 1 # Texas Instruments Synchronous Serial Frame Format @@ -89,7 +89,7 @@ patternProperties: pl022,com-mode: description: Specifies the transfer mode - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: - 0 # interrupt mode - 1 # polling mode @@ -98,30 +98,30 @@ patternProperties: pl022,rx-level-trig: description: Rx FIFO watermark level - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 4 pl022,tx-level-trig: description: Tx FIFO watermark level - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 4 pl022,ctrl-len: description: Microwire interface - Control length - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0x03 maximum: 0x1f pl022,wait-state: description: Microwire interface - Wait state - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] pl022,duplex: description: Microwire interface - Full/Half duplex - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] required: diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml index 66e49947b703..e4941e9212d1 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml @@ -11,7 +11,7 @@ description: as flash and display controllers using the SPI communication interface. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# maintainers: - Heiko Stuebner <heiko@sntech.de> diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 6e7e394fc1e4..5bffefb9c7eb 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -12,7 +12,7 @@ maintainers: - Palmer Dabbelt <palmer@sifive.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -51,14 +51,14 @@ properties: sifive,fifo-depth: description: Depth of hardware queues; defaults to 8 - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: [8] default: 8 sifive,max-bits-per-word: description: Maximum bits per word; defaults to 8 - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8] default: 8 diff --git a/Documentation/devicetree/bindings/spi/spi-st-ssc.txt b/Documentation/devicetree/bindings/spi/spi-st-ssc.txt deleted file mode 100644 index 1bdc4709e474..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-st-ssc.txt +++ /dev/null @@ -1,40 +0,0 @@ -STMicroelectronics SSC (SPI) Controller ---------------------------------------- - -Required properties: -- compatible : "st,comms-ssc4-spi" -- reg : Offset and length of the device's register set -- interrupts : The interrupt specifier -- clock-names : Must contain "ssc" -- clocks : Must contain an entry for each name in clock-names - See ../clk/* -- pinctrl-names : Uses "default", can use "sleep" if provided - See ../pinctrl/pinctrl-bindings.txt - -Optional properties: -- cs-gpios : List of GPIO chip selects - See ../spi/spi-bus.txt - -Child nodes represent devices on the SPI bus - See ../spi/spi-bus.txt - -Example: - spi@9840000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9840000 0x110>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-0 = <&pinctrl_spi0_default>; - pinctrl-names = "default"; - cs-gpios = <&pio17 5 0>; - #address-cells = <1>; - #size-cells = <0>; - - st95hf@0{ - compatible = "st,st95hf"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml b/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml index 3a58cf0f1ec8..edb5ba71af3a 100644 --- a/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sunplus sp7021 SPI controller allOf: - - $ref: "spi-controller.yaml" + - $ref: spi-controller.yaml maintainers: - Li-hao Kuo <lhjeff911@gmail.com> @@ -59,9 +59,9 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> - spi@9C002D80 { + spi@9c002d80 { compatible = "sunplus,sp7021-spi"; - reg = <0x9C002D80 0x80>, <0x9C002E00 0x80>; + reg = <0x9c002d80 0x80>, <0x9c002e00 0x80>; reg-names = "master", "slave"; interrupt-parent = <&intc>; interrupt-names = "dma_w", diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml index bbb735603f29..6bd83836eded 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml @@ -10,7 +10,7 @@ maintainers: - Michal Simek <michal.simek@xilinx.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 546c416cdb55..20f77246d365 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -10,7 +10,7 @@ maintainers: - Michal Simek <michal.simek@xilinx.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml b/Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml index a3ab1a1f1eb4..903b06f88b1b 100644 --- a/Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml +++ b/Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml @@ -1,9 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Spreadtrum ADI controller diff --git a/Documentation/devicetree/bindings/spi/st,ssc-spi.yaml b/Documentation/devicetree/bindings/spi/st,ssc-spi.yaml new file mode 100644 index 000000000000..6a77cd3f5d6e --- /dev/null +++ b/Documentation/devicetree/bindings/spi/st,ssc-spi.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/st,ssc-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics SSC SPI Controller + +description: | + The STMicroelectronics SSC SPI controller can be found on STi platforms + and it used to communicate with external devices using the + Serial Peripheral Interface. + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: st,comms-ssc4-spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ssc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stih407-clks.h> + spi@9840000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9840000 0x110>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-0 = <&pinctrl_spi0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 1eb17f7a4d86..8bba965a9ae6 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -11,7 +11,7 @@ maintainers: - Patrice Chotard <patrice.chotard@foss.st.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 1cda15f91cc3..9ca1a843c820 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -17,7 +17,7 @@ maintainers: - Fabrice Gasnier <fabrice.gasnier@foss.st.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# - if: properties: compatible: @@ -84,18 +84,17 @@ examples: #include <dt-bindings/clock/stm32mp1-clks.h> #include <dt-bindings/reset/stm32mp1-resets.h> spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 0 39 0x400 0x05>, - <&dmamux1 1 40 0x400 0x05>; - dma-names = "rx", "tx"; - cs-gpios = <&gpioa 11 0>; - + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 0 39 0x400 0x05>, + <&dmamux1 1 40 0x400 0x05>; + dma-names = "rx", "tx"; + cs-gpios = <&gpioa 11 0>; }; ... diff --git a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml index 1f1c40a9f320..83e8fb4a548d 100644 --- a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml @@ -11,7 +11,7 @@ description: memory devices. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 665c06e14f79..ba694ce4a037 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm845-imem - qcom,sdx55-imem - qcom,sdx65-imem + - qcom,sm8450-imem - const: syscon - const: simple-mfd diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml new file mode 100644 index 000000000000..fe9ae4c425c0 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC Low Voltage Thermal Sensor (LVTS) + +maintainers: + - Balsam CHIHI <bchihi@baylibre.com> + +description: | + LVTS is a thermal management architecture composed of three subsystems, + a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU), + a Converter - Low Voltage Thermal Sensor converter (LVTS), and + a Digital controller (LVTS_CTRL). + +properties: + compatible: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + description: LVTS reset for clearing temporary data on AP/MCU. + + nvmem-cells: + minItems: 1 + items: + - description: Calibration eFuse data 1 for LVTS + - description: Calibration eFuse data 2 for LVTS + + nvmem-cell-names: + minItems: 1 + items: + - const: lvts-calib-data-1 + - const: lvts-calib-data-2 + + "#thermal-sensor-cells": + const: 1 + +allOf: + - $ref: thermal-sensor.yaml# + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + then: + properties: + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + then: + properties: + nvmem-cells: + minItems: 2 + + nvmem-cell-names: + minItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/reset/mt8195-resets.h> + #include <dt-bindings/thermal/mediatek,lvts-thermal.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8195-lvts-mcu"; + reg = <0 0x11278000 0 0x1000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; + + trips { + cpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index d20569b9b763..52ec18cf1eda 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -13,6 +13,7 @@ properties: enum: - qcom,spmi-adc-tm5 - qcom,spmi-adc-tm5-gen2 + - qcom,adc-tm7 # Incomplete / subject to change reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0231f187b097..926e9c51c93c 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -37,6 +37,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens - const: qcom,tsens-v1 @@ -80,18 +81,120 @@ properties: maxItems: 2 nvmem-cells: - minItems: 1 - maxItems: 2 - description: - Reference to an nvmem node for the calibration data + oneOf: + - minItems: 1 + maxItems: 2 + description: + Reference to an nvmem node for the calibration data + - minItems: 5 + maxItems: 35 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor + # special case for msm8974 / apq8084 + - maxItems: 51 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor, main and backup copies, plus use_backup cell nvmem-cell-names: - minItems: 1 - items: - - const: calib - - enum: - - calib_backup - - calib_sel + oneOf: + - minItems: 1 + items: + - const: calib + - enum: + - calib_backup + - calib_sel + - minItems: 5 + items: + - const: mode + - const: base1 + - const: base2 + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + # special case for msm8974 / apq8084 + - items: + - const: mode + - const: base1 + - const: base2 + - const: use_backup + - const: mode_backup + - const: base1_backup + - const: base2_backup + - const: s0_p1 + - const: s0_p2 + - const: s1_p1 + - const: s1_p2 + - const: s2_p1 + - const: s2_p2 + - const: s3_p1 + - const: s3_p2 + - const: s4_p1 + - const: s4_p2 + - const: s5_p1 + - const: s5_p2 + - const: s6_p1 + - const: s6_p2 + - const: s7_p1 + - const: s7_p2 + - const: s8_p1 + - const: s8_p2 + - const: s9_p1 + - const: s9_p2 + - const: s10_p1 + - const: s10_p2 + - const: s0_p1_backup + - const: s0_p2_backup + - const: s1_p1_backup + - const: s1_p2_backup + - const: s2_p1_backup + - const: s2_p2_backup + - const: s3_p1_backup + - const: s3_p2_backup + - const: s4_p1_backup + - const: s4_p2_backup + - const: s5_p1_backup + - const: s5_p2_backup + - const: s6_p1_backup + - const: s6_p2_backup + - const: s7_p1_backup + - const: s7_p2_backup + - const: s8_p1_backup + - const: s8_p2_backup + - const: s9_p1_backup + - const: s9_p2_backup + - const: s10_p1_backup + - const: s10_p2_backup "#qcom,sensors": description: @@ -222,6 +325,36 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> + // Example 1 (new calbiration data: for pre v1 IP): + thermal-sensor@900000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2"; + + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> // Example 1 (legacy: for pre v1 IP): tsens1: thermal-sensor@900000 { compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml index 0f05f5c886c5..ecf276fd155c 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml @@ -28,6 +28,7 @@ properties: - renesas,r8a77980-thermal # R-Car V3H - renesas,r8a779a0-thermal # R-Car V3U - renesas,r8a779f0-thermal # R-Car S4-8 + - renesas,r8a779g0-thermal # R-Car V4H reg: true @@ -80,6 +81,7 @@ else: - description: TSC1 registers - description: TSC2 registers - description: TSC3 registers + - description: TSC4 registers if: not: properties: @@ -87,6 +89,7 @@ else: contains: enum: - renesas,r8a779f0-thermal + - renesas,r8a779g0-thermal then: required: - interrupts diff --git a/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml b/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml index c5b25ce44956..6f975821fa5e 100644 --- a/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml @@ -46,14 +46,9 @@ examples: - | // The UniPhier thermal should be a subnode of a "syscon" compatible node. - sysctrl@61840000 { - compatible = "socionext,uniphier-ld20-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - pvtctl: thermal { - compatible = "socionext,uniphier-ld20-thermal"; - interrupts = <0 3 1>; - #thermal-sensor-cells = <0>; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pvtctl: thermal-sensor { + compatible = "socionext,uniphier-ld20-thermal"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 8bbb6e94508b..b3e797e8aa31 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -33,6 +33,7 @@ Required properties: For those SoCs that use CPUX * "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX) + * "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX) - reg: Should contain location and length for timer register. - clocks: Should contain system clock. diff --git a/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt b/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt deleted file mode 100644 index 5e10c345548f..000000000000 --- a/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt +++ /dev/null @@ -1,47 +0,0 @@ -* MSM Timer - -Properties: - -- compatible : Should at least contain "qcom,msm-timer". More specific - properties specify which subsystem the timers are paired with. - - "qcom,kpss-timer" - krait subsystem - "qcom,scss-timer" - scorpion subsystem - -- interrupts : Interrupts for the debug timer, the first general purpose - timer, and optionally a second general purpose timer, and - optionally as well, 2 watchdog interrupts, in that order. - -- reg : Specifies the base address of the timer registers. - -- clocks: Reference to the parent clocks, one per output clock. The parents - must appear in the same order as the clock names. - -- clock-names: The name of the clocks as free-form strings. They should be in - the same order as the clocks. - -- clock-frequency : The frequency of the debug timer and the general purpose - timer(s) in Hz in that order. - -Optional: - -- cpu-offset : per-cpu offset used when the timer is accessed without the - CPU remapping facilities. The offset is - cpu-offset + (0x10000 * cpu-nr). - -Example: - - timer@200a000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>, - <1 4 0x301>, - <1 5 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <19200000>, - <32768>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x40000>; - }; diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 000000000000..38d67e1a5a79 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel <anup@brainfault.org> + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mode + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cannot-wake-cpu: + type: boolean + description: + If present, the timer interrupt cannot wake up the CPU from one or + more suspend/idle states. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +... diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml index b61ed1a431bb..65e59836a660 100644 --- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml +++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml @@ -17,6 +17,7 @@ properties: - items: - enum: - rockchip,rv1108-timer + - rockchip,rv1126-timer - rockchip,rk3036-timer - rockchip,rk3128-timer - rockchip,rk3188-timer diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index bbad24165837..aada6957216c 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -20,6 +20,10 @@ description: property of "/cpus" DT node. The "timebase-frequency" DT property is described in Documentation/devicetree/bindings/riscv/cpus.yaml + T-Head C906/C910 CPU cores include an implementation of CLINT too, however + their implementation lacks a memory-mapped MTIME register, thus not + compatible with SiFive ones. + properties: compatible: oneOf: @@ -30,6 +34,10 @@ properties: - canaan,k210-clint - const: sifive,clint0 - items: + - enum: + - allwinner,sun20i-d1-clint + - const: thead,c900-clint + - items: - const: sifive,clint0 - const: riscv,clint0 deprecated: true diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index f5c0a6283e61..6f482a254a1d 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -65,6 +65,8 @@ properties: - capella,cm3232 # CM3323: Ambient Light Sensor - capella,cm3323 + # Cisco SPI Petra + - cisco,spi-petra # High-Precision Digital Thermometer - dallas,ds1631 # Total-Elapsed-Time Recorder with Alarm @@ -141,6 +143,8 @@ properties: - infineon,slb9645tt # Infineon SLB9673 I2C TPM 2.0 - infineon,slb9673 + # Infineon TDA38640 Voltage Regulator + - infineon,tda38640 # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor - infineon,tlv493d-a1b6 # Infineon Multi-phase Digital VR Controller xdpe11280 @@ -169,6 +173,8 @@ properties: - isil,isl29030 # Intersil ISL68137 Digital Output Configurable PWM Controller - isil,isl68137 + # Linear Technology LTC2488 + - lineartechnology,ltc2488 # 5 Bit Programmable, Pulse-Width Modulator - maxim,ds1050 # 10 kOhm digital potentiometer with I2C interface @@ -227,6 +233,8 @@ properties: - memsic,mxc6655 # Menlo on-board CPLD trivial SPI device - menlo,m53cpld + # Micron SPI NOR Authenta + - micron,spi-authenta # Microchip differential I2C ADC, 1 Channel, 18 bit - microchip,mcp3421 # Microchip differential I2C ADC, 2 Channel, 18 bit @@ -305,10 +313,14 @@ properties: - pulsedlight,lidar-lite-v2 # Renesas ISL29501 time-of-flight sensor - renesas,isl29501 + # Rohm DH2228FV + - rohm,dh2228fv # S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) - samsung,24ad0xd1 # Samsung Exynos SoC SATA PHY I2C device - samsung,exynos-sataphy-i2c + # Semtech sx1301 baseband processor + - semtech,sx1301 # Sensirion low power multi-pixel gas sensor with I2C interface - sensirion,sgpc3 # Sensirion multi-pixel gas sensor with I2C interface @@ -323,6 +335,10 @@ properties: - sensortek,stk8ba50 # SGX Sensortech VZ89X Sensors - sgx,vz89x + # Silicon Labs EM3581 Zigbee SoC with SPI interface + - silabs,em3581 + # Silicon Labs SI3210 Programmable CMOS SLIC/CODEC with SPI interface + - silabs,si3210 # Relative Humidity and Temperature Sensors - silabs,si7020 # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index f2d6298d926c..c5a06c048389 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc + - qcom,sm8550-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 @@ -44,6 +45,8 @@ properties: minItems: 8 maxItems: 11 + dma-coherent: true + interconnects: minItems: 2 maxItems: 2 @@ -71,6 +74,9 @@ properties: minItems: 1 maxItems: 2 + required-opps: + maxItems: 1 + resets: maxItems: 1 @@ -103,6 +109,7 @@ allOf: - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc + - qcom,sm8550-ufshc then: properties: clocks: diff --git a/Documentation/devicetree/bindings/ufs/sprd,ums9620-ufs.yaml b/Documentation/devicetree/bindings/ufs/sprd,ums9620-ufs.yaml new file mode 100644 index 000000000000..36a8ae77949f --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/sprd,ums9620-ufs.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/sprd,ums9620-ufs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc Universal Flash Storage (UFS) Controller + +maintainers: + - Zhe Wang <zhe.wang1@unisoc.com> + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: sprd,ums9620-ufs + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: controller_eb + - const: cfg_eb + - const: core + + resets: + maxItems: 2 + + reset-names: + items: + - const: controller + - const: device + + vdd-mphy-supply: + description: + Phandle to vdd-mphy supply regulator node. + + sprd,ufs-anlg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of syscon used to control ufs analog regs. + + sprd,aon-apb-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of syscon used to control always-on regs. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + ufs: ufs@22000000 { + compatible = "sprd,ums9620-ufs"; + reg = <0x22000000 0x3000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + vcc-supply = <&vddemmccore>; + vdd-mphy-supply = <&vddufs1v2>; + clocks = <&apahb_gate 5>, <&apahb_gate 22>, <&aonapb_clk 52>; + clock-names = "controller_eb", "cfg_eb", "core"; + assigned-clocks = <&aonapb_clk 52>; + assigned-clock-parents = <&g5l_pll 12>; + resets = <&apahb_gate 4>, <&aonapb_gate 69>; + reset-names = "controller", "device"; + sprd,ufs-anlg-syscon = <&anlg_phy_g12_regs>; + sprd,aon-apb-syscon = <&aon_apb_regs>; + }; diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml index 8992eff6ce38..f972ce976e86 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -13,10 +13,12 @@ maintainers: properties: compatible: oneOf: - - const: allwinner,sun4i-a10-musb - - const: allwinner,sun6i-a31-musb - - const: allwinner,sun8i-a33-musb - - const: allwinner,sun8i-h3-musb + - enum: + - allwinner,sun4i-a10-musb + - allwinner,sun6i-a31-musb + - allwinner,sun8i-a33-musb + - allwinner,sun8i-h3-musb + - allwinner,suniv-f1c100s-musb - items: - enum: - allwinner,sun8i-a83t-musb diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index daf2a859418d..f38a2be07eda 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -108,6 +108,7 @@ allOf: then: properties: phy-names: + minItems: 2 items: - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used diff --git a/Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt b/Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt deleted file mode 100644 index 452c45c7bf29..000000000000 --- a/Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt +++ /dev/null @@ -1,11 +0,0 @@ -* Broadcom USB controllers - -Required properties: -- compatible: "brcm,bcm3384-ohci", "brcm,bcm3384-ehci" - - These currently use the generic-ohci and generic-ehci drivers. On some - systems, special handling may be needed in the following cases: - - - Restoring state after systemwide power save modes - - Sharing PHYs with the USBD (UDC) hardware - - Figuring out which controllers are disabled on ASIC bondout variants diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index ba51fb1252b9..72ceea575d58 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -11,6 +11,7 @@ Required properties: "fsl,imx6ul-usb" "fsl,imx7d-usb" "fsl,imx7ulp-usb" + "fsl,imx8mm-usb" "lsi,zevio-usb" "qcom,ci-hdrc" "chipidea,usb2" diff --git a/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml new file mode 100644 index 000000000000..75eec4a9a020 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cypress,cypd4226.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress cypd4226 Type-C Controller + +maintainers: + - Wayne Chang <waynec@nvidia.com> + +description: + The Cypress cypd4226 is a dual Type-C controller that is controlled + via an I2C interface. + +properties: + compatible: + const: cypress,cypd4226 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + const: 0x08 + + interrupts: + items: + - description: cypd4226 host interrupt + + firmware-name: + enum: + - nvidia,gpu + - nvidia,jetson-agx-xavier + description: | + The name of the CCGx firmware built for product series. + should be set one of following: + - "nvidia,gpu" for the NVIDIA RTX product series + - "nvidia,jetson-agx-xavier" for the NVIDIA Jetson product series + +patternProperties: + '^connector@[01]$': + $ref: /schemas/connector/usb-connector.yaml# + unevaluatedProperties: false + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +anyOf: + - required: + - connector@0 + - required: + - connector@1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/tegra194-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <2>; + + typec@8 { + compatible = "cypress,cypd4226"; + reg = <0x08>; + interrupt-parent = <&gpio_aon>; + interrupts = <TEGRA194_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>; + firmware-name = "nvidia,jetson-agx-xavier"; + #address-cells = <1>; + #size-cells = <0>; + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_role_switch0>; + }; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/ehci-omap.txt b/Documentation/devicetree/bindings/usb/ehci-omap.txt deleted file mode 100644 index d77e11a975a2..000000000000 --- a/Documentation/devicetree/bindings/usb/ehci-omap.txt +++ /dev/null @@ -1,31 +0,0 @@ -OMAP HS USB EHCI controller - -This device is usually the child of the omap-usb-host -Documentation/devicetree/bindings/mfd/omap-usb-host.txt - -Required properties: - -- compatible: should be "ti,ehci-omap" -- reg: should contain one register range i.e. start and length -- interrupts: description of the interrupt line - -Optional properties: - -- phys: list of phandles to PHY nodes. - This property is required if at least one of the ports are in - PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY - -To specify the port mode, see -Documentation/devicetree/bindings/mfd/omap-usb-host.txt - -Example for OMAP4: - -usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap"; - reg = <0x4a064c00 0x400>; - interrupts = <0 77 0x4>; -}; - -&usbhsehci { - phys = <&hsusb1_phy 0 &hsusb3_phy>; -}; diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt deleted file mode 100644 index 2855bae79fda..000000000000 --- a/Documentation/devicetree/bindings/usb/ehci-orion.txt +++ /dev/null @@ -1,22 +0,0 @@ -* EHCI controller, Orion Marvell variants - -Required properties: -- compatible: must be one of the following - "marvell,orion-ehci" - "marvell,armada-3700-ehci" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The EHCI interrupt - -Optional properties: -- clocks: reference to the clock -- phys: reference to the USB PHY -- phy-names: name of the USB PHY, should be "usb" - -Example: - - ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - }; diff --git a/Documentation/devicetree/bindings/usb/faraday,fotg210.yaml b/Documentation/devicetree/bindings/usb/faraday,fotg210.yaml index 84b3b69256b1..3fe4d1564dfe 100644 --- a/Documentation/devicetree/bindings/usb/faraday,fotg210.yaml +++ b/Documentation/devicetree/bindings/usb/faraday,fotg210.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/usb/faraday,fotg210.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Faraday Technology FOTG210 HS OTG USB 2.0 controller +title: Faraday Technology FOTG200 series HS OTG USB 2.0 controller maintainers: - Linus Walleij <linus.walleij@linaro.org> @@ -17,10 +17,11 @@ allOf: properties: compatible: oneOf: + - const: faraday,fotg200 - const: faraday,fotg210 - items: - const: cortina,gemini-usb - - const: faraday,fotg210 + - const: faraday,fotg200 reg: maxItems: 1 @@ -66,7 +67,7 @@ examples: #include <dt-bindings/clock/cortina,gemini-clock.h> #include <dt-bindings/reset/cortina,gemini-reset.h> usb0: usb@68000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; + compatible = "cortina,gemini-usb", "faraday,fotg200"; reg = <0x68000000 0x1000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_USB0>; diff --git a/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml b/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml index 9473f26b0621..51120fe90322 100644 --- a/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml +++ b/Documentation/devicetree/bindings/usb/fcs,fsa4480.yaml @@ -51,7 +51,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - fsa4480@42 { + typec-mux@42 { compatible = "fcs,fsa4480"; reg = <0x42>; diff --git a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt b/Documentation/devicetree/bindings/usb/fcs,fusb302.txt deleted file mode 100644 index 60e4654297af..000000000000 --- a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt +++ /dev/null @@ -1,34 +0,0 @@ -Fairchild FUSB302 Type-C Port controllers - -Required properties : -- compatible : "fcs,fusb302" -- reg : I2C slave address -- interrupts : Interrupt specifier - -Required sub-node: -- connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings - of the connector node are specified in: - - Documentation/devicetree/bindings/connector/usb-connector.yaml - - -Example: - -fusb302: typec-portc@54 { - compatible = "fcs,fusb302"; - reg = <0x54>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(3000, 12000, 3000) - PDO_PPS_APDO(3000, 11000, 3000)>; - op-sink-microwatt = <10000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/fcs,fusb302.yaml b/Documentation/devicetree/bindings/usb/fcs,fusb302.yaml new file mode 100644 index 000000000000..b396ea0ab10c --- /dev/null +++ b/Documentation/devicetree/bindings/usb/fcs,fusb302.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/fcs,fusb302.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fairchild FUSB302 Type-C Port controller + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + compatible: + const: fcs,fusb302 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vbus-supply: + description: VBUS power supply + + connector: + type: object + $ref: /schemas/connector/usb-connector.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - vbus-supply + - connector + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/usb/pd.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + typec-portc@54 { + compatible = "fcs,fusb302"; + reg = <0x54>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + vbus-supply = <&vbus_typec>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(3000, 12000, 3000) + PDO_PPS_APDO(3000, 11000, 3000)>; + op-sink-microwatt = <10000000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml index 01ab0f922ae8..3fb4feb6d3d9 100644 --- a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml @@ -71,6 +71,9 @@ properties: description: Power pad (PWR) polarity is active low. + power-domains: + maxItems: 1 + # Required child node: patternProperties: @@ -87,12 +90,14 @@ required: - clocks - clock-names - interrupts + - power-domains additionalProperties: false examples: - | #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/power/imx8mp-power.h> #include <dt-bindings/interrupt-controller/arm-gic.h> usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; @@ -102,6 +107,7 @@ examples: <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 994818cb6044..050cfd5acdaa 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -74,6 +74,11 @@ properties: - const: usb-ehci - enum: - generic-ehci + - marvell,armada-3700-ehci + - marvell,orion-ehci + - nuvoton,npcm750-ehci + - nuvoton,npcm845-ehci + - ti,ehci-omap - usb-ehci reg: diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml index 4fcbd0add49d..a9ba7257b884 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: USB OHCI Controller -allOf: - - $ref: "usb-hcd.yaml" - maintainers: - Greg Kroah-Hartman <gregkh@linuxfoundation.org> @@ -49,7 +46,16 @@ properties: - ingenic,jz4740-ohci - snps,hsdk-v1.0-ohci - const: generic-ohci - - const: generic-ohci + - enum: + - generic-ohci + - ti,ohci-omap3 + - items: + - enum: + - cavium,octeon-6335-ohci + - nintendo,hollywood-usb-ohci + - nxp,ohci-nxp + - st,spear600-ohci + - const: usb-ohci reg: maxItems: 1 @@ -119,11 +125,29 @@ properties: - host - otg + transceiver: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The associated ISP1301 device. Necessary for the UDC controller for + connecting to the USB physical layer. + required: - compatible - reg - interrupts +allOf: + - $ref: usb-hcd.yaml + - if: + not: + properties: + compatible: + contains: + const: nxp,ohci-nxp + then: + properties: + transceiver: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml index a9f831448cca..cc4cf92b70d1 100644 --- a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml +++ b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - usb5e3,608 + - usb5e3,610 reg: true diff --git a/Documentation/devicetree/bindings/usb/gpio-sbu-mux.yaml b/Documentation/devicetree/bindings/usb/gpio-sbu-mux.yaml new file mode 100644 index 000000000000..bf4b1d016e1f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/gpio-sbu-mux.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/gpio-sbu-mux.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: GPIO-based SBU mux + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + In USB Type-C applications the SBU lines needs to be connected, disconnected + and swapped depending on the altmode and orientation. This binding describes + a family of hardware solutions which switches between these modes using GPIO + signals. + +properties: + compatible: + items: + - enum: + - onnn,fsusb43l10x + - pericom,pi3usb102 + - const: gpio-sbu-mux + + enable-gpios: + description: Switch enable GPIO + + select-gpios: + description: Orientation select + + vcc-supply: + description: power supply + + mode-switch: + description: Flag the port as possible handle of altmode switching + type: boolean + + orientation-switch: + description: Flag the port as possible handler of orientation switching + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the SBU mux to a TypeC controller for the purpose of + handling altmode muxing and orientation switching. + +required: + - compatible + - enable-gpios + - select-gpios + - mode-switch + - orientation-switch + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + tcpm { + connector { + compatible = "usb-c-connector"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tcpm_hs_out: endpoint { + remote-endpoint = <&usb_hs_phy_in>; + }; + }; + + port@1 { + reg = <1>; + tcpm_ss_out: endpoint { + remote-endpoint = <&usb_ss_phy_in>; + }; + }; + + port@2 { + reg = <2>; + tcpm_sbu_out: endpoint { + remote-endpoint = <&sbu_mux_in>; + }; + }; + }; + }; + }; + + sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + port { + sbu_mux_in: endpoint { + remote-endpoint = <&tcpm_sbu_out>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index a3c37944c630..c119caa9ad16 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci reg: diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 7168110e2f9d..d2655173e108 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 reg: diff --git a/Documentation/devicetree/bindings/usb/npcm7xx-usb.txt b/Documentation/devicetree/bindings/usb/npcm7xx-usb.txt deleted file mode 100644 index 352a0a1e2f76..000000000000 --- a/Documentation/devicetree/bindings/usb/npcm7xx-usb.txt +++ /dev/null @@ -1,20 +0,0 @@ -Nuvoton NPCM7XX SoC USB controllers: ------------------------------ - -EHCI: ------ - -Required properties: -- compatible: should be one of - "nuvoton,npcm750-ehci" - "nuvoton,npcm845-ehci" -- interrupts: Should contain the EHCI interrupt -- reg: Physical address and length of the register set for the device - -Example: - - ehci1: usb@f0806000 { - compatible = "nuvoton,npcm750-ehci"; - reg = <0xf0806000 0x1000>; - interrupts = <0 61 4>; - }; diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index f6cb19efd98b..e638f77658fc 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -22,6 +22,7 @@ properties: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 - nvidia,tegra194-xudc # For Tegra194 + - nvidia,tegra234-xudc # For Tegra234 reg: minItems: 2 @@ -112,6 +113,8 @@ properties: hvdd-usb-supply: description: USB controller power supply. Must supply 3.3 V. + dma-coherent: true + required: - compatible - reg @@ -153,6 +156,7 @@ allOf: enum: - nvidia,tegra186-xudc - nvidia,tegra194-xudc + - nvidia,tegra234-xudc then: properties: reg: @@ -164,6 +168,17 @@ allOf: clock-names: maxItems: 4 + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-xudc + - nvidia,tegra234-xudc + then: + required: + - dma-coherent + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml new file mode 100644 index 000000000000..db761dcbf72a --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 xHCI controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by + the Tegra XUSB pad controller. The xHCI controller controls up to eight + ports; there are four USB 2.0 ports and four USB 3.2 Gen1 x1 ports. + +properties: + compatible: + const: nvidia,tegra234-xusb + + reg: + items: + - description: xHCI host registers + - description: XUSB FPCI registers + - description: XUSB bar2 registers + + reg-names: + items: + - const: hcd + - const: fpci + - const: bar2 + + interrupts: + items: + - description: xHCI host interrupt + - description: mailbox interrupt + + clocks: + items: + - description: XUSB host clock + - description: XUSB Falcon source clock + - description: XUSB SuperSpeed clock + - description: XUSB SuperSpeed source clock + - description: XUSB HighSpeed clock source + - description: XUSB FullSpeed clock source + - description: USB PLL + - description: reference clock + - description: I/O PLL + + clock-names: + items: + - const: xusb_host + - const: xusb_falcon_src + - const: xusb_ss + - const: xusb_ss_src + - const: xusb_hs_src + - const: xusb_fs_src + - const: pll_u_480m + - const: clk_m + - const: pll_e + + interconnects: + items: + - description: read client + - description: write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the XUSB pad controller that is used to configure + the USB pads used by the XHCI controller + + phys: + minItems: 1 + maxItems: 8 + + phy-names: + minItems: 1 + maxItems: 8 + items: + enum: + - usb2-0 + - usb2-1 + - usb2-2 + - usb2-3 + - usb3-0 + - usb3-1 + - usb3-2 + - usb3-3 + + power-domains: + items: + - description: XUSBC power domain (for Host and USB 2.0) + - description: XUSBA power domain (for SuperSpeed) + + power-domain-names: + items: + - const: xusb_host + - const: xusb_ss + + dma-coherent: true + +allOf: + - $ref: usb-xhci.yaml + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra234-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra234-mc.h> + #include <dt-bindings/power/tegra234-powergate.h> + + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + + phys = <&pad_lanes_usb2_0>; + phy-names = "usb2-0"; + }; diff --git a/Documentation/devicetree/bindings/usb/ohci-nxp.txt b/Documentation/devicetree/bindings/usb/ohci-nxp.txt deleted file mode 100644 index 71e28c1017ed..000000000000 --- a/Documentation/devicetree/bindings/usb/ohci-nxp.txt +++ /dev/null @@ -1,24 +0,0 @@ -* OHCI controller, NXP ohci-nxp variant - -Required properties: -- compatible: must be "nxp,ohci-nxp" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The OHCI interrupt -- transceiver: phandle of the associated ISP1301 device - this is necessary for - the UDC controller for connecting to the USB physical layer - -Example (LPC32xx): - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; - - ohci@31020000 { - compatible = "nxp,ohci-nxp"; - reg = <0x31020000 0x300>; - interrupt-parent = <&mic>; - interrupts = <0x3b 0>; - transceiver = <&isp1301>; - }; diff --git a/Documentation/devicetree/bindings/usb/ohci-omap3.txt b/Documentation/devicetree/bindings/usb/ohci-omap3.txt deleted file mode 100644 index ce8c47cff6d0..000000000000 --- a/Documentation/devicetree/bindings/usb/ohci-omap3.txt +++ /dev/null @@ -1,15 +0,0 @@ -OMAP HS USB OHCI controller (OMAP3 and later) - -Required properties: - -- compatible: should be "ti,ohci-omap3" -- reg: should contain one register range i.e. start and length -- interrupts: description of the interrupt line - -Example for OMAP4: - -usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3"; - reg = <0x4a064800 0x400>; - interrupts = <0 76 0x4>; -}; diff --git a/Documentation/devicetree/bindings/usb/pxa-usb.txt b/Documentation/devicetree/bindings/usb/pxa-usb.txt index 9c331799b87c..53fdae4fa6f6 100644 --- a/Documentation/devicetree/bindings/usb/pxa-usb.txt +++ b/Documentation/devicetree/bindings/usb/pxa-usb.txt @@ -22,7 +22,7 @@ Optional properties: Example: usb0: ohci@4c000000 { - compatible = "marvell,pxa-ohci", "usb-ohci"; + compatible = "marvell,pxa-ohci"; reg = <0x4c000000 0x100000>; interrupts = <18>; marvell,enable-port1; diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index a3f8a3f49852..4875c5b7d5b5 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -58,6 +58,9 @@ properties: description: specifies a phandle to PM domain provider node maxItems: 1 + required-opps: + maxItems: 1 + clocks: description: | Several clocks are used, depending on the variant. Typical ones are:: diff --git a/Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml b/Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml new file mode 100644 index 000000000000..b6e84a2a6925 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/renesas,rzn1-usbf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs USBF (USB Function) controller + +description: | + The Renesas USBF controller is an USB2.0 device + controller (UDC). + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-usbf + - const: renesas,rzn1-usbf + + reg: + maxItems: 1 + + clocks: + items: + - description: Internal bus clock (AHB) for Function + - description: Internal bus clock (AHB) for Power Management + + clock-names: + items: + - const: hclkf + - const: hclkpm + + power-domains: + maxItems: 1 + + interrupts: + items: + - description: The USBF EPC interrupt + - description: The USBF AHB-EPC interrupt + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + usb@4001e000 { + compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; + reg = <0x4001e000 0x2000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_USBF>, + <&sysctrl R9A06G032_HCLK_USBPM>; + clock-names = "hclkf", "hclkpm"; + power-domains = <&sysctrl>; + }; diff --git a/Documentation/devicetree/bindings/usb/renesas,rzv2m-usb3drd.yaml b/Documentation/devicetree/bindings/usb/renesas,rzv2m-usb3drd.yaml new file mode 100644 index 000000000000..ff625600d9af --- /dev/null +++ b/Documentation/devicetree/bindings/usb/renesas,rzv2m-usb3drd.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/renesas,rzv2m-usb3drd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M USB 3.1 DRD controller + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + The RZ/V2{M, MA} USB3.1 DRD module supports the following functions + * Role swapping function by the ID pin of the Micro-AB receptacle + * Battery Charging Specification Revision 1.2 + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-usb3drd # RZ/V2M + - renesas,r9a09g055-usb3drd # RZ/V2MA + - const: renesas,rzv2m-usb3drd + + reg: + maxItems: 1 + + interrupts: + items: + - description: Dual Role Device (DRD) + - description: Battery Charging + - description: Global Purpose Input + + interrupt-names: + items: + - const: drd + - const: bc + - const: gpi + + clocks: + items: + - description: Peripheral AXI clock + - description: APB clock + + clock-names: + items: + - const: axi + - const: reg + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + ranges: true + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +patternProperties: + "^usb3peri@[0-9a-f]+$": + type: object + $ref: /schemas/usb/renesas,usb3-peri.yaml + + "^usb@[0-9a-f]+$": + type: object + $ref: renesas,usb-xhci.yaml# + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a09g011-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb3drd: usb@85070400 { + compatible = "renesas,r9a09g011-usb3drd", "renesas,rzv2m-usb3drd"; + reg = <0x85070400 0x100>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "drd", "bc", "gpi"; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_USB_DRD_RESET>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + usb3host: usb@85060000 { + compatible = "renesas,r9a09g011-xhci", + "renesas,rzv2m-xhci"; + reg = <0x85060000 0x2000>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_USB_ARESETN_H>; + }; + + usb3peri: usb3peri@85070000 { + compatible = "renesas,r9a09g011-usb3-peri", + "renesas,rzv2m-usb3-peri"; + reg = <0x85070000 0x400>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_USB_ARESETN_P>; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml index 4c5efaf02308..1a07c0d2b1b1 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml @@ -10,9 +10,6 @@ maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -allOf: - - $ref: "usb-xhci.yaml" - properties: compatible: oneOf: @@ -37,6 +34,11 @@ properties: - renesas,xhci-r8a77965 # R-Car M3-N - renesas,xhci-r8a77990 # R-Car E3 - const: renesas,rcar-gen3-xhci # R-Car Gen3 and RZ/G2 + - items: + - enum: + - renesas,r9a09g011-xhci # RZ/V2M + - renesas,r9a09g055-xhci # RZ/V2MA + - const: renesas,rzv2m-xhci # RZ/{V2M, V2MA} reg: maxItems: 1 @@ -45,7 +47,16 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Main clock for host + - description: Register access clock + + clock-names: + minItems: 1 + items: + - const: axi + - const: reg phys: maxItems: 1 @@ -68,6 +79,28 @@ required: - power-domains - resets +allOf: + - $ref: usb-xhci.yaml + + - if: + properties: + compatible: + contains: + enum: + - renesas,rzv2m-xhci + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml index 55dfd121b555..b2b811a0ade8 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml @@ -28,26 +28,14 @@ properties: - items: - enum: - renesas,r9a09g011-usb3-peri # RZ/V2M + - renesas,r9a09g055-usb3-peri # RZ/V2MA - const: renesas,rzv2m-usb3-peri reg: maxItems: 1 interrupts: - minItems: 1 - items: - - description: Combined interrupt for DMA, SYS and ERR - - description: Dual Role Device (DRD) - - description: Battery Charging - - description: Global Purpose Input - - interrupt-names: - minItems: 1 - items: - - const: all_p - - const: drd - - const: bc - - const: gpi + maxItems: 1 clocks: minItems: 1 @@ -58,7 +46,7 @@ properties: clock-names: minItems: 1 items: - - const: aclk + - const: axi - const: reg phys: @@ -71,15 +59,7 @@ properties: maxItems: 1 resets: - minItems: 1 - items: - - description: Peripheral reset - - description: DRD reset - - reset-names: - items: - - const: aresetn_p - - const: drd_reset + maxItems: 1 usb-role-switch: $ref: /schemas/types.yaml#/definitions/flag @@ -127,25 +107,13 @@ allOf: minItems: 2 clock-names: minItems: 2 - interrupts: - minItems: 4 - interrupt-names: - minItems: 4 - resets: - minItems: 2 required: - clock-names - - interrupt-names - resets - - reset-names else: properties: clocks: maxItems: 1 - interrupts: - maxItems: 1 - resets: - maxItems: 1 additionalProperties: false diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml index b3798d94d2fd..291844c8f3e1 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -29,7 +29,6 @@ select: contains: enum: - rockchip,rk3328-dwc3 - - rockchip,rk3399-dwc3 - rockchip,rk3568-dwc3 required: - compatible @@ -39,7 +38,6 @@ properties: items: - enum: - rockchip,rk3328-dwc3 - - rockchip,rk3399-dwc3 - rockchip,rk3568-dwc3 - const: snps,dwc3 @@ -90,7 +88,7 @@ required: examples: - | - #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/clock/rk3328-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> bus { @@ -98,11 +96,11 @@ examples: #size-cells = <2>; usbdrd3_0: usb@fe800000 { - compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; + compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>; clock-names = "ref_clk", "suspend_clk", "bus_clk", "grf_clk"; dr_mode = "otg"; diff --git a/Documentation/devicetree/bindings/usb/rockchip,rk3399-dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,rk3399-dwc3.yaml new file mode 100644 index 000000000000..3159f9a6a0f7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/rockchip,rk3399-dwc3.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + const: rockchip,rk3399-dwc3 + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + ranges: true + + clocks: + items: + - description: + Controller reference clock, must to be 24 MHz + - description: + Controller suspend clock, must to be 24 MHz or 32 KHz + - description: + Master/Core clock, must to be >= 62.5 MHz for SS + operation and >= 30MHz for HS operation + - description: + USB3 aclk peri + - description: + USB3 aclk + - description: + Controller grf clock + + clock-names: + items: + - const: ref_clk + - const: suspend_clk + - const: bus_clk + - const: aclk_usb3_rksoc_axi_perf + - const: aclk_usb3 + - const: grf_clk + + resets: + maxItems: 1 + + reset-names: + const: usb3-otg + +patternProperties: + '^usb@': + $ref: snps,dwc3.yaml# + +additionalProperties: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/power/rk3399-power.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + usb { + compatible = "rockchip,rk3399-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + resets = <&cru SRST_A_USB3_OTG0>; + reset-names = "usb3-otg"; + + usb@fe800000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, + <&cru SCLK_USB3OTG0_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml index 6b9a3bcb3926..42ceaf13cd5d 100644 --- a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml @@ -108,19 +108,19 @@ examples: #include <dt-bindings/clock/exynos5420.h> #include <dt-bindings/interrupt-controller/arm-gic.h> - usb { + usb@12000000 { compatible = "samsung,exynos5250-dwusb3"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x12000000 0x10000>; clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; vdd33-supply = <&ldo9_reg>; vdd10-supply = <&ldo11_reg>; - usb@12000000 { + usb@0 { compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; + reg = <0x0 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; phy-names = "usb2-phy", "usb3-phy"; diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 6d78048c4613..be36956af53b 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -91,6 +91,16 @@ properties: - usb2-phy - usb3-phy + power-domains: + description: + The DWC3 has 2 power-domains. The power management unit (PMU) and + everything else. The PMU is typically always powered and may not have an + entry. + minItems: 1 + items: + - description: Core + - description: Power management unit + resets: minItems: 1 diff --git a/Documentation/devicetree/bindings/usb/spear-usb.txt b/Documentation/devicetree/bindings/usb/spear-usb.txt deleted file mode 100644 index 1dc91cc459c0..000000000000 --- a/Documentation/devicetree/bindings/usb/spear-usb.txt +++ /dev/null @@ -1,35 +0,0 @@ -ST SPEAr SoC USB controllers: ------------------------------ - -EHCI: ------ - -Required properties: -- compatible: "st,spear600-ehci" -- interrupts: Should contain the EHCI interrupt - -Example: - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - }; - - -OHCI: ------ - -Required properties: -- compatible: "st,spear600-ohci" -- interrupts: Should contain the OHCI interrupt - -Example: - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - }; diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml index b86bf6bc9cd6..a1cffb70c621 100644 --- a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml +++ b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml @@ -46,7 +46,6 @@ properties: required: - compatible - reg - - interrupts additionalProperties: false diff --git a/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml index fef4acdc4773..348a715d61f4 100644 --- a/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml +++ b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml @@ -23,6 +23,8 @@ properties: reg: maxItems: 1 + wakeup-source: true + interrupts: maxItems: 1 @@ -48,6 +50,7 @@ examples: tps6598x: tps6598x@38 { compatible = "ti,tps6598x"; reg = <0x38>; + wakeup-source; interrupt-parent = <&msmgpio>; interrupts = <107 IRQ_TYPE_LEVEL_LOW>; diff --git a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml index 326131dcf14d..921b986adc47 100644 --- a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml +++ b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.yaml @@ -35,7 +35,7 @@ properties: maxItems: 1 vbus-regulator: - description: Should specifiy the regulator supplying current drawn from + description: Should specify the regulator supplying current drawn from the VBus line. $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt index b796836d2ce7..29b8f65ff849 100644 --- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt @@ -8,6 +8,7 @@ Required properties: "fsl,imx6sx-usbmisc" for imx6sx "fsl,imx7d-usbmisc" for imx7d "fsl,imx7ulp-usbmisc" for imx7ulp + "fsl,imx8mm-usbmisc" for imx8mm - reg: Should contain registers location and length Examples: diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml new file mode 100644 index 000000000000..23a13e1d5c7a --- /dev/null +++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/vialab,vl817.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Via labs VL817 USB 3.1 hub controller + +maintainers: + - Anand Moon <linux.amoon@gmail.com> + +allOf: + - $ref: usb-device.yaml# + +properties: + compatible: + enum: + - usb2109,2817 + - usb2109,817 + + reg: true + + reset-gpios: + maxItems: 1 + description: + GPIO controlling the RESET# pin. + + vdd-supply: + description: + phandle to the regulator that provides power to the hub. + + peer-hub: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the peer hub on the controller. + +required: + - compatible + - reg + - reset-gpios + - vdd-supply + - peer-hub + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + usb { + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <1>; + vdd-supply = <&vcc_5v>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + + /* 3.1 hub on port 4 */ + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <2>; + vdd-supply = <&vcc_5v>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 70ffb3780621..ed64e06ecca4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -69,6 +69,8 @@ patternProperties: description: Annapurna Labs "^alcatel,.*": description: Alcatel + "^aldec,.*": + description: Aldec, Inc. "^alfa-network,.*": description: ALFA Network Inc. "^allegro,.*": @@ -264,6 +266,8 @@ patternProperties: description: Cirrus Logic, Inc. "^cisco,.*": description: Cisco Systems, Inc. + "^clockwork,.*": + description: Clockwork Tech LLC "^cloos,.*": description: Carl Cloos Schweisstechnik GmbH. "^cloudengines,.*": @@ -374,6 +378,8 @@ patternProperties: description: EBV Elektronik "^eckelmann,.*": description: Eckelmann AG + "^edgeble,.*": + description: Edgeble AI Technologies Pvt. Ltd. "^edimax,.*": description: EDIMAX Technology Co., Ltd "^edt,.*": @@ -396,6 +402,8 @@ patternProperties: description: Elimo Engineering Ltd. "^elpida,.*": description: Elpida Memory, Inc. + "^embedfire,.*": + description: Dongguan EmbedFire Electronic Technology Co., Ltd. "^embest,.*": description: Shenzhen Embest Technology Co., Ltd. "^emlid,.*": @@ -512,6 +520,8 @@ patternProperties: description: Shenzhen Huiding Technology Co., Ltd. "^google,.*": description: Google, Inc. + "^gplus,.*": + description: GPLUS "^grinn,.*": description: Grinn "^grmn,.*": @@ -635,6 +645,8 @@ patternProperties: description: Inverse Path "^iom,.*": description: Iomega Corporation + "^irondevice,.*": + description: Iron Device Corporation "^isee,.*": description: ISEE 2007 S.L. "^isil,.*": @@ -729,6 +741,8 @@ patternProperties: description: Lichee Pi "^linaro,.*": description: Linaro Limited + "^lineartechnology,.*": + description: Linear Technology "^linksprite,.*": description: LinkSprite Technologies, Inc. "^linksys,.*": @@ -775,6 +789,8 @@ patternProperties: description: MaxBotix Inc. "^maxim,.*": description: Maxim Integrated Products + "^maxlinear,.*": + description: MaxLinear Inc. "^mbvl,.*": description: Mobiveil Inc. "^mcube,.*": @@ -845,6 +861,8 @@ patternProperties: description: Moortec Semiconductor Ltd. "^mosaixtech,.*": description: Mosaix Technologies, Inc. + "^motorcomm,.*": + description: MotorComm, Inc. "^motorola,.*": description: Motorola, Inc. "^moxa,.*": @@ -1025,6 +1043,8 @@ patternProperties: description: PocketBook International SA "^polaroid,.*": description: Polaroid Corporation + "^polyhex,.*": + description: Polyhex Technology Co. Ltd. "^portwell,.*": description: Portwell Inc. "^poslab,.*": @@ -1246,6 +1266,8 @@ patternProperties: description: Starry Electronic Technology (ShenZhen) Co., LTD "^startek,.*": description: Startek + "^starterkit,.*": + description: Starterkit "^ste,.*": description: ST-Ericsson deprecated: true @@ -1319,6 +1341,8 @@ patternProperties: description: thingy.jp "^thundercomm,.*": description: Thundercomm Technology Co., Ltd. + "^thwc,.*": + description: Shenzhen Tong Heng Wei Chuang Technology Co., Ltd. "^ti,.*": description: Texas Instruments "^tianma,.*": @@ -1372,6 +1396,8 @@ patternProperties: description: uCRobotics "^udoo,.*": description: Udoo + "^ufispace,.*": + description: Ufi Space Co., Ltd. "^ugoos,.*": description: Ugoos Industrial Co., Ltd. "^uniwest,.*": @@ -1398,6 +1424,8 @@ patternProperties: description: Vertexcom Technologies, Inc. "^via,.*": description: VIA Technologies, Inc. + "^vialab,.*": + description: VIA Labs, Inc. "^vicor,.*": description: Vicor Corporation "^videostrong,.*": @@ -1444,6 +1472,8 @@ patternProperties: description: Shenzhen whwave Electronics, Inc. "^wi2wi,.*": description: Wi2Wi, Inc. + "^widora,.*": + description: Beijing Widora Technology Co., Ltd. "^wiligear,.*": description: Wiligear, Ltd. "^willsemi,.*": diff --git a/Documentation/devicetree/bindings/watchdog/amlogic,meson6-wdt.yaml b/Documentation/devicetree/bindings/watchdog/amlogic,meson6-wdt.yaml new file mode 100644 index 000000000000..84732cb58ec4 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/amlogic,meson6-wdt.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/amlogic,meson6-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson6 SoCs Watchdog timer + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - enum: + - amlogic,meson6-wdt + - amlogic,meson8-wdt + - amlogic,meson8b-wdt + - items: + - const: amlogic,meson8m2-wdt + - const: amlogic,meson8b-wdt + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + wdt: watchdog@c1109900 { + compatible = "amlogic,meson6-wdt"; + reg = <0xc1109900 0x8>; + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; + timeout-sec = <10>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml index fb7695515be1..181f0cc5b5bd 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -9,9 +9,6 @@ title: Freescale i.MX Watchdog Timer (WDT) Controller maintainers: - Anson Huang <Anson.Huang@nxp.com> -allOf: - - $ref: "watchdog.yaml#" - properties: compatible: oneOf: @@ -55,11 +52,45 @@ properties: If present, the watchdog device is configured to assert its external reset (WDOG_B) instead of issuing a software reset. + fsl,suspend-in-wait: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If present, the watchdog device is suspended in WAIT mode + (Suspend-to-Idle). Only supported on certain devices. + required: - compatible - interrupts - reg +allOf: + - $ref: watchdog.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx25-wdt + - fsl,imx35-wdt + - fsl,imx50-wdt + - fsl,imx51-wdt + - fsl,imx53-wdt + - fsl,imx6q-wdt + - fsl,imx6sl-wdt + - fsl,imx6sll-wdt + - fsl,imx6sx-wdt + - fsl,imx6ul-wdt + - fsl,imx7d-wdt + - fsl,imx8mm-wdt + - fsl,imx8mn-wdt + - fsl,imx8mp-wdt + - fsl,imx8mq-wdt + - fsl,vf610-wdt + then: + properties: + fsl,suspend-in-wait: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/watchdog/gpio-wdt.yaml b/Documentation/devicetree/bindings/watchdog/gpio-wdt.yaml new file mode 100644 index 000000000000..155dc7965e9b --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/gpio-wdt.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/gpio-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO controlled watchdog + +maintainers: + - Robert Marko <robert.marko@sartura.hr> + +properties: + compatible: + const: linux,wdt-gpio + + gpios: + maxItems: 1 + description: GPIO connected to the WDT reset pin + + hw_algo: + $ref: /schemas/types.yaml#/definitions/string + description: Algorithm used by the driver + oneOf: + - description: + Either a high-to-low or a low-to-high transition clears the WDT counter. + The watchdog timer is disabled when GPIO is left floating or connected + to a three-state buffer. + const: toggle + - description: + Low or high level starts counting WDT timeout, the opposite level + disables the WDT. + Active level is determined by the GPIO flags. + const: level + + hw_margin_ms: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Maximum time to reset watchdog circuit (in milliseconds) + minimum: 2 + maximum: 65535 + + always-running: + type: boolean + description: + If the watchdog timer cannot be disabled, add this flag to have the driver + keep toggling the signal without a client. + It will only cease to toggle the signal when the device is open and the + timeout elapsed. + +required: + - compatible + - gpios + - hw_algo + - hw_margin_ms + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/watchdog/maxim,max63xx.yaml b/Documentation/devicetree/bindings/watchdog/maxim,max63xx.yaml index ab9641e845db..38079e1b6a44 100644 --- a/Documentation/devicetree/bindings/watchdog/maxim,max63xx.yaml +++ b/Documentation/devicetree/bindings/watchdog/maxim,max63xx.yaml @@ -8,6 +8,7 @@ title: Maxim 63xx Watchdog Timers allOf: - $ref: "watchdog.yaml#" + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# maintainers: - Marc Zyngier <maz@kernel.org> diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml index b2b17fdf4e39..a668d0c2f14b 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml @@ -19,6 +19,12 @@ properties: reg: maxItems: 1 + mediatek,sysctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to system controller 'sysc' syscon node which + controls system registers + required: - compatible - reg @@ -30,4 +36,5 @@ examples: watchdog@100 { compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; + mediatek,sysctl = <&sysc>; }; diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index b3605608410c..55b34461df1b 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -52,6 +52,12 @@ properties: description: Disable sending output reset signal type: boolean + mediatek,reset-by-toprgu: + description: The Top Reset Generation Unit (TOPRGU) generates reset signals + and distributes them to each IP. If present, the watchdog timer will be + reset by TOPRGU once system resets. + type: boolean + '#reset-cells': const: 1 diff --git a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt deleted file mode 100644 index 7588cc3971bf..000000000000 --- a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt +++ /dev/null @@ -1,21 +0,0 @@ -Meson SoCs Watchdog timer - -Required properties: - -- compatible : depending on the SoC this should be one of: - "amlogic,meson6-wdt" on Meson6 SoCs - "amlogic,meson8-wdt" and "amlogic,meson6-wdt" on Meson8 SoCs - "amlogic,meson8b-wdt" on Meson8b SoCs - "amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs -- reg : Specifies base physical address and size of the registers. - -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -wdt: watchdog@c1109900 { - compatible = "amlogic,meson6-wdt"; - reg = <0xc1109900 0x8>; - timeout-sec = <10>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index d8ac0be36e6c..6448b633c970 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -9,15 +9,18 @@ title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer maintainers: - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> -allOf: - - $ref: watchdog.yaml# - properties: + $nodename: + pattern: "^(watchdog|timer)@[0-9a-f]+$" + compatible: oneOf: - items: - enum: + - qcom,kpss-wdt-ipq4019 + - qcom,apss-wdt-msm8994 - qcom,apss-wdt-qcs404 + - qcom,apss-wdt-sa8775p - qcom,apss-wdt-sc7180 - qcom,apss-wdt-sc7280 - qcom,apss-wdt-sc8180x @@ -29,15 +32,19 @@ properties: - qcom,apss-wdt-sm8150 - qcom,apss-wdt-sm8250 - const: qcom,kpss-wdt + - const: qcom,kpss-wdt + deprecated: true + - items: + - const: qcom,scss-timer + - const: qcom,msm-timer - items: - enum: - - qcom,kpss-wdt - - qcom,kpss-timer - qcom,kpss-wdt-apq8064 - - qcom,kpss-wdt-ipq4019 - qcom,kpss-wdt-ipq8064 + - qcom,kpss-wdt-mdm9615 - qcom,kpss-wdt-msm8960 - - qcom,scss-timer + - const: qcom,kpss-timer + - const: qcom,msm-timer reg: maxItems: 1 @@ -45,18 +52,87 @@ properties: clocks: maxItems: 1 + clock-names: + items: + - const: sleep + + clock-frequency: + description: + The frequency of the general purpose timer in Hz. + + cpu-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Per-CPU offset used when the timer is accessed without the CPU remapping + facilities. The offset is cpu-offset + (0x10000 * cpu-nr). + + interrupts: + minItems: 1 + maxItems: 5 + required: - compatible - reg - clocks +allOf: + - $ref: watchdog.yaml# + + - if: + properties: + compatible: + contains: + const: qcom,kpss-wdt + then: + properties: + clock-frequency: false + cpu-offset: false + interrupts: + minItems: 1 + items: + - description: Bark + - description: Bite + + else: + properties: + interrupts: + minItems: 3 + items: + - description: Debug + - description: First general purpose timer + - description: Second general purpose timer + - description: First watchdog + - description: Second watchdog + required: + - clock-frequency + unevaluatedProperties: false examples: - | - watchdog@208a038 { - compatible = "qcom,kpss-wdt-ipq8064"; - reg = <0x0208a038 0x40>; + #include <dt-bindings/interrupt-controller/arm-gic.h> + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; + reg = <0x17c10000 0x1000>; clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; timeout-sec = <10>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + watchdog@200a000 { + compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; + cpu-offset = <0x80000>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 26b1815a6753..e2c9bf1aec38 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -26,7 +26,7 @@ properties: - items: - enum: - - renesas,r9a07g043-wdt # RZ/G2UL + - renesas,r9a07g043-wdt # RZ/G2UL and RZ/Five - renesas,r9a07g044-wdt # RZ/G2{L,LC} - renesas,r9a07g054-wdt # RZ/V2L - const: renesas,rzg2l-wdt diff --git a/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml b/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml index 90698cfa8f94..70c005fdd197 100644 --- a/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml @@ -25,12 +25,6 @@ examples: - | // The UniPhier watchdog should be a subnode of a "syscon" compatible node. - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; + watchdog { + compatible = "socionext,uniphier-wdt"; }; diff --git a/Documentation/devicetree/bindings/watchdog/watchdog.yaml b/Documentation/devicetree/bindings/watchdog/watchdog.yaml index fccae0d00110..519b48889eb1 100644 --- a/Documentation/devicetree/bindings/watchdog/watchdog.yaml +++ b/Documentation/devicetree/bindings/watchdog/watchdog.yaml @@ -14,9 +14,14 @@ description: | This document describes generic bindings which can be used to describe watchdog devices in a device tree. +select: + properties: + $nodename: + pattern: "^watchdog(@.*|-[0-9a-f])?$" + properties: $nodename: - pattern: "^watchdog(@.*|-[0-9a-f])?$" + pattern: "^(timer|watchdog)(@.*|-[0-9a-f])?$" timeout-sec: description: |