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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ocelot Externally-Controlled Ethernet Switch
maintainers:
- Colin Foster <colin.foster@in-advantage.com>
description: |
The Ocelot ethernet switch family contains chips that have an internal CPU
(VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
the option to be controlled externally via external interfaces like SPI or
PCIe.
The switch family is a multi-port networking switch that supports many
interfaces. Additionally, the device can perform pin control, MDIO buses, and
external GPIO expanders.
properties:
compatible:
enum:
- mscc,vsc7512
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
spi-max-frequency:
maxItems: 1
patternProperties:
"^pinctrl@[0-9a-f]+$":
type: object
$ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
"^gpio@[0-9a-f]+$":
type: object
$ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
properties:
compatible:
enum:
- mscc,ocelot-sgpio
"^mdio@[0-9a-f]+$":
type: object
$ref: /schemas/net/mscc,miim.yaml
properties:
compatible:
enum:
- mscc,ocelot-miim
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
ocelot_clock: ocelot-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
spi {
#address-cells = <1>;
#size-cells = <0>;
soc@0 {
compatible = "mscc,vsc7512";
spi-max-frequency = <2500000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mdio@7107009c {
compatible = "mscc,ocelot-miim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7107009c 0x24>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
};
mdio@710700c0 {
compatible = "mscc,ocelot-miim";
pinctrl-names = "default";
pinctrl-0 = <&miim1_pins>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x710700c0 0x24>;
sw_phy4: ethernet-phy@4 {
reg = <0x4>;
};
};
gpio: pinctrl@71070034 {
compatible = "mscc,ocelot-pinctrl";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
reg = <0x71070034 0x6c>;
sgpio_pins: sgpio-pins {
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
function = "sg0";
};
miim1_pins: miim1-pins {
pins = "GPIO_14", "GPIO_15";
function = "miim";
};
};
gpio@710700f8 {
compatible = "mscc,ocelot-sgpio";
#address-cells = <1>;
#size-cells = <0>;
bus-frequency = <12500000>;
clocks = <&ocelot_clock>;
microchip,sgpio-port-ranges = <0 15>;
pinctrl-names = "default";
pinctrl-0 = <&sgpio_pins>;
reg = <0x710700f8 0x100>;
sgpio_in0: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
reg = <0>;
gpio-controller;
#gpio-cells = <3>;
ngpios = <64>;
};
sgpio_out1: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
reg = <1>;
gpio-controller;
#gpio-cells = <3>;
ngpios = <64>;
};
};
};
};
...
|
