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| author | Jouni Högander <jouni.hogander@intel.com> | 2024-03-19 15:33:24 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-04-03 21:26:10 +0300 |
| commit | 4e29234353a4378a49e5ee6f5683678d7e101e17 (patch) | |
| tree | a8c4429e22c62a29a1c35c09e33254b33c516020 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 64d845f651267deb62bcf013ce37e2360161fdf1 (diff) | |
| download | linux-4e29234353a4378a49e5ee6f5683678d7e101e17.tar.xz | |
drm/i915/psr: Move writing early transport pipe src
Currently PIPE_SRCSZ_ERLY_TPT is written in
intel_display.c:intel_set_pipe_src_size. This doesn't work as
intel_set_pipe_src_size is called only on modeset.
Bspec: 68927
Fixes: 3291bbb93e16 ("drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-3-jouni.hogander@intel.com
(cherry picked from commit b52c4093b0c9089b00b42823d41986a94d32e341)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions