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| author | Jouni Högander <jouni.hogander@intel.com> | 2024-03-19 15:33:23 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-04-03 21:26:09 +0300 |
| commit | 64d845f651267deb62bcf013ce37e2360161fdf1 (patch) | |
| tree | 4ded40623ce07f7309514dfcdd56403dccb8e626 /tools/perf/scripts/python/task-analyzer.py | |
| parent | caf3d748f646889425312897e81307441160d485 (diff) | |
| download | linux-64d845f651267deb62bcf013ce37e2360161fdf1.tar.xz | |
drm/i915/psr: Calculate PIPE_SRCSZ_ERLY_TPT value
When early transport is enabled we need to write PIPE_SRCSZ_ERLY_TPT on
every flip doing selective update. This patch calculates
PIPE_SRCSZ_ERLY_TPT same way as is done for PSR2_MAN_TRK_CTL value and
stores i in intel_crtc_state->pipe_srcsz_early_tpt to be written later
during flip.
Bspec: 68927
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-2-jouni.hogander@intel.com
(cherry picked from commit f3b899f0b4b17fa0b20e27c23f78604d5686383d)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions