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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2025-02-24 16:11:27 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2025-02-26 13:59:50 +0300 |
| commit | e3a16c33db69ffd1369ebfdf93f93a93a785896a (patch) | |
| tree | b7b4e05697484e35a655bf2542444dc725444360 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 76c3b774734feb8224b78721e0c67a54760a75c5 (diff) | |
| download | linux-e3a16c33db69ffd1369ebfdf93f93a93a785896a.tar.xz | |
irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL_{MASK,PREP}
On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H.
Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved
bits is ignored.
Use bitmask GENMASK(field_width - 2, 0) on both SoCs for extracting TSSEL
and then update the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK for
supporting both SoCs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/all/20250224131253.134199-12-biju.das.jz@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions