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| author | Manasi Navare <manasi.d.navare@intel.com> | 2018-10-31 03:19:22 +0300 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-01 00:10:08 +0300 |
| commit | 6cfd04b018f0a37e6d499ffd8382ff93c3f80798 (patch) | |
| tree | d8d5c97285c2d50cc045b1f92f2266c78f38e242 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | d9218c8f6cf43bc0db5422e6b05b9e487c400a23 (diff) | |
| download | linux-6cfd04b018f0a37e6d499ffd8382ff93c3f80798.tar.xz | |
drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-6-manasi.d.navare@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions