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| author | Manasi Navare <manasi.d.navare@intel.com> | 2018-10-31 03:19:21 +0300 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-01 00:09:44 +0300 |
| commit | d9218c8f6cf43bc0db5422e6b05b9e487c400a23 (patch) | |
| tree | 7d3cc681eec9967e911de82593d1a3a6b8967c1b /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 0575650077eae2a431f33532de4e15405cc9f653 (diff) | |
| download | linux-d9218c8f6cf43bc0db5422e6b05b9e487c400a23.tar.xz | |
drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as input arguments
so that this can be called in intel_dp_mode_valid (Manasi)
v5:
* Get the max slice width from DPCD
* Check against Min_Slice_width of 2560 (Anusha)
v4:
* #defines for PPR in slice count helper (Gaurav)
v3:
* Simply logic for bpp (DK)
* Limit the valid slice count by max supported by Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling
big joiner yet (Anusha)
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-5-manasi.d.navare@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions
