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| author | Tudor Ambarus <tudor.ambarus@linaro.org> | 2024-09-26 17:19:53 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@linaro.org> | 2024-10-02 10:23:56 +0300 |
| commit | 6a42bc97ccda237a54c4ec27aed5fa9c51517d40 (patch) | |
| tree | 515e79c15d6f09cf8fc5eca3488861fb14b7f083 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | ccac858d2bdb4f6eb97e903744d94f52046e742a (diff) | |
| download | linux-6a42bc97ccda237a54c4ec27aed5fa9c51517d40.tar.xz | |
mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
mode compared to STR modes. Allow operations to specify the byte order in
DTR mode, so that controllers can swap the bytes back at run-time to
address the flash's endianness requirements, if they are capable. If the
controller is not capable of swapping the bytes, the protocol is downgrade
via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the
bytes is always done regardless if it's a data or register access, so that
it comply with the JESD216 requirements: "Byte order of 16-bit words is
swapped when read in 8D-8D-8D mode compared to 1-1-1".
Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.
Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
Link: https://lore.kernel.org/r/20240926141956.2386374-4-alvinzhou.tw@gmail.com
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions