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| author | AlvinZhou <alvinzhou@mxic.com.tw> | 2024-09-26 17:19:51 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@linaro.org> | 2024-10-02 10:22:49 +0300 |
| commit | ccac858d2bdb4f6eb97e903744d94f52046e742a (patch) | |
| tree | ed7b88585c3440a0b5687d71ae953d939f69d6a6 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 50cb86f21ec2ede08d0ec0479fbd8697a8a25616 (diff) | |
| download | linux-ccac858d2bdb4f6eb97e903744d94f52046e742a.tar.xz | |
mtd: spi-nor: add Octal DTR support for Macronix flash
Create Macronix specify method for enable Octal DTR mode and
set 20 dummy cycles to allow running at the maximum supported
frequency for Macronix Octal flash.
Use number of dummy cycles which is parse by SFDP then convert
it to bit pattern and set in CR2 register.
Set CR2 register for enable octal DTR mode.
Use Read ID to confirm that enabling/disabling octal DTR mode
was successful.
Macronix ID format is A-A-B-B-C-C in octal DTR mode.
To ensure the successful enablement of octal DTR mode, confirm
that the 6-byte data is entirely correct.
Co-developed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
Link: https://lore.kernel.org/r/20240926141956.2386374-2-alvinzhou.tw@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions