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authorBjorn Helgaas <bhelgaas@google.com>2025-03-27 21:14:51 +0300
committerBjorn Helgaas <bhelgaas@google.com>2025-03-27 21:14:51 +0300
commit6547faa1bc25c4392473b80615cc30088295c89c (patch)
treead28477054e51a71f3f4972f91dec53b2f40aee0 /tools/perf/scripts/python/mem-phys-addr.py
parentd7f6f07ecec9594e95407cfa90e1364e51b2a476 (diff)
parent42c812d07088777a3439e51bd1461d215151150e (diff)
downloadlinux-6547faa1bc25c4392473b80615cc30088295c89c.tar.xz
Merge branch 'pci/controller/qcom'
- Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as RESERVED (Manivannan Sadhasivam) - Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry Baryshkov) - Make DT iommu property required for SA8775P and prohibited for SDX55 (Dmitry Baryshkov) - Add DT iommu and DMA-related properties for Qualcomm SM8450 (Dmitry Baryshkov) - Consolidate DMA vs non-DMA cases in DT (Dmitry Baryshkov) - Add endpoint DT properties for SAR2130P and enable endpoint mode in driver (Dmitry Baryshkov) * pci/controller/qcom: PCI: qcom-ep: Enable EP mode support for SAR2130P dt-bindings: PCI: qcom-ep: Add SAR2130P compatible dt-bindings: PCI: qcom-ep: Consolidate DMA vs non-DMA cases dt-bindings: PCI: qcom-ep: Enable DMA for SM8450 dt-bindings: PCI: qcom-ep: Describe optional IOMMU dt-bindings: PCI: qcom-ep: Describe optional dma-coherent property PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED
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