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| author | Shiju Jose <shiju.jose@huawei.com> | 2025-01-11 12:17:51 +0300 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-01-13 19:33:21 +0300 |
| commit | 5e31e3477f1661ebbbec1cbf141f91ad3cffafc3 (patch) | |
| tree | 9d481aab4250c2b63a1a68c4f6769d3dc22216a2 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 2f84d072bdcb7d6ec66cc4d0de9f37a3dc394cd2 (diff) | |
| download | linux-5e31e3477f1661ebbbec1cbf141f91ad3cffafc3.tar.xz | |
cxl/events: Update Common Event Record to CXL spec rev 3.1
CXL spec 3.1 section 8.2.9.2.1 Table 8-42, Common Event Record format has
updated with Maintenance Operation Subclass information.
Add updates for the above spec change in the CXL events record and CXL
common trace event implementations.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Link: https://patch.msgid.link/20250111091756.1682-2-shiju.jose@huawei.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions