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authorAlejandro Lucero <alucerop@amd.com>2024-12-03 19:21:12 +0300
committerDave Jiang <dave.jiang@intel.com>2025-01-02 23:09:13 +0300
commit2f84d072bdcb7d6ec66cc4d0de9f37a3dc394cd2 (patch)
tree4c10abc8ef2935830132db5b21bbbdf7b7ac8398 /tools/perf/scripts/python/mem-phys-addr.py
parentc8e88de1b44e58cacdef41ea9aaa78fca35f1357 (diff)
downloadlinux-2f84d072bdcb7d6ec66cc4d0de9f37a3dc394cd2.tar.xz
cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()
In cxl_dvsec_rr_decode() the pci driver expects to retrieve a cxlds, struct cxl_dev_state, from the driver_data field of struct device. While that works for Type 3, drivers for Type 1/2 devices may not put a cxlds in the driver_data field. In preparation for supporting Type 1/2 devices, replace parameter 'struct device' with 'struct cxl_dev_state' in cxl_dvsec_rr_decode(). Remove the unused parameter 'cxl_port' in cxl_dvsec_rr_decode(). Signed-off-by: Alejandro Lucero <alucerop@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20241203162112.5088-1-alucerop@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
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