arm64: dts: socfpga: agilex5: Add SMMU nodes

Agilex5 includes an ARM SMMU v3 (System Memory Management Unit) to provide
address translation and memory protection for DMA-capable devices such as
PCIe, USB, and other peripherals.

This commit adds the SMMU node to the Agilex5 device tree with compatible
string "arm,smmu-v3", along with its register space and interrupts.

The SMMU is required to:
- Enable DMA address translation for devices that cannot directly access
  the full physical memory space.
- Provide isolation and memory protection by restricting device access
  to specific regions of memory, improving system security.
- Support virtualization use cases by enabling safe and isolated device
  passthrough to guest VMs.
- Align with ARM platform architecture requirements for IOMMU support.

By describing the SMMU in the device tree, the Linux IOMMU framework
can probe and initialize it during boot. Devices in the system can then
bind to the SMMU via the `iommus` property, enabling memory translation
and protection features as expected.

The following devices are updated to reference the SMMU:
- NAND controller
- DMA controller
- SPI controller

This change is a necessary step toward full enablement high-speed
peripherals on Agilex5.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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