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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-02 10:46:25 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 13:30:19 +0300 |
| commit | e11f804afc12e1c622f0a6f966fafd05b7022f8a (patch) | |
| tree | 6f92a6c5cb53e2aa408007a90bd919f856f886d1 /scripts/gdb/linux/utils.py | |
| parent | f201eb84450f98decb1834e73409bb2271441dd7 (diff) | |
| download | linux-e11f804afc12e1c622f0a6f966fafd05b7022f8a.tar.xz | |
clk: renesas: r9a07g043: Add GbEthernet clock/reset
Add ETH{0,1} clock/reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions