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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-01-06 23:28:53 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 13:07:05 +0300 |
| commit | 989d673ff7c461b2abd472227fdb7df69860d23f (patch) | |
| tree | 55f2b5b52298184108c02f6b78c2b9d8c540cac6 /scripts/gdb/linux/utils.py | |
| parent | 5599c7c4b4df440aa4a470a5b72669081413981f (diff) | |
| download | linux-989d673ff7c461b2abd472227fdb7df69860d23f.tar.xz | |
clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
Add clock and reset entries for the DRP-AI block, which is available only
on the Renesas RZ/V2L SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250106202853.262787-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions