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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-01-03 19:38:00 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 13:05:34 +0300 |
| commit | 5599c7c4b4df440aa4a470a5b72669081413981f (patch) | |
| tree | 8c3d3d7d27e00599ba34f2481c5145fbf7c37346 /scripts/gdb/linux/utils.py | |
| parent | f6f73b891bf6beff069fcacc7b4a796e1009bf26 (diff) | |
| download | linux-5599c7c4b4df440aa4a470a5b72669081413981f.tar.xz | |
clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP
Add clocks, resets and power domains for the TSU IP available on the
Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250103163805.1775705-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions