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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-02-02 14:16:14 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-02-18 18:27:31 +0300 |
| commit | 61b3b2da10dba0ac1633c699c9d305c702b43720 (patch) | |
| tree | cb485d9c0c279c7c6086095c9d0d6853684c8b5a /scripts/gdb/linux/utils.py | |
| parent | f470b218b0bb7c9bae8aa2b4859d9a6bf97d98d1 (diff) | |
| download | linux-61b3b2da10dba0ac1633c699c9d305c702b43720.tar.xz | |
drm/i915: Make the pipe/output CSC register writes lockless
The pipe/output CSC register writes don't need to be locked
since all the registers are suitably isolated to their own
cachelines. So eliminate the locks to reduce the overhead
during the vblank evade critical section.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220202111616.1579-2-ville.syrjala@linux.intel.com
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions