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authorVille Syrjälä <ville.syrjala@linux.intel.com>2022-02-02 14:16:13 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2022-02-18 18:27:31 +0300
commitf470b218b0bb7c9bae8aa2b4859d9a6bf97d98d1 (patch)
tree5a50d3cc42e2558e03d2ec1e62649d3d84965260 /scripts/gdb/linux/utils.py
parent79af2404e537e0f74798faa0a26bbd374ece27f8 (diff)
downloadlinux-f470b218b0bb7c9bae8aa2b4859d9a6bf97d98d1.tar.xz
drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical section
We don't want any RMWs in the part of the commit that happens under vblank evasion. Eventually we want to use the DSB to handle that and it can't read registers at all. Also reads are just slowing us down needlessly. Let's move the whole PIPE_CHICKEN stuff out from the critical section since we don't have anything there that needs to be syncrhonized with other plane/pipe registers. If we ever need to add such things then we have to move it back, but without doing any reads. TODO: should look into eliminating the RMW anyway... Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220202111616.1579-1-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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