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| author | Stephen Boyd <sboyd@kernel.org> | 2026-01-21 21:56:09 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2026-01-21 21:56:09 +0300 |
| commit | 83436f2bf4e0cd84932a8fe5bce33af3b9e58120 (patch) | |
| tree | d4ebc6860057d6be930639120c512faa438ef9dc /include | |
| parent | a46a9cd19beefdca7f4f55674a380b1a91f9fa77 (diff) | |
| parent | 4fef3fd633be4a1a18c490a63f4131284f6ee0f4 (diff) | |
| download | linux-83436f2bf4e0cd84932a8fe5bce33af3b9e58120.tar.xz | |
Merge tag 'renesas-clk-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Fix s2ram on Renesas RZ/T2H and RZ/N2H
- Add CAN-FD clocks and resets on Renesas RZ/T2H, RZ/N2H,
RZ/V2H, and RZ/V2N
* tag 'renesas-clk-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: Add missing log message terminators
clk: renesas: rzg2l: Remove DSI clock rate restrictions
clk: renesas: rzv2h: Deassert reset on assert timeout
clk: renesas: rzg2l: Deassert reset on assert timeout
clk: renesas: cpg-mssr: Unlock before reset verification
clk: renesas: r9a09g056: Add entries for CANFD
clk: renesas: r9a09g057: Add entries for CANFD
clk: renesas: r9a09g077: Add CANFD clocks
clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacks
dt-bindings: clock: renesas,r9a09g077/87: Add PCLKCAN ID
clk: renesas: cpg-mssr: Simplify pointer math in cpg_rzt2h_mstp_read()
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 | ||||
| -rw-r--r-- | include/linux/clk/renesas.h | 11 |
3 files changed, 13 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 9eaedca6a616..c4863e444458 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -33,5 +33,6 @@ #define R9A09G077_ETCLKE 21 #define R9A09G077_XSPI_CLK0 22 #define R9A09G077_XSPI_CLK1 23 +#define R9A09G077_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 606468ac49a4..0d53f1e65077 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -33,5 +33,6 @@ #define R9A09G087_ETCLKE 21 #define R9A09G087_XSPI_CLK0 22 #define R9A09G087_XSPI_CLK1 23 +#define R9A09G087_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h index 69d8159deee3..c360df9fa735 100644 --- a/include/linux/clk/renesas.h +++ b/include/linux/clk/renesas.h @@ -35,6 +35,17 @@ void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev); #define cpg_mssr_detach_dev NULL #endif +enum { + PLL5_TARGET_DPI, + PLL5_TARGET_DSI +}; + +#ifdef CONFIG_CLK_RZG2L +void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target); +#else +static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { } +#endif + /** * struct rzv2h_pll_limits - PLL parameter constraints * |