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| author | Stephen Boyd <sboyd@kernel.org> | 2026-01-16 05:31:49 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2026-01-16 05:31:49 +0300 |
| commit | a46a9cd19beefdca7f4f55674a380b1a91f9fa77 (patch) | |
| tree | 41c1257cfe9a02b18eb55ec0a96f3f3142be8c6c /include | |
| parent | 8f0b4cce4481fb22653697cced8d0d04027cb1e8 (diff) | |
| parent | ebb3acf4d7c95b52265084168b59a565bf972883 (diff) | |
| download | linux-a46a9cd19beefdca7f4f55674a380b1a91f9fa77.tar.xz | |
Merge tag 'renesas-clk-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/T21H and RZ/N2H
- Add DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks
and resets on Renesas RZ/V2N
- Add more serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
* tag 'renesas-clk-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a09g056: Add clock and reset entries for TSU
clk: renesas: r9a09g057: Add entries for RSCIs
clk: renesas: r9a09g056: Add entries for RSCIs
clk: renesas: r9a09g056: Add entries for the RSPIs
clk: renesas: r9a09g056: Add entries for ICU
clk: renesas: r9a09g056: Add entries for the DMACs
clk: renesas: r9a09g077: Propagate rate changes through mux parents
clk: renesas: r9a09g077: Add xSPI core and module clocks
clk: renesas: rzg2l: Select correct div round macro
clk: renesas: rzg2l: Fix intin variable size
dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 2a805e06487b..9eaedca6a616 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G077_ETCLKC 19 #define R9A09G077_ETCLKD 20 #define R9A09G077_ETCLKE 21 +#define R9A09G077_XSPI_CLK0 22 +#define R9A09G077_XSPI_CLK1 23 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 09da0ad33be6..606468ac49a4 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G087_ETCLKC 19 #define R9A09G087_ETCLKD 20 #define R9A09G087_ETCLKE 21 +#define R9A09G087_XSPI_CLK0 22 +#define R9A09G087_XSPI_CLK1 23 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ |