diff options
| author | Bjorn Andersson <andersson@kernel.org> | 2026-03-11 23:44:31 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-03-11 23:44:31 +0300 |
| commit | 8081dbb031ef733d200f9a6b2f34dae9543caac0 (patch) | |
| tree | a436dd7233ca8968deefb285e3a370e2a1068243 /include | |
| parent | c69a586344758f0d9cf0526d2a4b14fb56941b10 (diff) | |
| parent | 0221b14be8aae98d687efab066133a114bea02d8 (diff) | |
| download | linux-8081dbb031ef733d200f9a6b2f34dae9543caac0.tar.xz | |
Merge branch '20260303034847.13870-2-val@packett.cool' into clk-for-7.1
Merge the definition of MDSS resets for SM6115 and SM6125 to allow them
to be made available in the DeviceTree branch.
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/qcom,dispcc-sm6125.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,sm6115-dispcc.h | 7 |
2 files changed, 10 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6125.h b/include/dt-bindings/clock/qcom,dispcc-sm6125.h index 4ff974f4fcc3..f58b85d2c814 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sm6125.h +++ b/include/dt-bindings/clock/qcom,dispcc-sm6125.h @@ -6,6 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_MDSS_AHB_CLK 1 #define DISP_CC_MDSS_AHB_CLK_SRC 2 @@ -35,7 +36,10 @@ #define DISP_CC_MDSS_VSYNC_CLK_SRC 26 #define DISP_CC_XO_CLK 27 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 #endif diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h index d1a6c45b5029..ab8d312ade37 100644 --- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h +++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H -/* DISP_CC clocks */ +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_PLL0_OUT_MAIN 1 #define DISP_CC_MDSS_AHB_CLK 2 @@ -30,7 +30,10 @@ #define DISP_CC_SLEEP_CLK 20 #define DISP_CC_SLEEP_CLK_SRC 21 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 #endif |