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| author | Nick Hawkins <nick.hawkins@hpe.com> | 2026-03-16 18:01:14 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2026-03-23 17:54:29 +0300 |
| commit | e65a413a2d4505012fdba2974dca613ac1779d84 (patch) | |
| tree | 9de8925369ddd3a407f78aa2d7d3a42c0173e360 | |
| parent | 3f1628baa51e78c3f0cba6383f00405e5a8c175e (diff) | |
| download | linux-e65a413a2d4505012fdba2974dca613ac1779d84.tar.xz | |
dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible
Add the 'hpe,gsc-dwcmshc' compatible string for the HPE GSC (ARM64
Cortex-A53) BMC SoC eMMC controller.
The HPE GSC requires access to the MSHCCS register in the SoC system
register block to configure SCG sync disable for HS200 RX delay-line
phase selection. The required 'hpe,gxp-sysreg' property takes a
phandle to the existing 'hpe,gxp-sysreg' syscon and the MSHCCS
register offset within that block.
The HPE GSC eMMC interface only exposes a single 'core' clock (no
bus clock), so clocks/clock-names are constrained to a single item.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index 5cebe5eb1efb..539fa3b54b5b 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -23,6 +23,7 @@ properties: - const: sophgo,sg2044-dwcmshc - const: sophgo,sg2042-dwcmshc - enum: + - hpe,gsc-dwcmshc - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci @@ -79,6 +80,17 @@ properties: description: Specifies the drive impedance in Ohm. enum: [33, 40, 50, 66, 100] + hpe,gxp-sysreg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to HPE GXP SoC system register block (syscon) + - description: offset of the MSHCCS register within the syscon block + description: + Phandle to the HPE GXP SoC system register block (syscon) and + offset of the MSHCCS register used to configure clock + synchronisation for HS200 tuning. + required: - compatible - reg @@ -93,6 +105,26 @@ allOf: properties: compatible: contains: + const: hpe,gsc-dwcmshc + + then: + properties: + clocks: + items: + - description: core clock + clock-names: + items: + - const: core + required: + - hpe,gxp-sysreg + else: + properties: + hpe,gxp-sysreg: false + + - if: + properties: + compatible: + contains: const: sophgo,sg2042-dwcmshc then: |