diff options
| author | Alexander Stein <alexander.stein@ew.tq-group.com> | 2026-03-13 10:07:32 +0300 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@oss.qualcomm.com> | 2026-03-19 17:14:39 +0300 |
| commit | a15840f7c3d7f7cac208df9c3a0dc651ebbfa80a (patch) | |
| tree | 23c48b6063a0c92aa287a7364586cb964e2145c3 | |
| parent | e2f8311a6aa5f809bb62de61888292e58087fd21 (diff) | |
| download | linux-a15840f7c3d7f7cac208df9c3a0dc651ebbfa80a.tar.xz | |
clk: imx: fracn-gppll: Add 477.4MHz support
Add the 477.4MHz frequency support that can be used for display with
pixelclk of 68.2 MHz. The divider of 7 is important for LVDS output on
imx93. It is also usable for parallel output.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://patch.msgid.link/20260313070740.585043-3-alexander.stein@ew.tq-group.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
| -rw-r--r-- | drivers/clk/imx/clk-fracn-gppll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index fe6ee77ba148..4048c16c0578 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -85,6 +85,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8), PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), + PLL_FRACN_GP(477400000U, 119, 35, 100, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), |