diff options
| author | Alexander Stein <alexander.stein@ew.tq-group.com> | 2026-03-13 10:07:31 +0300 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@oss.qualcomm.com> | 2026-03-19 17:12:13 +0300 |
| commit | e2f8311a6aa5f809bb62de61888292e58087fd21 (patch) | |
| tree | d0b4c3c61b4f47b8b5a248f0fcee2faa6f9cf1e1 | |
| parent | fca8688a6798f6fee6b86ce0bc39d1cd0b1c8b8a (diff) | |
| download | linux-e2f8311a6aa5f809bb62de61888292e58087fd21.tar.xz | |
clk: imx: fracn-gppll: Add 333.333333 MHz support
Some parallel panels have a pixelclk of 33.30 MHz. Add support for
333.333333 MHz so a by 10 divider can be used to derive the exact pixelclk.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20260313070740.585043-2-alexander.stein@ew.tq-group.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
| -rw-r--r-- | drivers/clk/imx/clk-fracn-gppll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 89ed7749bf47..fe6ee77ba148 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -88,6 +88,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), + PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9), PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10), PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12), PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20), |