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| author | Martin Schiller <ms@dev.tdt.de> | 2025-11-24 10:48:45 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2025-12-17 15:31:08 +0300 |
| commit | a08340fd291671c54d379d285b2325490ce90ddd (patch) | |
| tree | 04801b59bfea3efbd114af2a70cd6b2f74e5331c | |
| parent | 63dbadcafc1f4d1da796a8e2c0aea1e561f79ece (diff) | |
| download | linux-a08340fd291671c54d379d285b2325490ce90ddd.tar.xz | |
perf/x86/intel: Add Airmont NP
The Intel / MaxLinear Airmont NP (aka Lightning Mountain) supports the
same architectual and non-architecural events as Airmont.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251124074846.9653-3-ms@dev.tdt.de
| -rw-r--r-- | arch/x86/events/intel/core.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 0553c1160f15..1840ca1918d1 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7410,6 +7410,7 @@ __init int intel_pmu_init(void) case INTEL_ATOM_SILVERMONT_D: case INTEL_ATOM_SILVERMONT_MID: case INTEL_ATOM_AIRMONT: + case INTEL_ATOM_AIRMONT_NP: case INTEL_ATOM_SILVERMONT_MID2: memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); |