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| author | Martin Schiller <ms@dev.tdt.de> | 2025-11-24 10:48:44 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2025-12-17 15:31:08 +0300 |
| commit | 63dbadcafc1f4d1da796a8e2c0aea1e561f79ece (patch) | |
| tree | 2c47e9ab8058bba793f25be5f30a5237676f3da2 | |
| parent | 3c48808408af11d6f173c65eee9bd5ca4c53667c (diff) | |
| download | linux-63dbadcafc1f4d1da796a8e2c0aea1e561f79ece.tar.xz | |
perf/x86/msr: Add Airmont NP
Like Airmont, the Airmont NP (aka Intel / MaxLinear Lightning Mountain)
supports SMI_COUNT MSR.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251124074846.9653-2-ms@dev.tdt.de
| -rw-r--r-- | arch/x86/events/msr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 7f5007a4752a..8052596b8503 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data) case INTEL_ATOM_SILVERMONT: case INTEL_ATOM_SILVERMONT_D: case INTEL_ATOM_AIRMONT: + case INTEL_ATOM_AIRMONT_NP: case INTEL_ATOM_GOLDMONT: case INTEL_ATOM_GOLDMONT_D: |