diff options
| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2026-04-28 00:57:26 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-05-05 21:28:40 +0300 |
| commit | 640c768d315b25f8e56844d1d71c8d0040dfd88b (patch) | |
| tree | 441e2e4cab3062f5821a963e8c5e544e23bd492a | |
| parent | bb85f4f5541de9abbe7e300e94d58ea888dd3b33 (diff) | |
| download | linux-640c768d315b25f8e56844d1d71c8d0040dfd88b.tar.xz | |
arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-cm5-base
The board exposes the GPIO4_B5 pin to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to
allow adjusting the bias when transitioning between TMDS and FRL modes.
While at it, rename the hdmi_frl_pin pinmux to hdmi0_tx_on_h, in line
with the naming commonly used in RK3588s-bassed board schematics.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-8-924df9db884a@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts index 06120b2db690..20da0c2b3d92 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts @@ -143,10 +143,11 @@ }; &hdmi0 { - pinctrl-names = "default"; + frl-enable-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda - &hdmi_frl_pin>; + &hdmi0_tx_on_h>; + pinctrl-names = "default"; status = "okay"; }; @@ -245,8 +246,8 @@ }; hdmi { - hdmi_frl_pin: hdmi-frl-pin { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + hdmi0_tx_on_h: hdmi0-tx-on-h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; |