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authorRichard Zhu <hongxing.zhu@nxp.com>2025-10-15 06:04:24 +0300
committerShawn Guo <shawnguo@kernel.org>2025-11-12 04:51:29 +0300
commit1a79e70e9d101a52810c87acfb0ea35d73707b3e (patch)
treee4954c74061f4f61b5fb2848c71c483a3df940fb
parent44f9bcc943f53e25f63becbb471f0909fe77b603 (diff)
downloadlinux-1a79e70e9d101a52810c87acfb0ea35d73707b3e.tar.xz
arm64: dts: imx8qxp-mek: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8qxp-mek matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-mek.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index f19350536bc9..7c773782393d 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -640,6 +640,7 @@
pinctrl-names = "default";
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
+ supports-clkreq;
status = "okay";
};