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| author | Richard Zhu <hongxing.zhu@nxp.com> | 2025-12-11 09:48:19 +0300 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-12-23 15:33:03 +0300 |
| commit | 1352f58d7c8dfb6ba0fbd2041bfc8b4b3966ec67 (patch) | |
| tree | c6d492b5c33f1736912dcf8a4d9d8c28099027ae | |
| parent | 418970983059aa06302ddd5ca76d441973b537c1 (diff) | |
| download | linux-1352f58d7c8dfb6ba0fbd2041bfc8b4b3966ec67.tar.xz | |
dt-bindings: PCI: pci-imx6: Add external reference clock input
i.MX95 PCIes have two reference clock inputs: one from internal PLL.
It's wired inside chip and present as "ref" clock. It's not an optional
clock. The other from off chip crystal oscillator. The "extref" clock
refers to a reference clock from an external crystal oscillator through
the CLKIN_N/P pair PADs. It is an optional clock, relied on the board
design.
Add additional optional external reference clock input for i.MX95 PCIes.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251211064821.2707001-3-hongxing.zhu@nxp.com
| -rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index ca5f2970f217..12a01f7a5744 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -44,7 +44,7 @@ properties: clock-names: minItems: 3 - maxItems: 5 + maxItems: 6 interrupts: minItems: 1 @@ -212,14 +212,17 @@ allOf: then: properties: clocks: - maxItems: 5 + minItems: 5 + maxItems: 6 clock-names: + minItems: 5 items: - const: pcie - const: pcie_bus - const: pcie_phy - const: pcie_aux - const: ref + - const: extref # Optional unevaluatedProperties: false |