| Age | Commit message (Collapse) | Author | Files | Lines |
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Replace manual alignment checks with IS_ALIGNED() and
ADDRESS_IS_ALIGNED().
Convert the following bitmask and modulo forms:
- ((E & ((PowOf2Expr) - ONE)) == ZERO)
- ((E & ((PowOf2Expr) - ONE)) != ZERO)
- ((E % (PowOf2Expr)) == ZERO)
- ((E % (PowOf2Expr)) != ZERO)
to the corresponding helper macro forms:
+ IS_ALIGNED (E, PowOf2Expr)
+ !IS_ALIGNED (E, PowOf2Expr)
PowOf2Expr is limited to known power-of-two expressions, including
SIZE_* and BASE_* macros, EFI_PAGE_SIZE, CPU_STACK_ALIGNMENT,
RUNTIME_PAGE_ALLOCATION_GRANULARITY, sizeof() of UEFI integer types
(e.g. BOOLEAN, CHAR16, UINT32, UINTN) and pointer types, and 1 << E1
expressions.
Address checks that cast the checked value to UINTN are written with
ADDRESS_IS_ALIGNED().
The change was generated with the Coccinelle semantic patch below.
```smpl
@power_of_2_expr@
expression PowOf2Expr;
expression E1;
typedef BOOLEAN, CHAR8, CHAR16, INT8, UINT8, INT16, UINT16, INT32, UINT32, INT64, UINT64, INTN, UINTN;
type ScalarType = { BOOLEAN, CHAR8, CHAR16, INT8, UINT8, INT16, UINT16, INT32, UINT32, INT64, UINT64, INTN, UINTN };
type AnyType;
type PointerType = AnyType *;
idexpression ScalarType ScalarValue;
idexpression PointerType PointerValue;
constant SizeBase =~ "^(SIZE|BASE)_(1|2|4|8|16|32|64|128|256|512)[KMGTPE]B$";
constant NamedPowerOf2 =~ "^(EFI_PAGE_SIZE|CPU_STACK_ALIGNMENT|RUNTIME_PAGE_ALLOCATION_GRANULARITY)$";
constant ONE = {1, 1U, 1u};
@@
(
(
SizeBase
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NamedPowerOf2
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ONE << E1
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sizeof (ScalarType)
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sizeof (PointerType)
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sizeof (ScalarValue)
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sizeof (PointerValue)
)
&
PowOf2Expr
)
@aligned depends on power_of_2_expr disable is_zero,isnt_zero@
expression E;
expression power_of_2_expr.PowOf2Expr;
constant ONE = {1, 1U, 1u};
constant ZERO = {0, 0U, 0u};
@@
(
((E & (E - ONE)) == ZERO)
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- ((E & ((PowOf2Expr) - ONE)) == ZERO)
+ IS_ALIGNED (E, PowOf2Expr)
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((E & (E - ONE)) != ZERO)
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- ((E & ((PowOf2Expr) - ONE)) != ZERO)
+ !IS_ALIGNED (E, PowOf2Expr)
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- ((E % (PowOf2Expr)) == ZERO)
+ IS_ALIGNED (E, PowOf2Expr)
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- ((E % (PowOf2Expr)) != ZERO)
+ !IS_ALIGNED (E, PowOf2Expr)
)
@address_is_aligned@
typedef UINTN;
expression *Address;
expression Alignment;
@@
- IS_ALIGNED ((UINTN) Address, Alignment)
+ ADDRESS_IS_ALIGNED (Address, Alignment)
@normalize_aligned disable paren expression@
expression E, SZ;
@@
(
- (IS_ALIGNED (E, SZ))
+ IS_ALIGNED (E, SZ)
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- (!IS_ALIGNED (E, SZ))
+ !IS_ALIGNED (E, SZ)
)
@normalize_macro_args disable paren expression@
expression E, SZ;
@@
(
- IS_ALIGNED ((E), SZ)
+ IS_ALIGNED (E, SZ)
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- IS_ALIGNED (E, (SZ))
+ IS_ALIGNED (E, SZ)
)
```
Signed-off-by: Mingjie Shen <shen497@purdue.edu>
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As of now, the field-validator implemented by FNPTR_FIELD_VALIDATOR
function pointer takes two parameters, the pointer to the field and a
context pointer. For cases where the validator has to have access to the
length of the field, there is no clean way to currently do it. In order
to resolve this, this commit updates the field-validator's prototype to
take the length of the field as an additional parameter.
This enhancement allows field validators to perform more comprehensive
validation, especially when the length of the field is critical to the
validation logic. This change should improve the overall robustness and
flexibility of AcpiView.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Cc: James Morse <james.Morse@arm.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Bugzilla: 3458 - Add support IORT Rev E.d specification updates
(https://bugzilla.tianocore.org/show_bug.cgi?id=3458)
The IO Remapping Table, Platform Design Document, Revision E.d,
Feb 2022 (https://developer.arm.com/documentation/den0049/)
introduces the following updates, collectively including the
updates and errata fixes to Rev E, Rev E.a, Rev E.b, Rev E.c:
- increments the IORT table revision to 5.
- updates the node definition to add an 'Identifier' field.
- adds definition of node type 6 - Reserved Memory Range node.
- adds definition for Memory Range Descriptors.
- adds flag to indicate PRI support for root complexes.
- adds flag to indicate if the root complex supports forwarding
of PASID information on translated transactions to the SMMU.
- adds flag to indicate if the root complex supports PASID.
- adds flags to define access privilege and attributes for the
memory ranges.
Therefore, update the IORT parser to:
- parse the Identifier field.
- parse Reserved Memory Range node.
- parse Memory Range Descriptors.
- add validations to check that the physical range base
and size of the Memory Range Descriptor is 64KB aligned.
- add validation to check that the IORT Table Revision is
not 4 as IORT Rev E.c is deprecated.
- add validation to check that the IORT RMR node revision
is not 2 as it breaks backward compatibility and was
deprecated as part of IORT Rev E.c.
- skip parsing of IORT Rev E, Rev E.a, Rev E.b, Rev E.c as
some fields were deprecated in these revisions.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
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Some field names in the IORT table parser were longer than the
OUTPUT_FIELD_COLUMN_WIDTH plus indentation, resulting in loss of
the output print alignment. Therefore, abbreviate the field names.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the ShellPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
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A new file and header (AcpiViewConfig.[ch]) is created
that houses the user configuration. This declutters the
core code and improves modularity of the design.
The module level symbols for verbosity, table selection, and
highlighting are refactored into the new file.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Tomas Pilar <tomas.pilar@arm.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2534
Extend validation of ACPI structure lengths which are read from the
ACPI table being parsed. Additionally check if the structure 'Length'
field value is positive. If not, stop parsing the faulting table.
Some ACPI tables define internal structures of variable size. The
'Length' field inside the substructure is used to update a pointer used
for table traversal. If the byte-length of the structure is equal to 0,
acpiview can enter an infinite loop. This condition can occur if, for
example, the zero-allocated ACPI table buffer is not fully populated.
This is typically a bug on the ACPI table writer side.
In short, this method helps acpiview recover gracefully from a
zero-valued ACPI structure length.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Check if global (in the scope of the IORT parser) pointers have been
successfully updated before they are used for further table parsing.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
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Updated IORT parser to conform to the IO Remapping
Table, Platform Design Document, Revision D, March 2018.
The following structure parsers have been updated:
1. SMMUv3 - added proximity domain and device Id
mapping index.
2. RootComplex - added memory address size limit.
2. PMCG - added page 1 support.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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In IortParser.c ,the variable Index is set but not used in
function DumpIortNodeNamedComponent. This will cause build failure
when building ShellPkg with GCC.
Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
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Modify the IORT table parsing logic to prevent reading past the buffer
lengths provided.
Change DumpIortNodeIdMappings() function's signature and implementation
to simplify buffer overrun prevention. Update all calls to this
function accordingly.
Modify the parser for each type of IORT node such that the offset from
the start of the node's buffer is tracked as the parsing function is
executed. Again, this change helps prevent buffer overruns.
Test that the IORT node buffer fits in the table buffer before the
node's buffer contents are dumped.
References:
- IO Remapping Table (Issue D), Platform Design Document, March 2018
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@inte.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Move Performance Monitoring Counter Group (PMCG) node ID mapping count
validation from the core IORT acpiview parser logic to a dedicated
function. Now, the pointer to the validation function is passed to the
IortNodePmcgParser[] ACPI_PARSER array.
This check does not affect the flow of IORT parsing and is limited to
a single table field in scope, therefore, it is better to keep it away
from the code responsible for traversing the table.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Remove redundant forward function declarations by repositioning
blocks of code. This way the code structure is consistent across
ACPI table parsers and the code becomes more concise.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Remove redundant whitespace characters at the beginning of the strings
describing IORT table field names.
When dumping ACPI table contents, the indentation level for printing
field names is controled using the 'Indent' argument to the 'ParseAcpi'
function. In the IORT acpiview parser, both 'Indent' and extra
whitespace characters are used for indentation, which results in
excess indentation.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Replace the enum defining valid node types in the IORT table with
macros from IoRemappingTable.h.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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https://bugzilla.tianocore.org/show_bug.cgi?id=1373
Replace BSD 2-Clause License with BSD+Patent License. This change is
based on the following emails:
https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html
https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html
RFCs with detailed process for the license change:
V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html
V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html
V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
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1. Separate variable definition and initialization.
2. Make the variable naming following Edk2 rule.
V2: Remove the updates of guard macros in header files.
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Evan Lloyd <evan.lloyd@arm.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
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Make the function comments follow EDK2 coding style.
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Evan Lloyd <evan.lloyd@arm.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
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This program is provided to allow examination of ACPI table contents
from the UEFI Shell. This can help with investigations, especially at
that stage where the tables are not enabling an OS to boot.
The program is not exhaustive, and only encapsulates detailed knowledge
of a limited number of table types.
Default behaviour is to display the content of all tables installed.
'Known' table types will be parsed and displayed with descriptions and
field values. Where appropriate a degree of consistency checking is
done and errors may be reported in the output.
Other table types will be displayed as an array of Hexadecimal bytes.
To facilitate debugging, the -s and -d options can be used to generate a
binary file image of a table that can be copied elsewhere for
investigation using tools such as those provided by acpica.org. This is
especially relevant for AML type tables like DSDT and SSDT.
The inspiration for this is the existing smbiosview Debug1 Shell
command.
Many tables are not explicitly handled, in part because no examples are
available for our testing.
The program is designed to be extended to new tables with minimal
effort, and contributions are invited.
Change-Id: Ifa23dc80ab8ab042c56e88424847e796a8122a7c
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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