| Age | Commit message (Collapse) | Author | Files | Lines |
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The ACPI 6.5 specification introduces the CCEL (CC Event Log) table
in section 5.2.34:
https://uefi.org/specs/ACPI/6.5/
05_ACPI_Software_Programming_Model.html#cc-event-log-acpi-table
Extend AcpiView with a parser to decode and display CCEL table
contents. This allows users to inspect CCEL tables from the UEFI
Shell.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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Move the reserved-field validators from MpamParser.c into AcpiParser.c
and expose them through AcpiParser.h so they can be reused by multiple
Acpiview parsers.
Update the AGDI, MPAM and WSMT parsers to use the common helpers for
byte-length and bit-length reserved fields.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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Replace manual alignment checks with IS_ALIGNED() and
ADDRESS_IS_ALIGNED().
Convert the following bitmask and modulo forms:
- ((E & ((PowOf2Expr) - ONE)) == ZERO)
- ((E & ((PowOf2Expr) - ONE)) != ZERO)
- ((E % (PowOf2Expr)) == ZERO)
- ((E % (PowOf2Expr)) != ZERO)
to the corresponding helper macro forms:
+ IS_ALIGNED (E, PowOf2Expr)
+ !IS_ALIGNED (E, PowOf2Expr)
PowOf2Expr is limited to known power-of-two expressions, including
SIZE_* and BASE_* macros, EFI_PAGE_SIZE, CPU_STACK_ALIGNMENT,
RUNTIME_PAGE_ALLOCATION_GRANULARITY, sizeof() of UEFI integer types
(e.g. BOOLEAN, CHAR16, UINT32, UINTN) and pointer types, and 1 << E1
expressions.
Address checks that cast the checked value to UINTN are written with
ADDRESS_IS_ALIGNED().
The change was generated with the Coccinelle semantic patch below.
```smpl
@power_of_2_expr@
expression PowOf2Expr;
expression E1;
typedef BOOLEAN, CHAR8, CHAR16, INT8, UINT8, INT16, UINT16, INT32, UINT32, INT64, UINT64, INTN, UINTN;
type ScalarType = { BOOLEAN, CHAR8, CHAR16, INT8, UINT8, INT16, UINT16, INT32, UINT32, INT64, UINT64, INTN, UINTN };
type AnyType;
type PointerType = AnyType *;
idexpression ScalarType ScalarValue;
idexpression PointerType PointerValue;
constant SizeBase =~ "^(SIZE|BASE)_(1|2|4|8|16|32|64|128|256|512)[KMGTPE]B$";
constant NamedPowerOf2 =~ "^(EFI_PAGE_SIZE|CPU_STACK_ALIGNMENT|RUNTIME_PAGE_ALLOCATION_GRANULARITY)$";
constant ONE = {1, 1U, 1u};
@@
(
(
SizeBase
|
NamedPowerOf2
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ONE << E1
|
sizeof (ScalarType)
|
sizeof (PointerType)
|
sizeof (ScalarValue)
|
sizeof (PointerValue)
)
&
PowOf2Expr
)
@aligned depends on power_of_2_expr disable is_zero,isnt_zero@
expression E;
expression power_of_2_expr.PowOf2Expr;
constant ONE = {1, 1U, 1u};
constant ZERO = {0, 0U, 0u};
@@
(
((E & (E - ONE)) == ZERO)
|
- ((E & ((PowOf2Expr) - ONE)) == ZERO)
+ IS_ALIGNED (E, PowOf2Expr)
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((E & (E - ONE)) != ZERO)
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- ((E & ((PowOf2Expr) - ONE)) != ZERO)
+ !IS_ALIGNED (E, PowOf2Expr)
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- ((E % (PowOf2Expr)) == ZERO)
+ IS_ALIGNED (E, PowOf2Expr)
|
- ((E % (PowOf2Expr)) != ZERO)
+ !IS_ALIGNED (E, PowOf2Expr)
)
@address_is_aligned@
typedef UINTN;
expression *Address;
expression Alignment;
@@
- IS_ALIGNED ((UINTN) Address, Alignment)
+ ADDRESS_IS_ALIGNED (Address, Alignment)
@normalize_aligned disable paren expression@
expression E, SZ;
@@
(
- (IS_ALIGNED (E, SZ))
+ IS_ALIGNED (E, SZ)
|
- (!IS_ALIGNED (E, SZ))
+ !IS_ALIGNED (E, SZ)
)
@normalize_macro_args disable paren expression@
expression E, SZ;
@@
(
- IS_ALIGNED ((E), SZ)
+ IS_ALIGNED (E, SZ)
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- IS_ALIGNED (E, (SZ))
+ IS_ALIGNED (E, SZ)
)
```
Signed-off-by: Mingjie Shen <shen497@purdue.edu>
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ACPI defines Injection Header Size as the length of the EINJ
injection header, not necessarily the absolute offset of the
instruction entries. Update parser validation to use the correct
entry offset calculation and accept the layout used by Linux and
existing firmware tables.
Signed-off-by: Simon Wang <simowang@nvidia.com>
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The "ACPI for Memory System Resource Partitioning and Monitoring" spec
(Arm DEN0065, [1]) in version 2.0 described the "MMIO size" field in the
"MPAM MSC node" subtable as being always 0 if the the "PCC" interface type
is used for that MSC. Version 3.0 of the spec changes that field to convey
the enablement status of that MSC: "If set to 1, this MSC is accessible
... If set to 0, this MSC is non-functional...."
Relax the strict check for this value being 0 in the acpiview validation
checks, to also allow the new value of "1".
[1] https://developer.arm.com/documentation/den0065/3-0/
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Remove post-parse write to mHestIA32HardwareBankCount.
Keep HEST parsing read-only.
*mHestIA32HardwareBankCount = 0, line in code corrupts the
ACPI HEST table data Hardware bank count to zero.
mHestIA32HardwareBankCount points into the parsed HEST table
data (input buffer). Writing through it modifies ACPI table
contents during parsing, which should be read-only behavior.
Signed-off-by: Gaurav Pandya <Gaurav.Pandya@amd.com>
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Replace traditional `#ifndef`/`#define`/`#endif` include guards with
`#pragma` once.
`#pragma once` is a widely supported preprocessor directive that
prevents header files from being included multiple times. It is
supported by all toolchains used to build edk2: GCC, Clang/LLVM, and
MSVC.
Compared to macro-based include guards, `#pragma once`:
- Eliminates the risk of macro name collisions or copy/paste errors
where two headers inadvertently use the same guard macro.
- Eliminate inconsistency in the way include guard macros are named
(e.g., some files use `__FILE_H__`, others use `FILE_H_`, etc.).
- Reduces boilerplate (three lines replaced by one).
- Avoids polluting the macro namespace with guard symbols.
- Can improve build times as the preprocessor can skip re-opening the
file entirely, rather than re-reading it to find the matching
`#endif` ("multiple-include optimization").
- Note that some compilers may already optimize traditional include
guards, by recognzining the idiomatic pattern.
This change is made acknowledging that overall portability of the
code will technically be reduced, as `#pragma once` is not part of the
C/C++ standards.
However, this is considered acceptable given:
1. edk2 already defines a subset of supported compilers in
BaseTools/Conf/tools_def.template, all of which have supported
`#pragma once` for over two decades.
2. There have been concerns raised to the project about inconsistent
include guard naming and potential macro collisions.
Approximate compiler support dates:
- MSVC: Supported since Visual C++ 4.2 (1996)
- GCC: Supported since 3.4 (2004)
(http://gnu.ist.utl.pt/software/gcc/gcc-3.4/changes.html)
- Clang (LLVM based): Since initial release in 2007
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
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Add a new parser for the Firmware Performance Data Table (FPDT),
as per the ACPI6.5 specification.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Clang complains about unused variables:
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Rimt/RimtParser.c:21:60: error: variable 'mRimtNodeHeader' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
21 | STATIC EFI_ACPI_6_6_RIMT_NODE_HEADER_STRUCTURE mRimtNodeHeader;
| ^~~~~~~~~~~~~~~
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Rimt/RimtParser.c:25:60: error: variable 'mRimtIdMappingNode' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
25 | STATIC EFI_ACPI_6_6_RIMT_ID_MAPPING_STRUCTURE mRimtIdMappingNode;
| ^~~~~~~~~~~~~~~~~~
28 | STATIC EFI_ACPI_6_6_RIMT_PCIE_ROOT_COMPLEX_NODE_STRUCTURE mRimtPcieRootComplexNode;
| ^~~~~~~~~~~~~~~~~~~~~~~~
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Rimt/RimtParser.c:29:60: error: variable 'mRimtIommuNode' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
29 | STATIC EFI_ACPI_6_6_RIMT_IOMMU_NODE_STRUCTURE mRimtIommuNode;
| ^~~~~~~~~~~~~~
4 errors generated.
This is because these variables are only used to take the size of their
fields using the sizeof() operator, which does not support type names
directly.
So create a helper macro SIZE_OF_T () that provides the functionality we
need, and drop the unused variables.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
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Implementation tested on Qemu-10.1 virt machine with IOMMU enabled.
Signed-off-by: Krzysztof Drobiński <krzysztof@plasteli.net>
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The AGDI table is a Global Diagnostic Dump and Reset Interface table
defined by Arm. Add support for dumping the table contents in the
acpiview command.
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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edk2 is dropping support for the ARM32 architecture. This commit
removes support from ShellPkg.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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Revision 4 adds fields for UART clock frequency, precise baud rate and ACPI
object namespace string. The revision 4 specification is at
https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/serial-port-console-redirection-table
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
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Add support for the ARM FF-A Start Method Specific Parameters to the TPM2
parser
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
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Add a new parser for the TPM2 Table as specified in the TCG ACPI
Specification v1.4
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
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This checks the number of PCC descriptor entries provided match the
count set in the table, and if they don't indicate a warning.
Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
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Add a new parser for the RASF Table as specified in ACPI6.5
Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
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Remove unused define from RAS2 parser
Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
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Add a new parser for the RAS2 Table as specified in ACPI6.5
Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
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ACPI 6.5 adds mode flags that could do with
more human-readable display in Acpiview. This
adds support for displaying those flags.
Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
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Add a parser for the MPAM (Memory system resource partitioning and
monitoring) ACPI table. This parser would parse all MPAM related
structures embedded as part of the ACPI table. Necessary validations are
also performed where and when required.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Cc: James Morse <james.Morse@arm.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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As of now, the print-formatter implemented by the FNPTR_PRINT_FORMATTER
function pointer takes two parameters, the format string and the pointer
to the field. For cases where the print-formatter has to have access to
the length of the field, there is no clean way to currently do it. In
order to resolve this, update the print-formatter's prototype to take
the length of the field as a third parameter. This change should improve
the overall robustness and flexibility of AcpiView.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Cc: James Morse <james.Morse@arm.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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As of now, the field-validator implemented by FNPTR_FIELD_VALIDATOR
function pointer takes two parameters, the pointer to the field and a
context pointer. For cases where the validator has to have access to the
length of the field, there is no clean way to currently do it. In order
to resolve this, this commit updates the field-validator's prototype to
take the length of the field as an additional parameter.
This enhancement allows field validators to perform more comprehensive
validation, especially when the length of the field is critical to the
validation logic. This change should improve the overall robustness and
flexibility of AcpiView.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Cc: James Morse <james.Morse@arm.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Parse CORE_PIC, LIO_PIC, HT_PIC, EIO_PIC, MSI_PIC, BIO_PIC and LPC_PIC
tables in ACPI SPEC 6.5.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4306
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Chao Li <lichao@loongson.cn>
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Jinwei Wang <wangjinwei@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>
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Add a new pareser for the Hardware Error Source Table (HEST).
The HEST table is used to describe a system's hardware error sources
to OSPM.
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
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Add a new parser for the Error Injection Table (EINJ).
The EINJ table provides machinism through which OSPM
can inject hardware errors to the platform without requiring platform
specific OSPM software.
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
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Adds WSMT parse to the UefiShellAcpiViewCommandLib library.
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Adds HPET parse to the UefiShellAcpiViewCommandLib library.
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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ACPI 6.5 introduces a new filed to the MADT GICC
structure to specify the TRBE interrupt. The TRBE
interrupt is a Processor Private interrupt (PPI)
and is used to specify a platform-specific
interrupt to signal TRBE events.
Therefore, update the MADT GICC structure parser
to parse the new TRBE interrupt field. Also, add
validations to check that the TRBE interrupt is
within the PPI interrupt range.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
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Add a new parser for the Error Record Serialization Table.
The ERST table describes how an OS can save and retrieve
hardware error information to and from a persistent store.
Signed-off-by: Jeshua Smith <jeshuas@nvidia.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Add a new parser for the Arm Performance Monitoring Unit Table.
The APMT table describes the properties of PMU support
implemented by components in an Arm-based system.
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The ACPI specification updated some terms in accordance with:
s1.1.1 Principle of Inclusive Terminology
Update the PCCT parser accordincly with these new terms.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Parse Type 0 or Local APIC structure.
Also parse the Local APIC Flags as bitfields.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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This reverts commit d5fd86f256b9ab5b4e3aff70d3c177c18faea892 for tag202208.
This feature will be merged after stable tag 202208 is created.
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
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Bugzilla: 3995 (https://bugzilla.tianocore.org/show_bug.cgi?id=3995)
ACPI 6.4 spec states that if the revision field in the DSDT header is less
than 2, then all integers are restricted in width to 32 bits, including in
SSDTs.
Arm Base boot requirements state that platforms must conform to ACPI 6.3
or later, and that legacy tables are not supported.
Adds a check for this field and raise warning if revision is less
than 2 on arm.
Signed-off-by: Edward Pickup <edward.pickup@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Parse Type 0 or Local APIC structure.
Also parse the Local APIC Flags as bitfields.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Bugzilla: 3458 - Add support IORT Rev E.d specification updates
(https://bugzilla.tianocore.org/show_bug.cgi?id=3458)
The IO Remapping Table, Platform Design Document, Revision E.d,
Feb 2022 (https://developer.arm.com/documentation/den0049/)
introduces the following updates, collectively including the
updates and errata fixes to Rev E, Rev E.a, Rev E.b, Rev E.c:
- increments the IORT table revision to 5.
- updates the node definition to add an 'Identifier' field.
- adds definition of node type 6 - Reserved Memory Range node.
- adds definition for Memory Range Descriptors.
- adds flag to indicate PRI support for root complexes.
- adds flag to indicate if the root complex supports forwarding
of PASID information on translated transactions to the SMMU.
- adds flag to indicate if the root complex supports PASID.
- adds flags to define access privilege and attributes for the
memory ranges.
Therefore, update the IORT parser to:
- parse the Identifier field.
- parse Reserved Memory Range node.
- parse Memory Range Descriptors.
- add validations to check that the physical range base
and size of the Memory Range Descriptor is 64KB aligned.
- add validation to check that the IORT Table Revision is
not 4 as IORT Rev E.c is deprecated.
- add validation to check that the IORT RMR node revision
is not 2 as it breaks backward compatibility and was
deprecated as part of IORT Rev E.c.
- skip parsing of IORT Rev E, Rev E.a, Rev E.b, Rev E.c as
some fields were deprecated in these revisions.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
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Some field names in the IORT table parser were longer than the
OUTPUT_FIELD_COLUMN_WIDTH plus indentation, resulting in loss of
the output print alignment. Therefore, abbreviate the field names.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3839
Adds PrintFormatter function to the FADT flags field.
Prints indivisual flag name along with flag value.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Bugzilla: 3770 (https://bugzilla.tianocore.org/show_bug.cgi?id=3770)
The PPTT parser in AcpiView incorrectly dereferences a pointer to
FlagName when trying to log an error with the PPTT cache flags, which
can lead to random crashes and other errors.
Also fix some spacing in the error message to ensure the message is
printed cleanly.
Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)
Update the Acpiview PPTT parser with the Cache ID field and relevant
validations as defined in tables 5.140 and 5.141 of the ACPI 6.4
specification.
Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)
Update the Acpiview PPTT parser to use Acpi64.h. As part of the changes,
remove support for parsing PPTT type 2 ID structure.
Mantis ID for removing PPTT type 2 structure:
2072 (https://mantis.uefi.org/mantis/view.php?id=2072)
Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the ShellPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
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Parse and print the below interrupt structures
- I/O APIC Structure
- Interrupt Source Override Structure
- Processor Local x2APIC Structure
- Local x2APIC NMI Structure
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Add parser support for the new "MinTransferSize" field of the System
Locality, Latency and Bandwidth structure, introduced by the ACPI
specification version 6.4.
Also update the HMAT parser to use the newer ACPI version 6.4
definitions.
Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhcihao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Bugzilla: 3563 (https://bugzilla.tianocore.org/show_bug.cgi?id=3563)
Update the Acpiview PCCT parser with the HW Registers based
Communications Subspace Structure (Type 5) as defined in Section 14.1.7
of the ACPI 6.4 specification.
Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar <sami.mujawar@arm.com>
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Bugzilla: 3563 (https://bugzilla.tianocore.org/show_bug.cgi?id=3563)
Update the Acpiview PCCT parser to use Acpi64.h.
Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar <sami.mujawar@arm.com>
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Bugzilla: 3565 (https://bugzilla.tianocore.org/show_bug.cgi?id=3565)
Update the Acpiview GTDT parser to use Acpi64.h and as such rename all
occurences of "SBSA Generic Watchdog" to "Arm Generic Watchdog".
Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Bugzilla: 3045 (https://bugzilla.tianocore.org/show_bug.cgi?id=3045)
Add a new parser for the Heterogeneous Memory Attribute Table. The
parser also validates some fields for this table.
The HMAT table is used to describe the memory attributes such as memory
side cache attributes and bandwidth and latency details related to
memory proximity domains. The info in the HMAT table can be used by an
operating system for optimisation.
Signed-off-by: Marc Moisson-Franckhauser <marc.moisson-franckhauser@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Tested-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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Bugzilla: 3048 (https://bugzilla.tianocore.org/show_bug.cgi?id=3048)
Add a new parser for the Arm Error Source Table (AEST) described in
the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document,
dated 28 September 2020.
(https://developer.arm.com/documentation/den0085/0101/)
AEST enables kernel-first handling of errors in a system that supports
the Armv8 RAS extensions. It covers Armv8.2+ RAS extensions for PEs
and the RAS system architecture for non-PE system components.
Signed-off-by: Marc Moisson-Franckhauser <marc.moisson-franckhauser@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
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