Tianocore/edk2.git - EDK II (mirror)

Age	Commit message (Collapse)	Author	Files	Lines
2024-01-11	MdePkg/BaseLib: RISC-V: Add function to update stimecmp register	Sunil V L	1	-0/+7
	stimecmp is a CSR supported only when Sstc extension is supported by the platform. This register can be used to set the timer interrupt directly in S-mode instead of going via SBI call. Add a function to update this register. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-02-16	MdePkg/BaseLib: RISC-V: Add few more helper functions	Sunil V L	1	-0/+23
	REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>