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Add a ParseCacheInfo() function, parsing CPU cache
information from Device Tree and creating
CM_ARCH_COMMON_CACHE_INFO objects.
Parse:
- L1 cache information directly from CPU cache properties
- shared caches from "next-level-cache" DT nodes
Track cache sharing through CPU masks and attach cache
references to the deepest matching processor hierarchy node.
The processor hierarchy objects must be added after the
cache information is parsed as cache references are stored
in ProcHierarchy objects.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Add a TopologyInfoParser() function, parsing the "/cpus"
node and the optional "cpu-map" hierarchy to create
CM_ARCH_COMMON_PROC_HIERARCHY_INFO objects.
When no "cpu-map" node is present, create a flat topology
with a single package node containing all CPUs.
Add the corresponding FDT HwInfo object identifier and hook
the new parser in ArmFdtHwInfoParser. The parser must be
called after the GIC parsers as leaf topology nodes point
to GicC objects.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Create Tokens identifying Gic CPU interfaces.
The Configuration Manager relies on PROC_HIERARCHY_INFO structures
to represent the CPU topology. These objects have fields:
- ParentToken: Token identifying the parent of this struct
- AcpiIdObjectToken: Token identifying a Gic CPU interface
(for arm)
The Gic CPU interface information and topology information
will be parsed in 2 different files. The same token will
have to be generated for:
- a GicC object
- the ProcHierarchy object pointing to this GicC object
Also add missing documentation in CpusNodeParser()
and add a CM_ABSTRACT_TOKEN_ID_MASK macro.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Move the Abstract Token related definitions to a separate
file in prevision of the addition of new definitions.
No functional change.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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