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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä1-1262/+1210
2015-11-18drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä1-1/+1
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä1-0/+8
2015-11-18drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä1-2/+18
2015-11-18drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä1-1/+2
2015-11-18drm/i915: Parametrize MOCS registersVille Syrjälä1-6/+6
2015-11-18drm/i915: Parametrize L3 error registersVille Syrjälä1-4/+2
2015-11-18drm/i915: Prefix raw register defines with underscoreVille Syrjälä1-131/+131
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson1-0/+1
2015-11-17drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson1-0/+4
2015-11-17drm/i915/gen9: simplify DC toggling codeImre Deak1-0/+1
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak1-1/+3
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä1-7/+8
2015-11-16drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä1-27/+27
2015-11-16drm/i915: Parametrize AUX registersVille Syrjälä1-50/+52
2015-11-10drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä1-1/+1
2015-11-09drm/i915: Add csr programming registers to dmc debugfs entryMika Kuoppala1-0/+10
2015-11-09drm/i915/bxt: Expose DC5 entry countMika Kuoppala1-0/+1
2015-11-09drm/i915/skl: Expose DC5/DC6 entry countsDamien Lespiau1-0/+4
2015-11-05drm/i915/skl: While sanitizing cdclock check the SWF18 as wellShobhit Kumar1-0/+1
2015-10-26drm/i915: Use paramtrized WRPLL_CTL()Ville Syrjälä1-1/+1
2015-10-13drm/i915: Parametrize and fix SWF registersVille Syrjälä1-14/+14
2015-10-13drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.Ville Syrjälä1-6/+6
2015-10-13drm/i915: Fix a few bad hex numbers in register definesVille Syrjälä1-2/+2
2015-10-13drm/i915: Protect register macro argumentsVille Syrjälä1-46/+46
2015-10-13drm/i915: Include gpio_mmio_base in GMBUS reg definesVille Syrjälä1-6/+6
2015-10-13drm/i915: Parametrize HSW video DIP data registersVille Syrjälä1-8/+8
2015-10-13drm/i915: Eliminate weird parameter inversion from BXT PPS registersVille Syrjälä1-4/+4
2015-10-07drm/i915/bxt: Set time interval unit to 0.833usAkash Goel1-1/+4
2015-10-06drm/i915: Add GEN7_GPGPU_DISPATCHDIMX/Y/Z to the register whitelistJordan Justen1-0/+4
2015-10-02drm/i915/bxt: Modify BXT BLC according to VBT changesSunil Kamath1-8/+20
2015-10-02drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma1-0/+62
2015-10-02drm/i915/bxt: DSI enable for BXTShashank Sharma1-0/+7
2015-10-02drm/i915: rename INSTDONE1 to GEN4_INSTDONE1Imre Deak1-1/+1
2015-10-02drm/i915: rename INSTDONE to GEN2_INSTDONEImre Deak1-1/+2
2015-10-02drm/i915: remove duplicate names for the render ring INSTDONE registerImre Deak1-2/+4
2015-10-01drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.Ville Syrjälä1-2/+2
2015-09-30drm/i915/bdw: Check for slice, subslice and EU count for BDWŁukasz Daniluk1-0/+18
2015-09-30drm/i915: Read czclk from CCK on vlv/chvVille Syrjälä1-0/+1
2015-09-30drm/i915: Renaming CCK related reg definitionsVandana Kannan1-5/+5
2015-09-30drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASEVille Syrjälä1-1/+7
2015-09-30drm/i915: Parametrize PALETTE and LGC_PALETTEVille Syrjälä1-3/+3
2015-09-30drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSRVille Syrjälä1-1/+1
2015-09-30drm/i915: Add LO/HI PRIVATE_PAT registersVille Syrjälä1-1/+2
2015-09-30drm/i915: Parametrize fence registersVille Syrjälä1-5/+13
2015-09-30drm/i915/bxt: Set oscaledcompmethod to enable scale valueSonika Jindal1-1/+2
2015-09-23drm/i915: Parametrize DDI_BUF_TRANS registersVille Syrjälä1-1/+2
2015-09-23drm/i915: Parametrize TV luma/chroma filter registersVille Syrjälä1-8/+4
2015-09-23drm/i915: Parametrize ILK turbo registersVille Syrjälä1-5/+5
2015-09-23drm/i915: Parametrize FBC_TAG registersVille Syrjälä1-1/+1
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