BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2017-11-10	dt-bindings: Remove leading zeros from bindings notation	Marco Franchi	1	-8/+8
2016-05-13	clk: sunxi: Add display and TCON0 clocks driver	Maxime Ripard	1	-0/+2
2016-04-22	clk: sunxi: Add TCON channel1 clock	Maxime Ripard	1	-0/+1
2016-04-22	clk: sunxi: Add PLL3 clock	Maxime Ripard	1	-0/+1
2016-04-22	dt-bindings: clk: sun5i: add DRAM gates compatible	Maxime Ripard	1	-0/+1
2016-04-22	clk: sunxi: Add sun6i/8i display support	Jean-Francois Moine	1	-0/+1
2016-02-25	clk: sunxi: Add apb0 gates for H3	Krzysztof Adamski	1	-0/+2
2016-02-02	clk: sunxi: add bus gates for A83T	Vishnu Patekar	1	-0/+1
2016-02-02	clk: sunxi: Add apb0 gates for A83T	Vishnu Patekar	1	-0/+1
2015-12-08	clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i	Chen-Yu Tsai	1	-0/+4
2015-12-08	clk: sunxi: Add H3 clocks support	Jens Kuske	1	-0/+2
2015-12-07	clk: sunxi: Add DRAM gates support for sun4i-a10	Chen-Yu Tsai	1	-0/+1
2015-12-01	clk: sunxi: Add sun9i A80 cpus (cpu special) clock support	Chen-Yu Tsai	1	-0/+1
2015-12-01	clk: sunxi: Add sun9i A80 apbs gates support	Chen-Yu Tsai	1	-0/+1
2015-11-20	clk: sunxi: Add support for the H3 usb phy clocks	Reinder de Haan	1	-0/+1
2015-06-02	clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCs	Hans de Goede	1	-0/+1
2015-03-21	clk: sunxi: Add muxable ahb factors clock for sun5i and sun7i	Chen-Yu Tsai	1	-0/+1
2015-02-23	clk: sunxi: Add support for sun9i A80 USB clocks and resets	Chen-Yu Tsai	1	-0/+2
2015-01-20	clk: sunxi: Add driver for A80 MMC config clocks/resets	Chen-Yu Tsai	1	-1/+24
2015-01-20	clk: sunxi: Add mod0 and mmc module clock support for A80	Chen-Yu Tsai	1	-2/+5
2015-01-14	clk: sunxi: Rework MMC phase clocks	Maxime Ripard	1	-5/+8
2014-12-22	clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider	Chen-Yu Tsai	1	-1/+1
2014-11-23	clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output	Chen-Yu Tsai	1	-2/+17
2014-11-23	clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver	Chen-Yu Tsai	1	-1/+0
2014-11-11	clk: sunxi: unify APB1 clock	Emilio López	1	-1/+0
2014-10-21	clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC	Chen-Yu Tsai	1	-0/+5
2014-10-21	clk: sunxi: Add support for A80 basic bus clocks	Chen-Yu Tsai	1	-0/+5
2014-09-27	clk: sunxi: Add sun8i MBUS clock support	Chen-Yu Tsai	1	-0/+1
2014-09-27	clk: sunxi: mod0: Introduce MMC proper phase handling	Maxime Ripard	1	-0/+2
2014-09-27	clk: sunxi: Introduce mbus compatible	Maxime Ripard	1	-0/+1
2014-07-15	clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support	Chen-Yu Tsai	1	-0/+1
2014-07-07	clk: sunxi: Add A23 APB0 divider clock support	Chen-Yu Tsai	1	-0/+1
2014-07-04	clk: sunxi: Add A23 clocks support	Chen-Yu Tsai	1	-0/+5
2014-06-11	clk: sunxi: document PRCM clock compatible strings	Boris BREZILLON	1	-0/+3
2014-06-11	clk: sunxi: document new A31 USB clock compatible	Emilio López	1	-0/+1
2014-02-18	clk: sunxi: Add new clock compatibles	Maxime Ripard	1	-18/+18
2014-02-18	clk: sunxi: Add Allwinner A20/A31 GMAC clock unit	Chen-Yu Tsai	1	-0/+30
2014-02-18	clk: sunxi: Add support for PLL6 on the A31	Maxime Ripard	1	-0/+1
2014-02-18	clk: sunxi: Add USB clock register defintions	Roman Byshko	1	-0/+5
2014-02-03	clk: sunxi: update clock-output-names dt binding documentation	Chen-Yu Tsai	1	-6/+26
2013-12-29	clk: sunxi: Allwinner A20 output clock support	Chen-Yu Tsai	1	-0/+1
2013-12-29	clk: sunxi: mod0 support	Emilio López	1	-1/+4
2013-12-29	clk: sunxi: add PLL5 and PLL6 support	Emilio López	1	-0/+2
2013-12-29	clk: sunxi: add gating support to PLL1	Emilio López	1	-1/+1
2013-10-11	Documentation: dt: Remove clock gates IDs list for Allwinner SoCs	Maxime Ripard	1	-2/+2
2013-08-26	clk: sunxi: Add Allwinner A20 gates	Maxime Ripard	1	-0/+3
2013-08-26	clk: sunxi: Add A31 clocks support	Maxime Ripard	1	-0/+6
2013-08-26	clk: sunxi: Add A10s gates	Maxime Ripard	1	-0/+3
2013-05-29	clk: sun5i: Add compatibles for Allwinner A13	Maxime Ripard	1	-104/+13
2013-04-05	clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates	Emilio López	1	-1/+108