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Diffstat (limited to 'Documentation/devicetree/bindings/power')
| -rw-r--r-- | Documentation/devicetree/bindings/power/fsl,imx-gpc.txt | 91 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml | 124 |
2 files changed, 124 insertions, 91 deletions
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt deleted file mode 100644 index f0f5553a9e74..000000000000 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt +++ /dev/null @@ -1,91 +0,0 @@ -Freescale i.MX General Power Controller -======================================= - -The i.MX6 General Power Control (GPC) block contains DVFS load tracking -counters and Power Gating Control (PGC). - -Required properties: -- compatible: Should be one of the following: - - fsl,imx6q-gpc - - fsl,imx6qp-gpc - - fsl,imx6sl-gpc - - fsl,imx6sx-gpc -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain one interrupt specifier for the GPC interrupt -- clocks: Must contain an entry for each entry in clock-names. - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - ipg - -The power domains are generic power domain providers as documented in -Documentation/devicetree/bindings/power/power-domain.yaml. They are described as -subnodes of the power gating controller 'pgc' node of the GPC and should -contain the following: - -Required properties: -- reg: Must contain the DOMAIN_INDEX of this power domain - The following DOMAIN_INDEX values are valid for i.MX6Q: - ARM_DOMAIN 0 - PU_DOMAIN 1 - The following additional DOMAIN_INDEX value is valid for i.MX6SL: - DISPLAY_DOMAIN 2 - The following additional DOMAIN_INDEX value is valid for i.MX6SX: - PCI_DOMAIN 3 - -- #power-domain-cells: Should be 0 - -Optional properties: -- clocks: a number of phandles to clocks that need to be enabled during domain - power-up sequencing to ensure reset propagation into devices located inside - this power domain -- power-supply: a phandle to the regulator powering this domain - -Example: - - gpc: gpc@20dc000 { - compatible = "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - }; - }; - }; - - -Specifying power domain for IP modules -====================================== - -IP cores belonging to a power domain should contain a 'power-domains' property -that is a phandle pointing to the power domain the device belongs to. - -Example of a device that is part of the PU power domain: - - vpu: vpu@2040000 { - reg = <0x02040000 0x3c000>; - /* ... */ - power-domains = <&pd_pu>; - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml new file mode 100644 index 000000000000..a055b3e819d8 --- /dev/null +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX General Power Controller + +maintainers: + - Philipp Zabel <p.zabel@pengutronix.de> + +description: | + The i.MX6 General Power Control (GPC) block contains DVFS load tracking + counters and Power Gating Control (PGC). + + The power domains are generic power domain providers as documented in + Documentation/devicetree/bindings/power/power-domain.yaml. They are + described as subnodes of the power gating controller 'pgc' node of the GPC. + + IP cores belonging to a power domain should contain a 'power-domains' + property that is a phandle pointing to the power domain the device belongs + to. + +properties: + compatible: + enum: + - fsl,imx6q-gpc + - fsl,imx6qp-gpc + - fsl,imx6sl-gpc + - fsl,imx6sx-gpc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ipg + + pgc: + type: object + description: list of power domains provided by this controller. + + patternProperties: + "power-domain@[0-9]$": + type: object + properties: + + '#power-domain-cells': + const: 0 + + reg: + description: | + The following DOMAIN_INDEX values are valid for i.MX6Q: + ARM_DOMAIN 0 + PU_DOMAIN 1 + The following additional DOMAIN_INDEX value is valid for i.MX6SL: + DISPLAY_DOMAIN 2 + The following additional DOMAIN_INDEX value is valid for i.MX6SX: + PCI_DOMAIN 3 + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled during domain + power-up sequencing to ensure reset propagation into devices located + inside this power domain. + minItems: 1 + maxItems: 7 + + power-supply: true + + required: + - '#power-domain-cells' + - reg + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - pgc + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpc@20dc000 { + compatible = "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_VPU_AXI>; + }; + }; + }; |