1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2023 keith.zhao@starfivetech.com
*/
#include <asm/gpio.h>
#include <asm/io.h>
#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <dw_hdmi.h>
#include <edid.h>
#include <regmap.h>
#include <syscon.h>
#include <power/regulator.h>
#include <linux/delay.h>
#include "sf_hdmi.h"
static int hdmi_read(struct sf_hdmi_priv *priv,uint32_t addr)
{
return readl(priv->base + (addr) * 0x04);
}
static void hdmi_write(struct sf_hdmi_priv *priv,int val, uint32_t addr)
{
writel(val, priv->base + (addr) * 0x04);
}
static void inno_hdmi_detect(struct sf_hdmi_priv *priv)
{
int val;
val = hdmi_read(priv,0x1b0);
val |= 0x4;
hdmi_write(priv,val, 0x1b0); //set 0x1b0[2] to 1'b1
hdmi_write(priv,0xf, 0x1cc); //set 0x1cc[3:0] to 4'b1111
//while(!(hdmi_read(0x1cd) == 0x55));
/*turn on pre-PLL*/
val = hdmi_read(priv,0x1a0);
val &= ~(0x1);
hdmi_write(priv,val, 0x1a0);
/*turn on post-PLL*/
val = hdmi_read(priv,0x1aa);
val &= ~(0x1);
hdmi_write(priv,val, 0x1aa);
/*wait for pre-PLL and post-PLL lock*/
while(!(hdmi_read(priv,0x1a9) & 0x1));
while(!(hdmi_read(priv,0x1af) & 0x1));
/*turn on LDO*/
hdmi_write(priv,0x7, 0x1b4);
/*turn on serializer*/
hdmi_write(priv,0x70, 0x1be);
}
static void inno_hdmi_tx_phy_power_down(struct sf_hdmi_priv *priv)
{
hdmi_write(priv,0x63, 0x00);
}
static void inno_hdmi_config_1440x480i60(struct sf_hdmi_priv *priv)
{
#ifdef REF_CLK_27M
const reg_value_t cfg_pll_data[] = {
/* config pll: 1440x480i, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x28},
{0x1a4, 0x35},
{0x1a5, 0x61},
{0x1a6, 0x64},
{0x1ab, 0x01},
{0x1ac, 0x28},
{0x1ad, 0x03},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#else
const reg_value_t cfg_pll_data[] = {
/* config pll: 1440x480i, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x64},
{0x1a4, 0x2f},
{0x1a5, 0x6c},
{0x1a6, 0x64},
{0x1ab, 0x01},
{0x1ac, 0x50},
{0x1ad, 0x07},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#endif
for (int i = 0; i < sizeof(cfg_pll_data)/sizeof(reg_value_t); i++) {
hdmi_write(priv, cfg_pll_data[i].value, cfg_pll_data[i].reg);
}
return;
}
static void inno_hdmi_config_640x480p60(struct sf_hdmi_priv *priv)
{
#ifdef REF_CLK_27M
const reg_value_t cfg_pll_data[] = {
/* config pll: 640x480p, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xc0},
{0x1a3, 0x25},
{0x1a4, 0x35},
{0x1a5, 0x61},
{0x1a6, 0x64},
{0x1ab, 0x01},
{0x1ac, 0x28},
{0x1ad, 0x03},
{0x1aa, 0x0e},
{0x1a0, 0x00},
{0x1d1, 0x55},
{0x1d2, 0x55},
{0x1d3, 0x55},
};
#else
const reg_value_t cfg_pll_data[] = {
/* config pll: 640x480p, 60hz*/
{0x1a0, 0x01},
//{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x64},
{0x1a4, 0x2f},
//{0x1a4, 0x2a},
{0x1a5, 0x6c},
{0x1a6, 0x64},
{0x1ab, 0x01},
{0x1ac, 0x50},
//{0x1ad, 0x07},
{0x1ad, 0x0d},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#endif
for (int i = 0; i < sizeof(cfg_pll_data)/sizeof(reg_value_t); i++) {
hdmi_write(priv, cfg_pll_data[i].value, cfg_pll_data[i].reg);
}
return;
}
static void inno_hdmi_config_720x480p60(struct sf_hdmi_priv *priv)
{
#ifdef REF_CLK_27M
const reg_value_t cfg_pll_data[] = {
/* config pll: 720x480p, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x28},
{0x1a4, 0x35},
{0x1a5, 0x61},
{0x1a6, 0x64},
{0x1ab, 0x01},
{0x1ac, 0x28},
{0x1ad, 0x03},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#else
const reg_value_t cfg_pll_data[] = {
/* config pll: 640x480p, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x64},
{0x1a4, 0x2f},
{0x1a5, 0x6c},
{0x1a6, 0x64},
{0x1ab, 0x01},
{0x1ac, 0x50},
{0x1ad, 0x07},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#endif
for (int i = 0; i < sizeof(cfg_pll_data)/sizeof(reg_value_t); i++) {
hdmi_write(priv,cfg_pll_data[i].value, cfg_pll_data[i].reg);
}
return;
}
static void inno_hdmi_config_1280x720p60(struct sf_hdmi_priv *priv)
{
#ifdef REF_CLK_27M
const reg_value_t cfg_pll_data[] = {
/* config pll: 720p, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x37},
{0x1a4, 0x30},
{0x1a5, 0x61},
{0x1a6, 0x42},
{0x1ab, 0x01},
{0x1ac, 0x14},
{0x1ad, 0x01},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#else
const reg_value_t cfg_pll_data[] = {
/* config pll: 720p, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x63},
//{0x1a4, 0x1f},
{0x1a4, 0x1a},
//{0x1a5, 0x48},
{0x1a5, 0x41},
{0x1a6, 0x64},
{0x1ab, 0x01},
{0x1ac, 0x14},
{0x1ad, 0x01},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#endif
for (int i = 0; i < sizeof(cfg_pll_data)/sizeof(reg_value_t); i++) {
hdmi_write(priv, cfg_pll_data[i].value, cfg_pll_data[i].reg);
}
return;
}
static void inno_hdmi_config_1920x1080p60(struct sf_hdmi_priv *priv)
{
#ifdef REF_CLK_27M
const reg_value_t cfg_pll_data[] = {
/* config pll: 1080p, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x6e},
{0x1a4, 0x30},
{0x1a5, 0x60},
{0x1a6, 0x42},
{0x1ab, 0x04},
{0x1ac, 0x50},
{0x1ad, 0x01},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#else
const reg_value_t cfg_pll_data[] = {
/* config pll: 1080p, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x63},
{0x1a4, 0x15},
{0x1a5, 0x41},
{0x1a6, 0x42},
{0x1ab, 0x01},
//{0x1ac, 0x0a},
{0x1ac, 0x14},
//{0x1ad, 0x00},
{0x1ad, 0x01},
{0x1aa, 0x0e},
{0x1a0, 0x00},
};
#endif
for (int i = 0; i < sizeof(cfg_pll_data)/sizeof(reg_value_t); i++) {
hdmi_write(priv, cfg_pll_data[i].value, cfg_pll_data[i].reg);
}
return;
}
static void inno_hdmi_config_3840x2160p60(struct sf_hdmi_priv *priv)
{
#ifdef REF_CLK_27M
const reg_value_t cfg_pll_data[] = {
/* config pll: 4K, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x63},
{0x1a4, 0x08},
{0x1a5, 0x01},
{0x1a6, 0x21},
{0x1ab, 0x04},
{0x1ac, 0x14},
{0x1ad, 0x00},
{0x1aa, 0x02},
{0x1a0, 0x00},
};
#else
const reg_value_t cfg_pll_data[] = {
/* config pll: 4K, 60hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x63},
{0x1a4, 0x08},
{0x1a5, 0x01},
{0x1a6, 0x21},
{0x1ab, 0x04},
{0x1ac, 0x14},
{0x1ad, 0x00},
{0x1aa, 0x02},
{0x1a0, 0x00},
};
#endif
for (int i = 0; i < sizeof(cfg_pll_data)/sizeof(reg_value_t); i++) {
hdmi_write(priv, cfg_pll_data[i].value, cfg_pll_data[i].reg);
}
return;
}
static void inno_hdmi_config_3840x2160p30(struct sf_hdmi_priv *priv)
{
#ifdef REF_CLK_27M
const reg_value_t cfg_pll_data[] = {
/* config pll: 4K, 30hz*/
{0x1a0, 0x01},
{0x1aa, 0x03},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x58},
{0x1a4, 0x10},
{0x1a5, 0x41},
{0x1a6, 0x21},
{0x1ab, 0x04},
{0x1ac, 0x14},
{0x1ad, 0x00},
{0x1aa, 0x02},
{0x1a0, 0x00},
};
#else
const reg_value_t cfg_pll_data[] = {
/* config pll: 4K, 30hz*/
{0x1a0, 0x01},
{0x1aa, 0x0f},
{0x1a1, 0x01},
{0x1a2, 0xf0},
{0x1a3, 0x63},
{0x1a4, 0x10},
{0x1a5, 0x41},
{0x1a6, 0x21},
{0x1ab, 0x04},
{0x1ac, 0x14},
{0x1ad, 0x00},
{0x1aa, 0x02},
{0x1a0, 0x00},
};
#endif
for (int i = 0; i < sizeof(cfg_pll_data)/sizeof(reg_value_t); i++) {
hdmi_write(priv, cfg_pll_data[i].value, cfg_pll_data[i].reg);
}
return;
}
static void inno_hdmi_tx_ctrl(struct sf_hdmi_priv *priv,vic_code_t vic)
{
hdmi_write(priv, 0x06, 0x9f);
hdmi_write(priv, 0x82, 0xa0);
hdmi_write(priv, 0xd, 0xa2);
hdmi_write(priv, 0x0, 0xa3);
hdmi_write(priv, 0x0, 0xa4);
hdmi_write(priv, 0x8, 0xa5);
hdmi_write(priv, 0x70, 0xa6);
hdmi_write(priv, vic, 0xa7); //conifg video format Identification Code
hdmi_write(priv, 0x10, 0xc9); //bist mode: 0x00, normal mode: 0x10, phy mode: 0x4
}
static void inno_hdmi_tx_phy_param_config(struct sf_hdmi_priv *priv,resolution_t type)
{
vic_code_t vic;
switch(type) {
case RES_1440_480I_60HZ:
vic = VIC_1440x480i60;
inno_hdmi_config_1440x480i60(priv);
break;
case RES_640_480P_60HZ:
vic = VIC_640x480p60;
inno_hdmi_config_640x480p60(priv);
break;
case RES_720_480P_60HZ:
vic = VIC_720x480p60;
inno_hdmi_config_720x480p60(priv);
break;
case RES_1280_720P_60HZ:
vic = VIC_1280x720p60;
inno_hdmi_config_1280x720p60(priv);
break;
case RES_1920_1080P_60HZ:
vic = VIC_1920x1080p60;
inno_hdmi_config_1920x1080p60(priv);
break;
case RES_3840_2160P_30HZ:
vic = VIC_3840x2160p30;
inno_hdmi_config_3840x2160p30(priv);
break;
case RES_3840_2160P_60HZ:
vic = VIC_3840x2160p60;
inno_hdmi_config_3840x2160p60(priv);
break;
}
inno_hdmi_tx_ctrl(priv, vic);
return;
}
static void inno_hdmi_tx_phy_power_on(struct sf_hdmi_priv *priv)
{
hdmi_write(priv, 0x61, 0x00); //0x61: power 0n, 0x63: power off
}
static void inno_hdmi_data_sync(struct sf_hdmi_priv *priv)
{
hdmi_write(priv, 0x00, 0xce);
hdmi_write(priv, 0x01, 0xce);
}
void inno_hdmi_tmds_driver_on(struct sf_hdmi_priv *priv)
{
hdmi_write(priv, 0x8f, 0x1b2);
mdelay(50);
}
static int inno_hdmi_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *edid)
{
struct sf_hdmi_priv *priv = dev_get_priv(dev);
debug("inno_hdmi_enable on\r\n");
inno_hdmi_detect(priv);
inno_hdmi_tx_phy_power_down(priv);
inno_hdmi_tx_phy_param_config(priv,RES_1920_1080P_60HZ);
inno_hdmi_tx_phy_power_on(priv);
inno_hdmi_tmds_driver_on(priv);
/*data sync*/
inno_hdmi_data_sync(priv);
return 0;
}
int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
{
//need fix next
return 0;
}
static int inno_hdmi_of_to_plat(struct udevice *dev)
{
struct sf_hdmi_priv *priv = dev_get_priv(dev);
int ret;
priv->base = dev_remap_addr(dev);
if (!priv->base)
return -EINVAL;
debug("%s----priv->base = %px\n",__func__,priv->base);
ret = clk_get_by_name(dev, "sysclk", &priv->sys_clk);
if (ret) {
pr_err("clk_get_by_name(sysclk) failed: %d", ret);
return ret;
}
ret = clk_get_by_name(dev, "mclk", &priv->mclk);
if (ret) {
pr_err("clk_get_by_name(mclk) failed: %d\n", ret);
return ret;
}
ret = clk_get_by_name(dev, "bclk", &priv->bclk);
if (ret) {
pr_err("clk_get_by_name(bclk) failed: %d\n", ret);
return ret;
}
ret = reset_get_by_name(dev, "hdmi_tx", &priv->tx_rst);
if (ret) {
pr_err("failed to get hdmi_tx reset (ret=%d)\n", ret);
return ret;
}
return 0;
}
static int inno_hdmi_probe(struct udevice *dev)
{
struct sf_hdmi_priv *priv = dev_get_priv(dev);
int ret;
ret = clk_enable(&priv->sys_clk);
if (ret < 0) {
pr_err("clk_enable(sys_clk) failed: %d\n", ret);
return ret;
}
ret = clk_enable(&priv->mclk);
if (ret < 0) {
pr_err("clk_enable(mclk) failed: %d\n", ret);
goto free_clock_sys_clk;
}
ret = clk_enable(&priv->bclk);
if (ret < 0) {
pr_err("clk_enable(bclk) failed: %d\n", ret);
goto free_clock_mclk_clk;
}
ret = reset_deassert(&priv->tx_rst);
if (ret < 0) {
pr_err("failed to deassert tx_rst\n");
goto free_reset;
}
ret = (hdmi_read(priv, HDMI_STATUS) & m_HOTPLUG) ? 0 : 1; // 0 connected.. 1 disconnected
debug("ret = %d\n",ret);
return ret;
free_reset:
clk_disable(&priv->bclk);
free_clock_mclk_clk:
clk_disable(&priv->mclk);
free_clock_sys_clk:
clk_disable(&priv->sys_clk);
return ret;
}
static int sf_hdmi_remove(struct udevice *dev)
{
struct sf_hdmi_priv *priv = dev_get_priv(dev);
debug("sf_hdmi_remove ---\n");
hdmi_write(priv, 0x00,0x1b2);
hdmi_write(priv, 0x00,0x1be);
hdmi_write(priv, 0x00,0x1b4);
hdmi_write(priv, 1,0x1a0);
hdmi_write(priv, 1,0x1aa);
hdmi_write(priv, 0x00,0x1cc);
hdmi_write(priv, 0x00,0x1b0);
clk_disable(&priv->bclk);
clk_disable(&priv->mclk);
clk_disable(&priv->sys_clk);
reset_assert(&priv->tx_rst);
return 0;
}
static const struct dm_display_ops inno_hdmi_ops = {
.read_edid = rk_hdmi_read_edid,
.enable = inno_hdmi_enable,
};
static const struct udevice_id inno_hdmi_ids[] = {
{ .compatible = "starfive,inno-hdmi" },
{ }
};
U_BOOT_DRIVER(inno_hdmi_starfive) = {
.name = "inno_hdmi_starfive",
.id = UCLASS_DISPLAY,
.of_match = inno_hdmi_ids,
.ops = &inno_hdmi_ops,
.of_to_plat = inno_hdmi_of_to_plat,
.probe = inno_hdmi_probe,
.priv_auto = sizeof(struct sf_hdmi_priv),
.remove = sf_hdmi_remove,
.flags = DM_FLAG_OS_PREPARE,
};
|
