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2021-09-22x86: tangier: acpi: Add GPIO card detection to SDHCI #2Andy Shevchenko1-0/+32
On Intel Tangier the SDHCI #2 provides SD card connection. Add GPIO card detection for it. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-08-17efi_loader rename enum efi_mem_type to efi_memory_typeHeinrich Schuchardt1-1/+1
Use the same name as in the UEFI specification to avoid confusion. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-08-02x86: mtrr: Abort if requested size is not power of 2Bin Meng1-3/+4
The size parameter of mtrr_add_request() and mtrr_set_next_var() shall be power of 2, otherwise the logic creates a mask that does not meet the requirement of IA32_MTRR_PHYSMASK register. Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-07-15x86: Add function comments to cb_sysinfo.hSimon Glass1-0/+16
Add a function comment for get_coreboot_info() and a declaration for cb_get_sysinfo(), since this may be called from elsewhere. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: Update the MP constants to avoid conflictsSimon Glass1-4/+8
These constants conflict with error codes returned by the MP implementation when something is wrong. In particular, mp_first_cpu() returns MP_SELECT_BSP when running without multiprocessing enabled. Since this is -2, it is interpreted as an error by callers, which expect a positive CPU number for the first CPU. Correct this by using a different range for the pre-defined CPU numbers, above zero and out of the range of possible CPU values. For now it is safe to assume there are no more than 64K CPUs. This fixes the 'mtrr' command when CONFIG_SMP is not enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-22lmb: move CONFIG_LMB in KconfigPatrick Delaunay1-1/+0
Migrate CONFIG_LMB in Kconfig. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-04-15x86: mtrr: Fix function descriptionsWolfgang Wallner1-2/+2
Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set(). Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-27x86: coral: Allow init of debug UART in U-Boot properSimon Glass1-0/+1
At present the debug UART is only set up in SPL, on the assumption that the boot flow will always pass through there. When booting from coreboot, SPL is not used, so the debug UART is not available. Move the code into a common place so that it can be used in U-Boot proper also. Add the required init to start_from_spl.S as well. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Allow installing an e820 when booting from corebootSimon Glass1-1/+15
Move this code into a generic location so that it can be used by other x86 boards which want to boot from coreboot. Also ensure that this is called if booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coreboot: Update parsing of the latest sysinfoSimon Glass2-35/+290
Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coreboot: Sync up timestamp codesSimon Glass1-1/+63
Add new timestamp codes that are present in coreboot, so that we can decode these in U-Boot. At present TS_U_BOOT_START_KERNEL is used twice. It should only be used just before jumping to Linux, so update the other call site to use TS_START_KERNEL. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Move coreboot timestamp info into coreboot_tables.hSimon Glass2-24/+39
This all relates to the sysinfo structure provided by coreboot. Put the timestamp definitions into the same file as the others. Tidy up a few comments at the same time. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Make coreboot sysinfo available to any x86 boardSimon Glass1-0/+0
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or from coreboot. In the latter case we want to provide access to the coreboot sysinfo tables. Move the definitions into a file available to any x86 board. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15Merge tag 'v2021.04-rc4' into nextTom Rini1-0/+4
Prepare v2021.04-rc4
2021-03-09x86: Fix member check in intel_gnvsSimon Glass1-0/+4
When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-03gpio: x86: Drop the deprecated methods in intel_gpioSimon Glass1-0/+5
We don't need to implement direction_input() and direction_output() anymore. Drop them and use update_flags() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass7-2/+14
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-01x86: zimage: Allow dumping the image from outside the moduleSimon Glass1-0/+10
At present it is possible to dump an image within the zimage command, but it is also useful to be able to dump it from elsewhere, for example in a loader that has special handling for the different zimage stages. Export this feature as a new function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: Update Chromium OS GNVS namesSimon Glass1-6/+28
The Global Non-Volatile Storage struct has some fields with particular meanings. Rename these to make things easier to follow. Also add a few more boot flags. GNVS should not be confused with GNVQ (Going Nowhere Very Quickly). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-01-31x86: coral: Support TPM and RTC in SPLSimon Glass1-0/+3
Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: apl: Adjust how the UART gets its platform dataSimon Glass1-1/+18
At present this driver calls malloc() to start a new platform data structure, fills it in and tells driver model to use it. We want to avoid malloc, particularly with the new version of of-platdata. Create a new struct which encompasses both the dtd struct and the ns16550 one, to avoid this. Unfortunately we must copy the data into the right place for the ns16550 driver. Add some comments about this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: sysreset: Move priv/plat structs to headersSimon Glass1-0/+18
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them and add the dtd struct too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05x86: Move priv/plat structs for intel_common to headersSimon Glass2-0/+39
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: apl: Move priv/plat structs to headersSimon Glass3-0/+62
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: Fix header guard in asm/pmu.hSimon Glass1-3/+3
This has the wrong name. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-31fsp: Move and rename fsp_types.h fileSughosh Ganu2-63/+2
The fsp_types.h header file contains macros for building signatures of different widths. These signature macros are architecture agnostic, and can be used in all places which use signatures in a data structure. Move and rename the fsp_types.h under the common include header. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-12-19x86: Drop unnecessary mp_init logicSimon Glass1-1/+1
Now that sequence numbers are set up when devices are bound, this code is not needed. Also, we should use dev_seq() instead of req_seq. Update the whole file accordingly. Also fix up APL cpu while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2-2/+2
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass1-4/+3
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass1-1/+1
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-11-06x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass1-3/+0
At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06x86: Define the Chrome OS GNVS regionSimon Glass1-1/+50
It is not possible to boot Chrome OS properly without passing some basic information from U-Boot. This applies even if verified boot is not being used. Add a structure definition for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06x86: Show the interrupt pointer with 'irqinfo'Simon Glass1-0/+17
It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: Allow writing tables to failSimon Glass1-1/+3
At present write_tables() can fail but does not report this problem to its caller. Fix this by changing the return type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: Add a layout for Chrome OS verified bootSimon Glass1-0/+38
Add definitions for part of the vboot context used with verified boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: apl: Add core init for the SoCSimon Glass3-1/+42
Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Add support for more than 8 MTRRsSimon Glass1-3/+12
At present the mtrr command only support 8 MTRRs. Some SoCs have more than that. Update the implementation to support up to 10. Read the number of MTRRs dynamically instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: hob: Try to show a name instead of a GUIDSimon Glass1-0/+25
GUIDs are one of the seven evils of the computer world. They obfuscate the meaning and require people to look up long hex strings to decode it. Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use. Add a way to decode the GUIDs known to U-Boot. Add a few more to the list for good measure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Add a header guard to asm/acpi_table.hSimon Glass1-0/+4
This file cannot currently be included in ASL files. Add a header guard to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Correct the assembly guard in e820.hSimon Glass1-2/+1
This is currently in the wrong place, so including the file in the device tree fails. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: cpu: Report address width from cpu_get_info()Simon Glass1-0/+9
Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: fsp: Update the FSP API with the end-firmware methodSimon Glass1-3/+12
This new method is intended to be called when UEFI shuts down the 'boot services', i.e. any lingering code in the boot loader that might be used by the OS. Add a definition for this new method and update the comments a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: apl: Generate required ACPI tablesSimon Glass1-0/+18
Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Allow reading hostbridge base addressesSimon Glass1-0/+31
Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add support for additional Intel tablesSimon Glass1-0/+115
Apollo Lake needs to generate a few more table types used on Intel SoCs. Add support for these into the x86 ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add common Intel ACPI tablesSimon Glass3-0/+81
Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add PCT and PTC tablesSimon Glass1-0/+35
These are needed for the CPU tables. Add them into an x86-specific file since we do not support them on sandbox, or include tests. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support generation of the DBG2 tableSimon Glass1-0/+11
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table. Adjust one of the header includes to be in the correct order, before adding more. Note that the DBG2 table is generic but the PCI UART is x86-specific at present since it assumes an ns16550 UART. It can be generalised later if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support generation of the HPET tableSimon Glass1-0/+10
Add an implementation of the HPET (High Precision Event Timer) ACPI table. Since this is x86-specific, put it in an x86-specific file Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a few common Intel CPU functionsSimon Glass1-0/+49
Add functions to query CPU information, needed for ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-14 21:41:51 +0300