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2025-08-25eeprom: starfive: Add function get_mmc_size_from_eeprom()Hal Feng1-0/+1
Export a function get_mmc_size_from_eeprom() to read the eMMC size. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2025-08-11board: starfive: visionfive2: Move get_vf2_board_type() to eeprom driverHal Feng1-0/+1
Move get_vf2_board_type() to eeprom driver and export it. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2025-07-30cmd: fastboot: Switch to usb device through rgpio0 when using CM / Lite boardHal Feng1-0/+12
rgpio0 output high level for switching to usb device when running usb fastboot in CM / Lite board. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2025-06-09eeprom: starfive: Add function get_product_id_from_eeprom()Hal Feng1-0/+1
Export a function get_product_id_from_eeprom() to read the product ID. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-04-26spl: amp: Enable UART2 and move rtos image to memoryMinda Chen1-0/+3
Enable UART2 for rtos and move rtos image to running memory. The image size is 832KB. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-11-29riscv: cpu: jh7110: Add EEPROM supportHal Feng1-0/+14
Add a header to easily use the EEPROM interface. The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-07-26gpio: starfive: Add SET_DS/SET_PULL/SET_SLEW supportSamin Guo1-1/+23
SET_DS/SET_PULL/SET_SLEW can configure the properties of the GPIO Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang4-4/+4
Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-02-02sysreset: provide SBI based sysreset driverHeinrich Schuchardt1-0/+1
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-02-02riscv: add missing SBI extension definitionsHeinrich Schuchardt1-2/+37
Add the System Reset Extension and the Hart State Management Extension definitions. Add missing RFENCE Extension enum values. The SBI 0.1 extension constants are needed for the sbi command. Remove an #ifdef. Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-11-01board:starfive:evb: add get_chip_typeSamin Guo1-0/+2
Read the chip model from the rgpio3 and setenv "chip_vision" 1: jh7110B 0: JH7110A defalut: JH7110A Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmiiSamin Guo1-0/+8
JH7110B needs switch gmac0/1 tx to rgmii phy. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18arch: riscv: jh7110: add pll clk configuration for jh7110Yan Hong Wang2-18/+36
Add common interface to set and get pll clk information for jh7110 soc. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:starfive-jh7110: Modify the default division factor of sdcard clkyanhong.wang1-0/+4
Modify the default division factor of sdcard clk to 4. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: add usb init configyanhong.wang1-0/+18
Add usb init config for starfive EVB board. Default set to USB2.0 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18spl: satrfive: bus_root switch to pll2.samin1-5/+0
High-speed emmc/sdio support Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18board:starfive:evb: modify the GPIO configuration for sd moduleyanhong.wang1-0/+5
Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc to high frequency Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:riscv:starfive-jh7110: Adjust CPU working frequencyyanhong.wang1-0/+17
Adjust CPU working frequency from 1G to 1.25G for starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add clk inityanhong.wang1-5/+27
Add clk init for ddr on JH7110 board Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add macro definitionyanhong.wang1-0/+21
Add macro definition of GPIO Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add rtc timer inityanhong.wang1-0/+16
The rtc timer is used early in kernel, but the clk&reset driver is not ready,so some clk&reset init is placed here. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive visionfive board supportyanhong.wang1-0/+45
Add board support for StarFive VisionFive. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang1-0/+14
Add StarFive JH7110 soc to support RISC-V arch Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang1-0/+53
Support for GPIO controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-09-07riscv: lib: modify the indentZong Li1-1/+1
We usually use a space in function declaration, rather than a tab. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07board: sifive: use ccache driver instead of helper functionZong Li2-28/+0
Invokes the common cache_init function to initialize ccache. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-07-06board: sifive: Add an interface to get PCB revisionZong Li1-0/+15
There are different DDR parameter settings for different board revisions. Add a new interface to get the PCB revision to determine which DT should be selected at runtime. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan5-0/+93
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-17riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng1-1/+1
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-04-22lmb: move CONFIG_LMB in KconfigPatrick Delaunay1-1/+0
Migrate CONFIG_LMB in Kconfig. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-04-08riscv: assembler versions of memcpy, memmove, memsetHeinrich Schuchardt1-21/+15
Provide optimized versions of memcpy(), memmove(), memset() copied from the Linux kernel. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-02-03riscv: Change phys_addr_t and phys_size_t to 64-bitBin Meng1-2/+2
phys_addr_t and phys_size_t are currently defined as `unsigned long`, but RV32 supports 34-bit physical address, hence both phys_addr_t and phys_size_t should be defined to 64-bit using `unsigned long long`. Signed-off-by: Bin Meng <bin.meng@windriver.com>
2021-01-18riscv: Add DMA 64-bit address supportPadmarao Begari1-0/+4
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2-2/+2
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-30riscv: Use a valid bit to ignore already-pending IPIsSean Anderson1-0/+7
Some IPIs may already be pending when U-Boot is started. This could be a problem if a secondary hart tries to handle an IPI before the boot hart has initialized the IPI device. To be specific, the Kendryte K210 ROM-based bootloader does not clear IPIs before passing control to U-Boot. Without this patch, the secondary hart jumps to address 0x0 as soon as it enters secondary_hart_loop, and then hangs in its trap handler. This commit introduces a valid bit so secondary harts know when and IPI originates from U-Boot, and it is safe to use the IPI API. The valid bit is initialized to 0 by board_init_f_init_reserve. Before this, secondary harts wait in wait_for_gd_init. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-09-30riscv: Rework Andes PLMT as a UCLASS_TIMER driverSean Anderson2-5/+2
This converts the PLMT driver from the riscv-specific timer interface to be a DM-based UCLASS_TIMER driver. The clock-frequency/clocks properties are preferred over timebase-frequency for two reasons. First, properties which affect a device should be located near its binding in the device tree. Using timebase-frequency only really makes sense when the cpu itself is the timer device. This is the case when we read the time from a CSR, but not when there is a separate device. Second, it lets the device use the clock subsystem which adds flexibility. If the device is configured for a different clock speed, the timer can adjust itself. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-15riscv: define function set_gd()Heinrich Schuchardt1-0/+9
Function set_gd() is needed in the UEFI sub-system if the global data pointer is stored in a register. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-25cmd: provide command sbiHeinrich Schuchardt1-0/+2
Provide a command to display information about the SBI implementation. The output might look like: => sbi SBI 0.2 OpenSBI Extensions: sbi_set_timer sbi_console_putchar sbi_console_getchar sbi_clear_ipi sbi_send_ipi sbi_remote_fence_i sbi_remote_sfence_vma sbi_remote_sfence_vma_asid sbi_shutdown SBI Base Functionality Timer Extension IPI Extension RFENCE Extension Hart State Management Extension The command can be used to construct a unit test checking that the communication with the SEE is working. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com> Tested-by: Pragnesh Patel <pragnesh.patel@openfive.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
2020-08-14riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng1-1/+1
spl_soc_init() seems to be a better name, as all SPL functions names start from the spl_ prefix. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14riscv: Call spl_board_init_f() in the generic SPL board_init_f()Bin Meng1-0/+7
The generic SPL version of board_init_f() should give a call to board specific codes to initialize board in the SPL phase. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-04sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam1-0/+13
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-06Merge branch 'next'Tom Rini4-17/+87
Merge all outstanding changes from the current next branch in now that we have released.
2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel1-0/+14
Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson1-0/+40
Some older processors (notably the Kendryte K210) use an older version of the RISC-V privileged specification. The primary changes between the old and new are in virtual memory, and in the merging of three separate counter enable CSRs. Using the new CSR on an old processor causes an illegal instruction exception. This patch adds an option to use the old CSRs instead of the new one. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01riscv: Clean up IPI initialization codeSean Anderson1-0/+43
The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-01riscv: Add headers for asm/global_data.hSean Anderson1-0/+2
This header depended on bd_t and ulong, but did not include the appropriate headers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-25bdinfo: riscv: Use generic bd_infoSimon Glass1-17/+2
At present riscv still uses its own private bd_info struct. Move it over to use the generic one like other archs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04riscv: sbi: Remove sbi_spec_versionBin Meng1-2/+0
U-Boot defaults to use SBI v0.2. Howerver there is a global variable sbi_spec_version that stills refers to v0.1. Since it is not used anywhere, let's remove it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-06-04riscv: sifive: fu540: add SPL configurationPragnesh Patel1-0/+14
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel2-0/+52
Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-09-30 01:59:01 +0300