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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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arch
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riscv
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cpu
Age
Commit message (
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Author
Files
Lines
2019-01-15
riscv: move the AX25-specific implementation of flush_dcache_all
Lukas Auer
1
-0
/
+22
2018-12-18
riscv: Save boot hart id to the global data
Bin Meng
1
-0
/
+4
2018-12-18
riscv: Return to previous privilege level after trap handling
Bin Meng
1
-8
/
+0
2018-12-18
riscv: Fix context restore before returning from trap handler
Bin Meng
1
-1
/
+1
2018-12-18
riscv: Move trap handler codes to mtrap.S
Bin Meng
3
-90
/
+112
2018-12-18
riscv: Do some basic architecture level cpu initialization
Bin Meng
1
-1
/
+26
2018-12-18
riscv: Update supports_extension() to use desc from cpu driver
Bin Meng
1
-0
/
+26
2018-12-18
riscv: Remove non-DM version of print_cpuinfo()
Bin Meng
1
-37
/
+0
2018-12-18
riscv: Probe cpus during boot
Bin Meng
2
-0
/
+27
2018-12-18
riscv: qemu: Add platform-specific Kconfig options
Bin Meng
1
-0
/
+11
2018-12-18
riscv: ax25: Hide the ax25-specific Kconfig option
Bin Meng
2
-11
/
+18
2018-12-18
riscv: qemu: Create a simple-bus driver for the soc node
Bin Meng
1
-0
/
+14
2018-12-05
riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
Rick Chen
1
-2
/
+0
2018-12-05
riscv: Add kconfig option to run U-Boot in S-mode
Anup Patel
1
-8
/
+15
2018-11-26
riscv: cache: Implement i/dcache [status, enable, disable]
Rick Chen
6
-1
/
+114
2018-11-26
riscv: save hart ID and device tree passed by prior boot stage
Lukas Auer
2
-2
/
+16
2018-11-26
riscv: do not blindly modify the mstatus CSR
Lukas Auer
1
-4
/
+4
2018-11-26
riscv: remove unused labels in start.S
Lukas Auer
1
-9
/
+0
2018-11-26
Drop CONFIG_INIT_CRITICAL
Bin Meng
1
-13
/
+0
2018-11-26
riscv: align mtvec on a 4-byte boundary
Lukas Auer
1
-1
/
+1
2018-11-26
riscv: fix inconsistent use of spaces and tabs in start.S
Lukas Auer
1
-161
/
+161
2018-10-03
riscv: Move do_reset() to a common place
Bin Meng
2
-17
/
+0
2018-10-03
riscv: Add QEMU virt board support
Bin Meng
3
-0
/
+52
2018-10-03
riscv: Make start.S available for all targets
Bin Meng
4
-3
/
+3
2018-10-03
riscv: Add a helper routine to print CPU information
Bin Meng
2
-0
/
+54
2018-10-03
riscv: Fix coding style issues in the linker script
Bin Meng
1
-30
/
+28
2018-10-03
riscv: Move the linker script to the CPU root directory
Bin Meng
1
-0
/
+0
2018-08-20
riscv: Include bss subsections in linker script
Alexander Graf
1
-1
/
+1
2018-07-25
efi_loader: Rename sections to allow for implicit data
Alexander Graf
1
-10
/
+16
2018-05-29
riscv: cpu: nx25: Rename as ax25
Rick Chen
4
-2
/
+2
2018-05-29
efi_loader: Enable RISC-V support
Rick Chen
1
-0
/
+16
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
4
-9
/
+4
2018-03-30
riscv: ae250: Support DT provided by the board at runtime
Rick Chen
1
-0
/
+2
2018-01-12
riscv: cpu: Add nx25 to support RISC-V
Rick Chen
4
-0
/
+403