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path: root/arch/riscv/cpu/jh7110
AgeCommit message (Expand)AuthorFilesLines
2023-07-20board: starfive: evb: use dram_init in splSamin Guo2-1/+7
2023-07-18dram: jh7110: remove resize-ddr functionSamin Guo1-40/+10
2023-07-10dram: starfive: jh7110: Add 1G supportSamin Guo1-0/+1
2023-07-10dram: jh7110: Add CONFIG_ID_EEPROM to determine if EEPROM is availableSamin Guo1-18/+26
2023-07-10dram: jh7110: Macro definitions STARFIVE_JH7110_EEPROM_DDRINFO_OFFSETSamin Guo1-1/+2
2023-06-25dram: jh7110: Add resize DDR info from EEPROM.Samin Guo1-2/+47
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang2-2/+2
2023-02-21riscv:uboot:cache driverkeith.zhao1-1/+1
2023-02-17riscv:cache:jh7110: add cache driverkeith.zhao3-0/+66
2022-12-14board:starfive:jh7110: default cpufreq is 1000Mhz.Samin Guo1-1/+1
2022-10-18arch: riscv: jh7110: add pll clk configuration for jh7110Yan Hong Wang2-0/+380
2022-10-18riscv:starfive-jh7110: clear L2 LIM memoryyanhong.wang1-0/+14
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang5-0/+165